19-2878; Rev 1; 5/07
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
The MAX9394/MAX9395 consist of a 2:1 multiplexer
and a 1:2 demultiplexer with loopback. The multiplexer
section (channel B) accepts two low-voltage differential
signaling (LVDS) inputs and generates a single LVDS
output. The demultiplexer section (channel A) accepts
a single LVDS input and generates two parallel LVDS
outputs. The MAX9394/MAX9395 feature a loopback
mode that connects the input of channel A to the output
of channel B and connects the selected input of channel B to the outputs of channel A.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the commonmode voltage exceeds the specified range. The
MAX9394 provides high-level input fail-safe detection
for HSTL, LVDS, and other GND-referenced differential
inputs. The MAX9395 provides low-level fail-safe detection for CML, LVPECL, and other VCC-referenced differential inputs.
Ultra low 91psP-P (max) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in highspeed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switching performance guarantees 1.5GHz operation and less
than 87ps (max) skew between channels.
LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS outputs drive
100Ω loads. The MAX9394/MAX9395 are offered in a
32-pin TQFP package and operate over the extended
temperature range (-40°C to +85°C).
Features
♦ Guaranteed 1.5GHz Operation with 250mV
Differential Output Swing
♦ Simultaneous Loopback Control
♦ 2ps(RMS) (max) Random Jitter
♦ AC Specifications Guaranteed for 150mV
Differential Input
♦ Signal Inputs Accept Any Differential Signaling
Standard
♦ LVDS Outputs for Clock or High-Speed Data
♦ High-Level Input Fail-Safe Detection (MAX9394)
♦ Low-Level Input Fail-Safe Detection (MAX9395)
♦ 3.0V to 3.6V Supply Voltage Range
♦ LVCMOS/LVTTL Logic Inputs
Ordering Information
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX9394EHJ
-40°C to +85°C
32 TQFP
H32-1
MAX9394EHJ+
-40°C to +85°C
32 TQFP
H32-1
MAX9395EHJ
-40°C to +85°C
32 TQFP
H32-1
MAX9395EHJ+
-40°C to +85°C
32 TQFP
H32-1
PART
+Denotes a lead-free package.
Typical Operating Circuit
3.0V TO
3.6V
0.1μF
0.01μF
Z0 = 50Ω
INA
VCC
Z0 = 50Ω
Applications
Z0 = 50Ω
OUTA0
Z0 = 50Ω
OUTA1
Z0 = 50Ω
OUTA1
Z0 = 50Ω
OUTB
Z0 = 50Ω
OUTB
Z0 = 50Ω
100Ω
MAX9394
MAX9395
INA
INB0
LVDS
RECEIVER
INB0
High-Speed Telecom/Datacom Equipment
INB1
Central Office Backplane Clock Distribution
INB1
DSLAM
ENA0
Protection Switching
ENA1
ENB
Fault-Tolerant Systems
OUTA0
100Ω
LVCMOS/LVTTL
LOGIC INPUTS
LB_SELA
LB_SELB
BSEL
GND
GND
GND
GND
Pin Configurations and Functional Diagram appear at end
of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9394/MAX9395
General Description
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V
IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, _SEL, LB_SEL_
to GND........................................................-0.3V to (VCC + 0.3V)
IN_ _ to IN_ _..........................................................................±3V
Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFP (derate 13.1mW/°C above +70°C)........1047mW
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin TQFP............................................................+76.4°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection (Human Body Model)
(IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, SEL_, LB_SEL_) ..±2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, EN_ _ = VCC, VCM = +0.05V to (VCC - 0.6V) (MAX9394), VCM = +0.06V to (VCC - 0.05V)
(MAX9395), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C.)
(Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.0
VCC
V
LVCMOS/LVTTL INPUTS (EN_ _, BSEL, LB_SEL_)
Input High Voltage
VIH
Input Low Voltage
VIL
0
0.8
V
Input High Current
IIH
VIN = 2.0V to VCC
0
20
µA
Input Low Current
IIL
VIN = 0V to 0.8V
0
10
µA
VID
VILD > 0V and VIHD < VCC, Figure 1
3.0
V
DIFFERENTIAL INPUTS (IN_ _, IN_ _)
Differential Input Voltage
Input Common-Mode Range
Input Current
0.1
IIN_ _,
IIN_ _
MAX9394
|VID| < 3.0V
-75
VCC 0.6
VCC 0.05
10
MAX9395
|VID| < 3.0V
-10
100
VOD
RL = 100Ω, Figure 2
MAX9394
0.05
MAX9395
0.6
VCM
V
µA
LVDS OUTPUTS (OUT_ _, OUT_ _)
Differential Output Voltage
Change in Magnitude of VOD
Between Complementary Output
States
Offset Common-Mode Voltage
Change in Magnitude of VOS
Between Complementary Output
States
2
ΔVOD
Figure 2
VOS
Figure 2
ΔVOS
Figure 2
250
1.125
350
450
mV
1.0
50
mV
1.25
1.375
V
1.0
50
mV
_______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, EN_ _ = VCC, VCM = 0.05V to (VCC - 0.6V) (MAX9394), VCM = 0.06V to (VCC - 0.05V)
(MAX9395), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25°C.)
(Notes 1, 2, and 3)
PARAMETER
SYMBOL
Output Short-Circuit Current
(Output(s) Shorted to GND)
|IOS|
Output Short-Circuit Current
(Outputs Shorted Together)
|IOSB|
CONDITIONS
TYP
MAX
VOUT_ _ or V OUT_ _ = 0V
30
40
VOUT_ _ =
V OUT_ _ = 0V
17
24
VID = ±100mV, VOUT_ _ = V OUT_ _ (Note 4)
5
12
RL = 100Ω, EN_ _ = VCC
53
65
RL = 100Ω, EN_ _ = VCC, switching at
670MHz (1.34Gbps)
53
65
VID = ±100mV
(Note 4)
MIN
UNITS
mA
mA
SUPPLY CURRENT
Supply Current
ICC
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, fIN < 1.34GHz, tR_IN = tF_IN = 125ps, RL = 100Ω ±1%, |VID| ≥ 150mV, VCM = 0.075V to (VCC - 0.6V) (MAX9394
only), VCM = 0.6V to (VCC - 0.075V) (MAX9395 only), EN_ _ = VCC, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, fIN = 1.34GHz, TA = +25°C.) (Note 5)
PARAMETER
SYMBOL
MAX
UNITS
SEL to Switched Output
tSWITCH
Figure 3
1.1
ns
Disable Time to Differential
Output Low
tPHD
Figure 4
1.7
ns
Enable Time to Differential Output
High
tPDH
Figure 4
1.7
ns
Switching Frequency
fMAX
VOD > 250mV
1.5
2.2
Low-to-High Propagation Delay
tPLH
Figures 1, 5
340
567
720
ps
tPHL
Figures 1, 5
340
High-to-Low Propagation Delay
Pulse Skew |tPLH – tPHL|
Output Channel-to-Channel Skew
tSKEW
tCCS
CONDITIONS
MIN
Figures 1, 5 (Note 6)
Figure 6 (Note 7)
TYP
GHz
562
720
ps
12.4
86
ps
16
87
ps
Output Low-to-High Transition
Time (20% to 80%)
tR
fIN_ _ = 100MHz, Figures 1, 5
112
154
187
ps
Output High-to-Low Transition
Time (80% to 20%)
tF
fIN_ _ = 100MHz, Figures 1, 5
112
152
187
ps
Added Random Jitter
tRJ
fIN_ _ = 1.34GHz, clock pattern (Note 8)
2
ps(RMS)
Added Deterministic Jitter
tDJ
1.34Gbps, 223 - 1 PRBS (Note 8)
60
91
psP-P
Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except VID, VOD, and ΔVOD.
Current into the device defined as positive. Current out of the device defined as negative.
DC parameters production tested at TA = +25°C and guaranteed by design and characterization for TA = -40°C to +85°C.
Current through either output.
Guaranteed by design and characterization. Limits set at ±6 sigma.
tSKEW is the magnitude difference of differential propagation delays for the same output over the same condtions. tSKEW =
|tPHL - tPLH|.
Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition under the same conditions. Does not apply to loopback mode.
Note 8: Device jitter added to the differential input signal.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
_______________________________________________________________________________________
3
MAX9394/MAX9395
DC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VCC = 3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25°C, fIN = 1.34GHz, Figure 5.)
55
50
VCC = 3.3V
VCC = 3.0V
40
35
250
200
150
-15
10
35
60
tR
150
tF
140
130
120
85
0
0.4
0.8
1.2
1.6
-40
2.4
2.0
-15
10
35
60
85
TEMPERATURE (°C)
FREQUENCY (GHz)
TEMPERATURE (°C)
PROPAGATION DELAY
vs. TEMPERATURE
MAX9394 DIFFERENTIAL INPUT CURRENT
vs. TEMPERATURE
MAX9395 DIFFERENTIAL INPUT CURRENT
vs. TEMPERATURE
INPUT CURRENT (μA)
570
560
550
540
530
VIN_ _ = 0V
80
VIN_ _ = 3.0V
VIN_ _ = VCC
70
-10
-15
-20
VIN_ _ = 0.1V
-25
-30
-35
-40
520
510
-15
10
35
60
85
30
VIN_ _ = (VCC - 3.0V)
-15
10
35
85
60
-40
-15
TEMPERATURE (°C)
IN_ _ OR
IN_ _ = GND
VCC = 3V
-15
-20
VCC = 3.6V
-25
-30
35
MAX9395
DIFFERENTIAL INPUT CURRENT vs. VILD
80
IN_ _ OR
IN_ _ = VCC
70
60
INPUT CURRENT (μA)
-5
10
TEMPERATURE (°C)
MAX9394/95 toc07
5
INPUT CURRENT (μA)
40
0
-40
MAX9394
DIFFERENTIAL INPUT CURRENT vs. VIHD
-10
50
10
TEMPERATURE (°C)
0
VIN_ _ = (VCC - 0.1V)
60
20
-45
-50
500
MAX9394/95 toc06
580
5
0
-5
INPUT CURRENT (μA)
590
MAX9394/95 toc05
10
MAX9394/95 toc04
600
-40
160
100
0
-40
50
VCC = 3.6V
40
30
VCC = 3V
20
10
-35
0
-40
-10
0
0.6
1.2
1.8
VIHD (V)
4
170
50
30
fIN = 100MHz
MAX9394/95 toc08
45
300
RISE/FALL TIME (ps)
VCC = 3.6V
180
MAX9394/95 toc02
60
350
OUTPUT AMPLITUDE (mV)
65
SUPPLY CURRENT (mA)
400
MAX9394/95 toc01
70
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
OUTPUT AMPLITUDE vs. FREQUENCY
MAX9394/95 toc03
SUPPLY CURRENT vs. TEMPERATURE
PROPAGATION DELAY (ps)
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
2.4
3.0
3.6
0
0.6
1.2
1.8
2.4
3.0
VILD (V)
_______________________________________________________________________________________
3.6
60
85
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
PIN
NAME
FUNCTION
1, 2, 3, 30,
31, 32
N.C.
No Connection. Not internally connected.
4, 9, 20, 25
GND
Ground
5
ENB
Channel B Output Enable. Drive ENB high to enable the LVDS outputs for channel B. An internal 435kΩ
resistor to GND pulls ENB low when unconnected.
6
OUTB
Channel B LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTB and OUTB at
the receiver inputs to ensure proper operation.
7
OUTB
Channel B LVDS Inverting Output. Connect a 100Ω termination resistor between OUTB and OUTB at the
receiver inputs to ensure proper operation.
8, 13, 24,
29
VCC
Power-Supply Input. Bypass each VCC to GND with a 0.1µF and 0.01µF ceramic capacitor. Install both
bypass capacitors as close to the device as possible, with the 0.01µF capacitor closest to the device.
10
INB0
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal 128kΩ pullup resistor to
VCC pulls the input high when unconnected (MAX9394). An internal 68kΩ resistor to GND pulls the input
low when unconnected (MAX9395).
11
INB0
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal 128kΩ pullup
resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68kΩ resistor to GND
pulls the input low when unconnected (MAX9395).
12
LB_SELB
Loopback Select for Channel B Output. Connect LB_SELB to GND or leave unconnected to reproduce
the INB_ (INB_) differential inputs at OUTB (OUTB). Connect LB_SELB to VCC to loop back the INA (INA)
differential inputs to OUTB (OUTB). An internal 435kΩ resistor to GND pulls LB_SELB low when
unconnected.
14
INB1
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal 128kΩ pullup resistor to
VCC pulls the input high when unconnected (MAX9394). An internal 68kΩ resistor to GND pulls the input
low when unconnected (MAX9395).
15
INB1
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal 128kΩ pullup
resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68kΩ resistor to GND
pulls the input low when unconnected (MAX9395).
16
BSEL
Channel B Multiplexer Control Input. Selects the differential input to reproduce at the B channel
differential output. Connect BSEL to GND or leave unconnected to select the INB0 (INB0) set of inputs.
Connect BSEL to VCC to select the INB1 (INB1) set of inputs. An internal 435kΩ resistor to GND pulls
BSEL low when unconnected.
17
ENA1
Channel A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435kΩ resistor
to GND pulls the ENA1 low when unconnected.
18
OUTA1
Channel A1 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTA1 and OUTA1 at
the receiver inputs to ensure proper operation.
19
OUTA1
Channel A1 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTA1 and
OUTA1 at the receiver inputs to ensure proper operation.
_______________________________________________________________________________________
5
MAX9394/MAX9395
Pin Description
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
MAX9394/MAX9395
Pin Description (continued)
PIN
FUNCTION
21
ENA0
Channel A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An internal 435kΩ resistor
to GND pulls ENA0 low when unconnected.
22
OUTA0
Channel A0 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTA0 and OUTA0 at
the receiver inputs to ensure proper operation.
23
OUTA0
Channel A0 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTA0 and
OUTA0 at the receiver inputs to ensure proper operation.
26
INA
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal 128kΩ pullup
resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68kΩ resistor to GND
pulls the input low when unconnected (MAX9395).
27
INA
LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal 128kΩ pullup resistor to
VCC pulls the input high when unconnected (MAX9394). An internal 68kΩ resistor to GND pulls the input
low when unconnected (MAX9395).
28
6
NAME
Loopback Select for Channel A Output. Connect LB_SELA to GND or leave unconnected to reproduce
the INA (INA) differential inputs at OUTA_ (OUTA_). Connect LB_SELA to VCC to loop back the INB_
LB_SELA
(INB_) differential inputs to OUTA_ (OUTA_). An internal 435kΩ resistor to GND pulls LB_SELA low when
unconnected.
_______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
MAX9394/MAX9395
VIN_ _
VIHD
VID = 0V
VID = 0V
OUT_ _
VIN_ _
VILD
MAX9394/MAX9395
VOD
tPHL
tPLH
RL/2
VOUT_ _
VOD = 0V
IN_ _
VOD = 0V
VOS
IN_ _
VOUT_ _
RL/2
80%
VOD = 0V
50%
EN_ _ = HIGH
VID = VIN_ _ - VIN_ _
80%
ΔVOD = ⎪VOD - VOD*⎪
RL = 100Ω ±1%
ΔVOS = ⎪VOS - VOS*⎪
VOD AND VOS ARE MEASURED WITH VID = +100mV.
VOD* AND VOS* ARE MEASURED WITH VID = -100mV.
20%
20%
tR
OUT_ _
VOD = 0V
50%
tF
VID = VIN_ _ - VIN_ _
VOD = VOUT_ _ - VOUT_ _
Figure 1. Output Transition Time and Propagation Delay Timing
Diagram
Figure 2. Test Circuit for VOD and VOS
VIHD
INB0
VID = 0V
VILD
INB0
VIHD
INB1
VID = 0V
VILD
INB1
VIH
1.5V
1.5V
VIL
BSEL
OUT_ _
INB0
VOD = 0V
INB1
VOD = 0V
INB0
OUT_ _
tSWITCH
tSWITCH
EN_0 = EN_1 = HIGH
VID = VIN_ _ - VIN_ _
Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram
_______________________________________________________________________________________
7
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
OUT_ _
MAX9394/MAX9395
CL
RL/2
IN_ _
IN_ _
1.25V
RL/2
RL = 100Ω ±1%
OUT_ _ CL = 1.0pF
EN_ _
PULSE
GENERATOR
CL
50Ω
1.5V
VEN_ _
3V
1.5V
0V
tPHD
VOUT_ _ WHEN VID = +100mV
VOUT_ _ WHEN VID = -100mV
tPDH
50%
VOUT_ _ WHEN VID = -100mV
VOUT_ _ WHEN VID = +100mV
50%
50%
50%
tPHD
tPDH
VID = VIN_ _ - VIN_ _
Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram
LB_SELA
MAX9394
MAX9395
INA
PULSE
GENERATOR
CL
OUTA0
0
INA
RL
50Ω
50Ω
LB
OUTA0
CL
FROM
CHANNEL B
CL
OUTA1
RL
OUTA1
CL
RL = 100Ω ±1%
CL = 1.0pF
ENA0 = ENA1 = HIGH
1 CHANNEL SHOWN.
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
8
_______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
VOD = 0V
VOD = 0V
tCCS
tCCS
VOUTA0
VOUTA1
VOD = 0V
VOD = 0V
VOUTA1
VOD = VOUT_ _ - VOUT_ _
Figure 6. Output Channel-to-Channel Skew
Detailed Description
The LVDS interface standard provides a signaling
method for point-to-point communication over a controlled-impedance medium as defined by the ANSI
TIA/EIA-644 standard. LVDS utilizes a lower voltage
swing than other communication standards, achieving
higher data rates with reduced power consumption,
while reducing EMI emissions and system susceptibility
to noise.
The MAX9394/MAX9395 high-speed, low-power 2:1
multiplexers and 1:2 demultiplexers with loopback provide signal redundancy switching in telecom and storage applications. These devices select one of two
remote signal sources for local input and buffer a single
local output signal to two remote receivers.
The multiplexer section (channel B) accepts two differential inputs and generates a single LVDS output. The
demultiplexer section (channel A) accepts a single differential input and generates two parallel LVDS outputs. The
MAX9394/MAX9395 feature a loopback mode that connects the input of channel A to the output of channel B
and connects the selected input of channel B to the outputs of channel A. LB_SELA and LB_SELB provide independent loopback control for each channel.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.
Input Fail-Safe
The differential inputs of the MAX9394/MAX9395 possess internal fail-safe protection. Fail-safe circuitry
forces the outputs to a differential-low condition for
undriven inputs or when the common-mode voltage
exceeds the specified range. The MAX9394 provides
high-level input fail-safe detection for LVDS, HSTL, and
other GND-referenced differential inputs. The MAX9395
provides low-level input fail-safe detection for LVPECL,
CML, and other VCC-referenced differential inputs.
Select Function
BSEL selects the differential input pair to transmit
through OUTB (OUTB) for LB_SELB = GND or through
OUTA_ (OUTA_) for LB_SELA = VCC. LB_SEL_ controls
the loopback function for each channel. Connect
LB_SEL_ to GND to select the normal inputs for each
channel. Connect LB_SEL_ to VCC to enable the loopback function. The loopback function routes the input of
channel A to the output of channel B, and the inputs of
channel B to the outputs of channel A. See Tables 1
and 2 for a summary of the input/output routing
between channels.
Enable Function
The EN_ _ logic inputs enable and disable each set of
differential outputs. Connect EN_ 0 to VCC to enable the
OUT_0/OUT_0 differential output pair. Connect EN_0 to
GND to disable the OUT_0/OUT_0 differential output
pair. The differential output pairs assert to a differential
low condition when disabled.
Applications Information
Differential Inputs
The MAX9394/MAX9395 inputs accept any differential
signaling standard within the specified common-mode
voltage range. The fail-safe feature detects commonmode input signal levels and generates a differential
output low condition for undriven inputs or when the
common-mode voltage exceeds the specified range
(VCM ≥ VCC - 0.6V, MAX9394; VCM ≤ 0.6V, MAX9395).
Leave unused inputs unconnected or connect to VCC
for the MAX9394 or to GND for the MAX9395.
_______________________________________________________________________________________
9
MAX9394/MAX9395
VOUTA0
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
Table 1. Input Select Truth Table
LOGIC INPUTS
DIFFERENTIAL OUTPUTS
LB_SELA
LB_SELB
BSEL
OUTA_ / OUTA_
OUTB / OUTB
0
0
0
INA selected
INB0 selected
0
0
1
INA selected
INB1 selected
0
1
X
INA selected
INA selected
1
0
0
INB0 selected
INB0 selected
1
0
1
INB1 selected
INB1 selected
1
1
0
INB0 selected
INA selected
1
1
INB1 selected
INA selected
1
X = Don’t care.
Differential Outputs
The output common-mode voltage is not properly
established if the LVDS output is higher than 0.6V when
the supply voltage is ramping up at power-on. This
condition can occur when an LVDS output drives an
LVDS input on the same chip. To avoid this situation for
the MAX9394/MAX9395, connect a 10kΩ resistor from
the noninverting output (OUT_) to ground, and connect
a 10kΩ resistor from the inverting output (OUT_) to
ground. These pulldown resistors keep the output
below 0.6V when the supply is ramping up (Figure 7).
Power-Supply Bypassing
Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1µF and 0.01µF capacitors in parallel
as close to the device as possible. Install the 0.01µF
capacitor closest to the device.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9394/MAX9395. Connect each input
and output to a 50Ω characteristic impedance trace.
Maintain the distance between differential traces and
eliminate sharp corners to avoid discontinuities in differential impedance and maximize common-mode
noise immunity. Minimize the number of vias on the differential input and output traces to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ω characteristic impedance through connectors and
across cables. Minimize skew by matching the electrical length of the traces.
Table 2. Loopback Select Truth Table
LB_SEL_
OUT_ _
GND or open
Normal inputs selected.
VCC
Loopback inputs selected.
100Ω DIFFERENTIAL
TRANSMISSION LINE
MAX9394
MAX9395
OUT_
100Ω
OUT_
10kΩ
10kΩ
TERMINATION
RESISTOR
GND
Figure 7. Pulldown Resistor Configuration for LVDS Outputs
Observe the total thermal limits of the MAX9394/
MAX9395 under all operating conditions.
Cables and Connectors
Use matched differential impedance for transmission
media. Use cables and connectors with matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables.
Balanced cables such as twisted pair offer superior
signal quality and tend to generate less EMI due to
canceling effects.
Output Termination
Board Layout
Terminate LVDS outputs with a 100Ω resistor between
the differential outputs at the receiver inputs. LVDS outputs require 100Ω termination for proper operation.
Ensure that the output currents do not exceed the current limits specified in the Absolute Maximum Ratings.
Use a four-layer printed circuit (PC) board providing
separate signal, power, and ground planes for highspeed signaling applications. Bypass VCC to GND as
close to the device as possible. Install termination
resistors as close to receiver inputs as possible. Match
the electrical length of the differential traces to minimize
signal skew.
10
______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
LB_SELA
ENA0
MAX9394
MAX9395
OUTA0
INA
OUTA0
0
INA
LB
OUTA1
OUTA1
ENA1
LB_SELB
INB0
OUTB
LB
0
INB0
OUTB
ENB
0
INB1
1
INB1
BSEL
______________________________________________________________________________________
11
MAX9394/MAX9395
Functional Diagram
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
MAX9394/MAX9395
Pin Configurations
N.C.
N.C.
VCC
LB_SELA
INA
INA
GND
TRANSISTOR COUNT: 1565
PROCESS: BIPOLAR
N.C.
TOP VIEW
Chip Information
32
31
30
29
28
27
26
25
+
N.C. 1
24 VCC
N.C. 2
23 OUTA0
N.C. 3
22 OUTA0
21 ENA0
GND 4
MAX9394
MAX9395
ENB 5
20 GND
OUTB 6
19 OUTA1
OUTB 7
18 OUTA1
VCC 8
14
15
16
BSEL
INB0
13
INB1
INB0
12
INB1
11
VCC
10
LB_SELB
9
GND
17 ENA1
TQFP
12
______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
32L TQFP, 5x5x01.0.EPS
PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm
21-0110
B
1
2
______________________________________________________________________________________
13
MAX9394/MAX9395
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9394/MAX9395
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm
21-0110
B
2
2
Revision History
All pages changed at Rev 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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is a registered trademark of Maxim Integrated Products, Inc.
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