MAX9660ETA+

19-4564; Rev 0; 4/09 KIT ATION EVALU E L B AVAILA 7-Bit, Programmable VCOM Reference with 30x MOTP Memory o Integrated Nonvolatile Memory to Store VCOM Setting o 7-Bit, Adjustable Sink-Current Device o Resistor-Adjustable, Full-Scale Range o 2.5V to 3.6V Logic Supply Range o 8V to 20V Analog Supply Range TFT-LCD Panels 8 DVDD TOP VIEW SCL Pin Configuration SDA Applications o VCOM Amplifier with 900mA Peak Output Current SET The MAX9660 provides a programmable reference voltage for VCOM adjustment in TFT-LCD panels. A 7-bit, current digital-to-analog converter (DAC) sinks current from an external resistor-divider string to create the VCOM reference voltage, which then serves as the input to a voltage buffer capable of driving out high current. The MAX9660 includes multiple one-time programmable (MOTP) memory to store the DAC code on the chip, eliminating the need for external EEPROM. The chip supports up to 30 write operations to MOTP memory. The MAX9660 has an I2C interface to set the VCOM reference voltage and write into MOTP memory. Features 7 6 5 Instrumental Control Voltage Source MAX9660 8 TDFN-EP* 3 4 GND PIN-PACKAGE 2 AVDD TEMP RANGE -40°C to +125°C OUT PART MAX9660ATA+ 1 VCOM + Ordering Information TDFN +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Functional Diagram AVDD R1 DVDD AVDD OUT R2 19R MAX9660 SDA SCL I2C AND MOTP CONTROLLER 7 R VCOM 7 MOTP MEMORY GND SET RSET ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9660 General Description MAX9660 7-Bit, Programmable VCOM Reference with 30x MOTP Memory ABSOLUTE MAXIMUM RATINGS Supply Voltage DVDD, SET, SCL, and SDA to GND .....................-0.3V to +4V AVDD to GND.....................................................-0.3V to +22V OUT to GND .......................................................-0.3V to +22V VCOM to GND .......................................-0.3V to AVDD + 0.3V Continuous Current SDA .................................................................................10mA VCOM .........................................................................±100mA Continuous Power Dissipation (TA = +70°C) 8-Pin TDFN-EP (derate 18.5mW/°C above +70°C) Single-Layer Board ..................................................1481mW 8-Pin TDFN-EP (derate 24.4mW/°C above +70°C) Multilayer Board .......................................................1951mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDVDD = 3.3V, VAVDD = 16V, VGND = 0, RSET = 6.8kΩ, no load, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.3 3.6 V 20 V 4.5 10 mA 15 20 SUPPLIES Digital Supply Voltage Range VDVDD 2.5 Analog Supply Voltage Range VAVDD 8 Analog Quiescent Current IAVDD Analog Supply Current Range for Programming MOTP Digital Quiescent Current MOTP Programming Times IAVDD TA = +25°C TA = +85°C 45 IDVDD 200 MOTPSET 500 30 mA µA Times VCOM OUTPUT (VCOM) Common-Mode Range Total Output Error VERR TA = +25°C, VVCOM from 2V to VAVDD - 2V Output Voltage Swing Low VOL IL = -5mA, VOUT = 0 Output Voltage Swing High VOH IL = +5mA, VOUT = VAVDD 0.2 VAVDD - 0.2 V -22 +22 mV 150 mV VAVDD - 150 Output Load Regulation LR Short-Circuit Current (Note 2) ISC Power-Supply Rejection Ratio PSRR 8V ≤ VAVDD ≤ 20V, VOUT = 5V Slew Rate SR 4VP-P at VCOM, 10% to 90%, RL = 10kΩ, CL = 20pF 45 V/µs Bandwidth dB RL = 10kΩ, CL = 20pF, VVCOM = 100mVP-P 20 MHz 2 IL = -80mA to +80mA mV ±0.2 VCOM = AVDD -900 VCOM = GND +900 70 mV/mA mA dB _______________________________________________________________________________________ 7-Bit, Programmable VCOM Reference with 30x MOTP Memory (VDVDD = 3.3V, VAVDD = 16V, VGND = 0, RSET = 6.8kΩ, no load, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 20 V DVR OUT Voltage Range VOUT VSET + 0.5V Resolution RES 7 Integral Nonlinearity Error INL 0.125 LSB Differential Nonlinearity Error DNL 0.125 LSB AVDD to VSET Ratio AVDD/VSET Set External Resistance Set Current RSET ISET Bits 20:1 V/V VAVDD = 8V 3.35 67 VAVDD = 18V 6.75 135 Through RSET kΩ 134 µA Set Zero-Scale Error SETZSE ±2 LSB Set Full-Scale Error SETFSE ±4 LSB LOGIC INPUTS (SDA, SCL) 0.7 x VDVDD Input High Voltage VIH Input Low Voltage VIL SDA Output Low Voltage VOL ISINK = 6mA IIH, IIL 0V or VDVDD Input Leakage Current -3 Input Capacitance V 0.01 0.3 x VDVDD V 0.4 V +3 5 µA pF I2C TIMING CHARCTERISTICS Serial-Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Hold Time START Condition 400 kHz tHD, STA 0.6 µs SCL Pulse-Width Low tLOW 1.3 µs SCL Pulse-Width High tHIGH 0.6 µs Setup Time for a START Condition tSU, STA 0.6 µs Data Hold Time tHD, DAT 0 Data Setup Time tSU, DAT (Note 3) 100 SDA and SCL Receiving Rise Time tR (Note 4) 20 + 0.1CB 300 ns SDA and SCL Receiving Fall Time tF (Note 4) 20 + 0.1CB 300 ns SDA Transmitting Fall Time tF (Note 4) 20 + 0.1CB 250 ns 900 ns ns _______________________________________________________________________________________ 3 MAX9660 ELECTRICAL CHARACTERISTICS (continued) MAX9660 7-Bit, Programmable VCOM Reference with 30x MOTP Memory ELECTRICAL CHARACTERISTICS (continued) (VDVDD = 3.3V, VAVDD = 16V, VGND = 0, RSET = 6.8kΩ, no load, TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Bus Capacitance CB Pulse Width of Suppressed Spike tSP Note 1: Note 2: Note 3: Note 4: 4 CONDITIONS MIN TYP 0 MAX UNITS 400 pF 50 ns All devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design. Short-circuit current is for a 1µs pulsed current only, not to exceed thermal characteristics of package. Data hold time is tested in receive mode only. CB is in pF. _______________________________________________________________________________________ 7-Bit, Programmable VCOM Reference with 30x MOTP Memory INL vs. CODE 0.05 0.05 0 -0.05 -0.10 -0.10 -0.15 -0.15 -0.20 -20 -30 0 -0.05 -10 PSRR (dB) 0.10 64 96 -60 -80 -90 -100 0 128 -50 32 CODE (NUMERIC) 64 96 128 100 10 CODE (NUMERIC) OUTPUT OFFSET VOLTAGE DISTRIBUTION 8 6 0.10 16.0 4 2 VVCOM (V) LOAD VOLTAGE (mV) 0.15 0 -2 15.9 -4 15.8 -6 0.05 16.1 MAX9660 toc05 10 MAX9660 toc04 0.20 10,000 VVCOM vs. ISOURCE VCOM LOAD REGULATION 0.25 1000 FREQUENCY (kHz) MAX9660 toc06 32 -40 -70 -0.20 0 MAX9660 toc03 0.15 0.10 0 MAX9660 toc02 MAX9660 toc01 0.20 DNL (LSB) INL (LSB) 0.15 N (%) DAC PSRR vs. FREQUENCY DNL vs. CODE 0.20 -8 -10 0 BELOW 0.65 2.41 4.17 5.93 7.69 ABOVE -0.23 1.53 3.29 5.05 6.81 8.57 OUTPUT OFFSET (mV) 15.7 -80 VVCOM vs. ISINK -20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 45 50 LOAD CURRENT (mA) ISOURCE (mA) VCOM PSRR vs. FREQUENCY VCOM BUFFER PULSE LOAD TRANSIENT MAX9660 toc09 MAX9660 toc08 0.12 -40 0 MAX9660 toc07 0.15 -60 -10 -20 VVCOMOUT 200mV/div 0.09 PSRR (dB) VVCOM (V) -30 0.06 -40 -50 -60 -70 0.03 -80 0 -100 IVCOMOUT 500mA/div -90 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 ISINK (mA) 0 10 100 1000 10,000 2μs/div FREQUENCY (kHz) _______________________________________________________________________________________ 5 MAX9660 Typical Operating Characteristics (Typical Application Circuit, VDVDD = 3.3V, VAVDD = 16V, RSET = 7kΩ, R1 = R2 = 35kΩ, TA = +25°C, unless otherwise noted.) 7-Bit, Programmable VCOM Reference with 30x MOTP Memory MAX9660 Pin Description PIN 1 NAME OUT FUNCTION Adjustable Sink Current for Integrated VCOM Voltage Buffer. OUT connects to the resistive voltagedivider between AVDD and GND. 2 AVDD Analog Power Supply. Bypass AVDD with 0.1µF and 10µF capacitors in parallel to GND. 3 VCOM VCOM Output 4 GND 5 DVDD 6 SDA I2C-Compatible Serial-Data Input/Output 7 SCL I2C-Compatible Serial-Clock Input Full-Scale Sink-Current Adjustment Input. Connect a resistor, RSET, from SET to GND to set the fullscale adjustable sink current. The full-scale adjustable sink current is equal to: 8 SET — EP Ground Digital Power Supply. Bypass DVDD with 0.1µF capacitor to GND. ⎛ VAVDD ⎞ ⎜ 20 × R ⎟ ⎝ SET ⎠ Exposed Pad. Connect EP to GND. Detailed Description The MAX9660, a programmable VCOM buffer, replaces the mechanical potentiometer that is used for adjusting the VCOM voltage with an electrical solution (see the Typical Application Circuit ). The MAX9660 attaches to an external resistor-divider (resistors R1 and R2) and sinks a programmable current IOUT to create the VCOM reference voltage. The resolution of the current DAC that generates IOUT is 7 bits. The DAC is ratiometric relative to VAVDD and is monotonic over all operating conditions. The external resistor RSET sets the full-scale sink current and the minimum value of the VCOM reference voltage. The external resistor-divider and the AVDD supply set the maximum value of the VCOM reference voltage. The VCOM reference voltage is the input to the integrated voltage buffer, which can source and sink 900mA so that VCOM can quickly recover after a polarity inversion or a horizontal line change. The MAX9660 features output short-circuit protection and soft-start to reduce inrush current. The user can store the DAC setting in a type of nonvolatile memory known as MOTP. On power-up, MOTP sets the DAC register to the last stored setting. The DAC register and the MOTP can be programmed through the I2C interface. 6 7-Bit DAC An internal 7-bit DAC sinks current IOUT. The following equations determine the value of IOUT: ⎛ CODE + 1⎞ ⎛ VAVDD ⎞ IOUT = ⎜ ⎟ ×⎜ ⎟ ⎝ ⎠ ⎝ 20 × RSET ⎠ 2N where CODE is the numeric value of the DAC’s binary input code and N is the bits of resolution. For the MAX9660, N = 7 and CODE ranges from 0 to 127. The MAX9660 pulls IOUT through the external resistordivider comprised of R1 and R2. The resulting voltage VOUT is given by the following formula: ⎛ ⎛ CODE + 1⎞ ⎛ ⎛ R2 ⎞ ⎞⎞ R1 VVCOM = ⎜ × VAVDD × ⎜1 − ⎜ ⎟⎜ ⎟ ⎟⎟ ⎝ R1 + R2 ⎠ ⎝ ⎝ 128 ⎠ ⎝ 20 × RSET ⎠ ⎠ VCOM Amplifier The buffer attached to VOUT holds the VCOM voltage stable while providing the ability to source and sink 900mA into the backplane of a TFT-LCD panel. The buffer can directly drive the capacitive load of the TFTLCD backplane without the need for a series resistor in most cases. The VCOM amplifier has current limiting on its output to protect its bond wires. _______________________________________________________________________________________ 7-Bit, Programmable VCOM Reference with 30x MOTP Memory SCL SDA ACK ACK DEVICE ID ACK VALUE SETTING DEVICE ID MOTP PROGRAMMING SCL = 400kHz ACK VALUE SETTING MOTP PROGRAMMING Figure 1. MOTP programming interval. Wait 500ms after issuing a write command to MOTP memory before starting another write command to MOTP memory. SCL SDA ACK DEVICE ID NACK VALUE SETTING ALWAYS RETURN A 1 WHEN THE MOTP IS FULL. Figure 2. Example of a write command to MOTP memory after MOTP memory is full. The MAX9660 responds with a NACK. Multiple One-Time Programmable Memory (MOTP) Programming DAC codes can be written into MOTP memory up to 30 times because the MOTP memory is a bank of 30 onetime programmable registers. See the Write Data Format section for a description of how to use the I2C interface to write data into MOTP. After an I 2 C write operation to MOTP memory, the MAX9660 requires a maximum of 500ms to burn the data into the MOTP register (see Figure 1). During this time, do not perform another write operation to MOTP memory. If a write operation to MOTP memory is attempted during this time, the MAX9660 responds with a not acknowledge (NACK). The MAX9660 integrates MOTP memory that can be programmed 30 times. After 30 writes to MOTP memory, the MAX9660 responds with a not acknowledge (NACK) to all future write attempts (see Figure 2). I2C Serial Interface I2C/SMBus™-compatible, The MAX9660 features an 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9660 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9660 by transmitting the proper slave address followed by the data word. Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each word transmitted to the MAX9660 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9660 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9660 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500Ω, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9660 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. SMBus is a trademark of Intel Corp. _______________________________________________________________________________________ 7 MAX9660 500ms MAX9660 7-Bit, Programmable VCOM Reference with 30x MOTP Memory SDA tBUF tSU, DAT tSP tHD, DAT tLOW tSU, STO SCL tHIGH tHD, STA tR tF STOP CONDITION START CONDITION START CONDITION Figure 3. I2C Serial-Interface Timing Diagram Table 1. Slave Address B7 B6 B5 B4 B3 B2 B1 B0 WRITE ADDRESS READ ADDRESS 1 0 0 1 1 1 1 R/W 0x9E 0x9F Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the MAX9660. The master terminates transmission, and frees the bus, by issuing a STOP condition. Early STOP Conditions The MAX9660 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the MAX9660 to read mode. 8 Set the R/W bit to 0 to configure the MAX9660 to write mode. The address is the first byte of information sent to the MAX9660 after the START condition. Table 1 shows the possible addresses for the MAX9660. Acknowledge The acknowledge bit (ACK) is a clocked ninth bit that the MAX9660 uses to handshake receipt of each byte of data when in write mode (see Figure 5). The MAX9660 pulls down SDA during the entire mastergenerated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9660 is in read mode. An acknowledge bit is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge bit is sent when the master reads the final byte of data from the MAX9660, followed by a STOP condition. Write Data Format A write to the MAX9660 consists of transmitting a START condition, the slave address with the R/W bit set to 0, 7-bit data, M bit, and a STOP condition. Figure 6 illustrates the proper frame format for writing 7 bits of data to the MAX9660. The slave address with the R/W bit set to 0 indicates that the master intends to write _______________________________________________________________________________________ 7-Bit, Programmable VCOM Reference with 30x MOTP Memory P CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL SCL MAX9660 S 1 2 8 9 NOT ACKNOWLEDGE SDA SDA ACKNOWLEDGE Figure 4. START and STOP Conditions Figure 5. Acknowledge Register Map REG B7 B6 B5 B4 B3 B3 B1 B0 FACTORY INITIALIZATION R/W VCOM d6 d5 d4 d3 d2 d1 d0 M 64 R/W Table 2. I2C Register BITS DESCRIPTION B7:B1 7-bit DAC data B0 Data location indicator (M bit). The M bit identifies the register for the data to be written to. M = 0, the data is written to the MOTP register. M = 1, the data is written to the DAC register. data to the MAX9660. The MAX9660 acknowledges receipt of the address byte during the master-generated ninth SCL pulse. The second byte sent to the MAX9660 contains the 7-bit data that is written to the DAC latch or MOTP. The M bit after bit B1 identifies the register to be written to, as shown in Table 2. When M = 0, the MOTP is written to, and when M = 1, the DAC register is written to. An acknowledge pulse from the MAX9660 signals receipt of the VCOM data byte. The master signals the end of transmission by issuing a STOP condition. Read Data Format The master presets the address pointer by first sending the MAX9660’s slave address with the R/W bit set to 1 after a START condition. The MAX9660 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. The MAX9660 transmits the contents of the DAC register as 7-bit data and the eighth bit, M, is don’t care. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). A STOP condition is issued after reading the data byte. The master acknowledges receipt of the read byte during the acknowledge clock pulse. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 7 illustrates the frame format for reading data from the MAX9660. Applications Information Power-Up and Power-Down Operation During power-up, the digital supply must be powered up first. The analog supply should not be powered up until the digital supply has stabilized. During this time, the MOTP register value is loaded into the DAC register (0x40 is the factory-programmed default). Once AVDD is above approximately 7V, the VCOM amplifier has enough headroom and powers up proportionally with AVDD. For power-down, AVDD must be powered down first to 0V, and then DVDD can safely be powered down. _______________________________________________________________________________________ 9 MAX9660 7-Bit, Programmable VCOM Reference with 30x MOTP Memory S 1 0 0 1 1 1 1 R/W =0 ACK B7 B6 B5 SLAVE ADDRESS B4 B3 B2 B1 M ACK P 7-BIT VCOM DATA Figure 6. Write Operation to MOTP or DAC Register DON'T CARE S 1 0 0 1 1 1 1 R/W =1 ACK SLAVE ADDRESS B7 B6 B5 B4 B3 B2 B1 M ACK P 7-BIT VCOM DATA Figure 7. Read Operation to MOTP or DAC Register Power Supplies and Bypass Capacitors The MAX9660 operates from a single 8V to 20V analog supply (AVDD) and a 2.5V to 3.6V digital supply (DVDD). Bypass AVDD to GND with 0.1µF and 10µF capacitors in parallel. Use an extensive ground plane to ensure optimum performance. Bypass DVDD to GND with a 0.1µF capacitor. The 0.1µF bypass capacitors should be placed as close as possible to their respective pins. Refer to the MAX9660 evaluation kit for a proven PCB layout. Layout and Grounding Exposed Pad The exposed pad on the TDFN package is electrically connected to GND. Solder the exposed pad to a ground plane to provide a low thermal resistance to ground for heat dissipation. Do not route traces under these packages. The layout of the exposed pad should have multiple small through-holes over a single large through-hole as shown as Figure 8. Thermal resistance between top and ground layer can be reduced. In addition, the vias should be flooded with solder for best thermal performance. 10 Figure 8. Multiple small through-holes are recommended over a single large through-hole in PCB layout. ______________________________________________________________________________________ 7-Bit, Programmable VCOM Reference with 30x MOTP Memory 16V 3.3V RSET R1 OUT AVDD R2 + 2 0.1μF VCOM TO VCOM GND 8 1 MAX9660 7 3 6 4 5 SET 10kΩ SCL 10kΩ SERIAL CLOCK SDA SERIAL DATA DVDD 0.1μF Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX9660 Typical Application Circuit MAX9660 7-Bit, Programmable VCOM Reference with 30x MOTP Memory Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 12 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 TDFN-EP T833+2 21-0137 ______________________________________________________________________________________ 7-Bit, Programmable VCOM Reference with 30x MOTP Memory COMMON DIMENSIONS PACKAGE VARIATIONS MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b A 0.70 0.80 T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF D 2.90 3.10 T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF E 2.90 3.10 T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF A1 0.00 0.05 T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF L 0.20 0.40 T1033MK-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF SYMBOL [(N/2)-1] x e k 0.25 MIN. T1033-2 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF A2 0.20 REF. T1433-1 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF T1433-2 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF T1433-3F 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX9660 Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.