OP07

Ultralow Offset Voltage Operational Amplifier OP07 FEATURES Low VOS: 75 μV maximum Low VOS drift: 1.3 μV/°C maximum Ultrastable vs. time: 1.5 μV per month maximum Low noise: 0.6 μV p-p maximum Wide input voltage range: ±14 V typical Wide supply voltage range: 3 V to 18 V 125°C temperature-tested dice PIN CONFIGURATION VOS TRIM –IN +IN V– 1 2 3 4 OP07 8 7 6 5 VOS TRIM V+ OUT 00316-001 NC NC = NO CONNECT Figure 1. APPLICATIONS Wireless base station control circuits Optical network control circuits Instrumentation Sensors and controls Thermocouples Resistor thermal detectors (RTDs) Strain bridges Shunt current measurements Precision filters GENERAL DESCRIPTION The OP07 has very low input offset voltage (75 μV maximum for OP07E) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA for the OP07E) and high open-loop gain (200 V/mV for the OP07E). The low offset and high open-loop gain make the OP07 particularly useful for high gain instrumentation applications. The wide input voltage range of ±13 V minimum combined with a high CMRR of 106 dB (OP07E) and high input impedance provide high accuracy in the noninverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variations in temperature is excellent. The accuracy and stability of the OP07, even at high gain, combined with the freedom from external nulling have made the OP07 an industry standard for instrumentation applications. The OP07 is available in two standard performance grades. The OP07E is specified for operation over the 0°C to 70°C range, and the OP07C is specified over the −40°C to +85°C temperature range. The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow SOIC packages. For CERDIP and TO-99 packages and standard microcircuit drawing (SMD) versions, see the OP77. V+ 7 R2A1 R1A 1 R2B1 (OPTIONAL NULL) C1 8 R1B Q19 Q9 Q7 NONINVERTING INPUT 3 INVERTING INPUT R3 Q5 Q3 Q1 Q21 R4 2 4 V– 1 R2A R7 Q10 Q11 Q12 C2 Q17 R9 OUT 6 Q16 Q15 R10 Q20 Q8 Q6 Q4 Q27 C3 R5 Q26 Q2 Q25 Q23 Q24 Q22 Q14 Q13 R6 Q18 R8 00316-002 AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE. Figure 2. Simplified Schematic Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. OP07 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Pin Configuration............................................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 OP07E Electrical Characteristics ............................................... 3 OP07C Electrical Characteristics ............................................... 4 Absolute Maximum Ratings ............................................................6 Thermal Resistance .......................................................................6 ESD Caution...................................................................................6 Typical Performance Characteristics ..............................................7 Typical Applications....................................................................... 11 Applications Information.......................................................... 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 14 REVISION HISTORY 7/06—Rev. C. to Rev D Changes to Features.......................................................................... 1 Changes to General Description .................................................... 1 Changes to Specifications Section.................................................. 3 Changes to Table 4............................................................................ 6 Changes to Figure 6 and Figure 8................................................... 7 Changes to Figure 13 and Figure 14............................................... 8 Changes to Figure 20........................................................................ 9 Changes to Figure 21 to Figure 25................................................ 10 Changes to Figure 26 and Figure 30............................................. 11 Replaced Figure 28 ......................................................................... 11 Changes to Applications Information Section............................ 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 8/03—Rev. B to Rev. C Changes to OP07E Electrical Specifications ................................. 2 Changes to OP07C Electrical Specifications................................. 3 Edits to Ordering Guide .................................................................. 5 Edits to Figure 6 ................................................................................ 9 Updated Outline Dimensions ....................................................... 11 3/03—Rev. A to Rev. B Updated Package Titles......................................................Universal Updated Outline Dimensions....................................................... 11 2/02—Rev. 0 to Rev. A Edits to Features.................................................................................1 Edits to Ordering Guide ...................................................................1 Edits to Pin Connection Drawings .................................................1 Edits to Absolute Maximum Ratings ..............................................2 Deleted Electrical Characteristics .............................................. 2–3 Deleted OP07D Column from Electrical Characteristics....... 4–5 Edits to TPCs ................................................................................ 7–9 Edits to High-Speed, Low VOS Composite Amplifier ...................9 Rev. D | Page 2 of 16 OP07 SPECIFICATIONS OP07E ELECTRICAL CHARACTERISTICS VS = ±15 V, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS TA = 25°C Input Offset Voltage 1 Long-Term VOS Stability 2 Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Symbol Conditions Min Typ Max Unit VOS VOS/Time IOS IB en p-p en 0.1 Hz to 10 Hz 3 fO = 10 Hz fO = 100 Hz3 fO = 1 kHz fO = 10 Hz fO = 100 Hz3 fO = 1 kHz 15 ±13 106 200 150 Input Noise Current Input Noise Current Density In p-p In Input Resistance, Differential Mode 4 Input Resistance, Common Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain 0°C ≤ TA ≤ 70°C Input Offset Voltage1 Voltage Drift Without External Trim4 Voltage Drift with External Trim3 Input Offset Current Input Offset Current Drift Input Bias Current Input Bias Current Drift Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain OUTPUT CHARACTERISTICS TA = 25°C Output Voltage Swing RIN RINCM IVR CMRR PSRR AVO VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 30 0.3 0.5 ±1.2 0.35 10.3 10.0 9.6 14 0.32 0.14 0.12 50 160 ±14 123 5 500 400 45 0.3 0.3 0.9 8 ±1.5 13 ±13.5 123 7 450 75 1.5 3.8 ±4.0 0.6 18.0 13.0 11.0 30 0.80 0.23 0.17 20 μV μV/Month nA nA μV p-p nV/√Hz nV/√Hz nV/√Hz pA p-p pA/√Hz pA/√Hz pA/√Hz MΩ GΩ V dB μV/V V/mV V/mV μV μV/°C μV/°C nA pA/°C nA pA/°C V dB μV/V V/mV VOS TCVOS TCVOSN IOS TCIOS IB TCIB IVR CMRR PSRR AVO RP = 20 kΩ 130 1.3 1.3 5.3 35 ±5.5 35 VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V ±13 103 180 32 VO RL ≥ 10 kΩ RL ≥ 2 kΩ RL ≥ 1 kΩ RL ≥ 2 kΩ ±12.5 ±12.0 ±10.5 ±12 ±13.0 ±12.8 ±12.0 ±12.6 V V V V 0°C ≤ TA ≤ 70°C Output Voltage Swing VO Rev. D | Page 3 of 16 OP07 Parameter DYNAMIC PERFORMANCE TA = 25°C Slew Rate Closed-Loop Bandwidth Open-Loop Output Resistance Power Consumption Offset Adjustment Range 1 2 Symbol Conditions Min Typ Max Unit SR BW RO Pd RL ≥ 2 kΩ3 AVOL = 1 5 VO = 0, IO = 0 VS = ±15 V, No load VS = ±3 V, No load RP = 20 kΩ 0.1 0.4 0.3 0.6 60 75 4 ±4 120 6 V/μs MHz Ω mW mW mV Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is sample tested. 3 Sample tested. 4 Guaranteed by design. 5 Guaranteed but not tested. OP07C ELECTRICAL CHARACTERISTICS VS = ±15 V, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS TA = 25°C Input Offset Voltage 1 Long-Term VOS Stability 2 Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density Symbol Conditions Min Typ Max Unit VOS VOS/Time IOS IB en p-p en 0.1 Hz to 10 Hz3 fO = 10 Hz fO = 100 Hz 3 fO = 1 kHz fO = 10 Hz fO = 100 Hz3 fO = 1 kHz 8 ±13 100 120 100 Input Noise Current Input Noise Current Density In p-p In Input Resistance, Differential Mode 4 Input Resistance, Common Mode Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain −40°C ≤ TA ≤ +85°C Input Offset Voltage1 Voltage Drift Without External Trim4 Voltage Drift with External Trim3 Input Offset Current Input Offset Current Drift Input Bias Current Input Bias Current Drift Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain RIN RINCM IVR CMRR PSRR AVO VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V4 60 0.4 0.8 ±1.8 0.38 10.5 10.2 9.8 15 0.35 0.15 0.13 33 120 ±14 120 7 400 400 85 0.5 0.4 1.6 12 ±2.2 18 ±13.5 120 10 400 150 2.0 6.0 ±7.0 0.65 20.0 13.5 11.5 35 0.90 0.27 0.18 32 μV μV/Month nA nA μV p-p nV/√Hz nV/√Hz nV/√Hz pA p-p pA/√Hz pA/√Hz pA/√Hz MΩ GΩ V dB μV/V V/mV V/mV μV μV/°C μV/°C nA pA/°C nA pA/°C V dB μV/V V/mV VOS TCVOS TCVOSN IOS TCIOS IB TCIB IVR CMRR PSRR AVO RP = 20 kΩ 250 1.8 1.6 8.0 50 ±9.0 50 VCM = ±13 V VS = ±3 V to ±18 V RL ≥ 2 kΩ, VO = ±10 V Rev. D | Page 4 of 16 ±13 97 100 51 OP07 Parameter OUTPUT CHARACTERISTICS TA = 25°C Output Voltage Swing Symbol Conditions Min Typ Max Unit VO RL ≥ 10 kΩ RL ≥ 2 kΩ RL ≥ 1 kΩ RL ≥ 2 kΩ ±12.0 ±11.5 ±13.0 ±12.8 ±12.0 ±12.6 V V V V −40°C ≤ TA ≤ +85°C Output Voltage Swing DYNAMIC PERFORMANCE TA = 25°C Slew Rate Closed-Loop Bandwidth Open-Loop Output Resistance Power Consumption Offset Adjustment Range 1 2 VO ±12 SR BW RO Pd RL ≥ 2 kΩ3 AVOL = 1 5 VO = 0, IO = 0 VS = ±15 V, No load VS = ±3 V, No load RP = 20 kΩ 0.1 0.4 0.3 0.6 60 80 4 ±4 150 8 V/μs MHz Ω mW mW mV Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is sample tested. 3 Sample tested. 4 Guaranteed by design. 5 Guaranteed but not tested. Rev. D | Page 5 of 16 OP07 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage (VS) Input Voltage1 Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range S and P Packages Operating Temperature Range OP07E OP07C Junction Temperature Lead Temperature, Soldering (60 sec) 1 Ratings ±22 V ±22 V ±30 V Indefinite −65°C to +125°C 0°C to 70°C −40°C to +85°C 150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 8-Lead PDIP (P-Suffix) 8-Lead SOIC_N (S-Suffix) θJA 103 158 θJC 43 43 Unit °C/W °C/W For supply voltages less than ±22 V, the absolute maximum input voltage is equal to the supply voltage. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 6 of 16 OP07 TYPICAL PERFORMANCE CHARACTERISTICS 1000 900 800 1.0 MAXIMUM ERROR REFERRED TO INPUT (mV) VS = ±15V VS = ±15V TA = 25°C 0.8 OPEN-LOOP GAIN (V/mV) 700 600 500 400 300 200 100 00316-003 0.6 0.4 0.2 OP07C OP07E 1k 10k 100k 00316-006 00316-008 0 –75 –50 –25 0 25 50 75 100 125 0 100 TEMPERATURE (°C) MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω) Figure 3. Open-Loop Gain vs. Temperature 30 1.2 Figure 6. Maximum Error vs. Source Resistance MAXIMUM ERROR REFERRED TO INPUT (mV) VS = ±15V 0°C ≤ TA ≤ 70°C 1.0 VS = ±15V TA = 25°C, TA = 70°C 25 ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µV) 20 0.8 15 10 THERMAL SHOCK RESPONSE BAND 0.6 0.4 OP07C 0.2 OP07E 1k 10k 100k 00316-007 5 DEVICE IMMERSED IN 70°C OIL BATH 0 20 40 TIME (Seconds) 60 80 100 00316-004 0 –20 0 100 MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω) Figure 4. Offset Voltage Change due to Thermal Shock 25 NONINVERTING INPUT BIAS CURRENT (nA) Figure 7. Maximum Error vs. Source Resistance 30 AT |VDIFF| ≤ 1.0V, | IB | ≤ 7nA (OP07C) VS = ±15V TA = 25°C VS = ±15V TA = 25°C ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µV) 20 20 10 15 0 10 OP07C OP07E –10 5 –20 0 1 2 3 4 5 00316-005 0 –30 –30 –20 –10 0 10 20 30 TIME AFTER SUPPLY TURN-ON (Minutes) DIFFERENTIAL INPUT VALUE (V) Figure 5. Warm-Up Drift Figure 8. Input Bias Current vs. Differential Input Voltage Rev. D | Page 7 of 16 OP07 4 VS = ±15V 1000 RS1 = RS2 = 200kΩ THERMAL NOISE SOURCE RESISTORS INCLUDED EXCLUDED 100 INPUT BIAS CURRENT (nA) 3 OP07C 2 INPUT NOISE VOLTAGE (nV/ Hz) 10 RS = 0 1 OP07E VS = ±15V TA = 25°C 00316-009 –50 –25 0 25 50 75 100 125 1 10 100 FREQUENCY (Hz) 1000 TEMPERATURE (°C) Figure 9. Input Bias Current vs. Temperature 2.5 VS = ±15V 2.0 10 Figure 12. Total Input Noise Voltage vs. Frequency VS = ±15V TA = 25°C INPUT OFFSET CURRENT (nA) 1.5 RMS NOISE (µV) 1 1.0 OP07C 0.5 OP07E 00316-010 –75 –50 –25 0 25 50 75 100 1k 10k BANDWIDTH (Hz) 100k TEMPERATURE (°C) Figure 10. Input Offset Current vs. Temperature 130 Figure 13. Input Wideband Noise vs. Bandwidth, 0.1 Hz to Frequency Indicated REFERRED TO INPUT 5mV/CM AT OUTPUT 120 110 VOLTAGE (200nV/DIV) OP07C CMRR (dB) 100 90 80 70 60 00316-011 1 10 100 1k 10k 100k TIME (1s/DIV) FREQUENCY (Hz) Figure 11. Low Frequency Noise Figure 14. CMRR vs. Frequency Rev. D | Page 8 of 16 00316-014 00316-013 0 –100 0.1 100 00316-012 0 –75 1 OP07 120 TA = 25°C 110 OP07C 100 80 100 VS = ±15V TA = 25°C CLOSED-LOOP GAIN (dB) 00316-015 60 PSRR (dB) 90 80 70 60 50 0.1 40 20 0 1 10 100 1k 10k 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. PSRR vs. Frequency 1000 TA = 25°C Figure 18. Closed-Loop Frequency Response for Various Gain Configurations 28 24 PEAK-TO-PEAK AMPLITUDE (V) VS = ±15V TA = 25°C 800 OPEN-LOOP GAIN (V/mV) 20 16 12 8 4 600 400 200 00316-016 0 ±5 ±10 ±15 ±20 10k 100k FREQUENCY (Hz) 1M POWER SUPPLY VOLTAGE (V) Figure 16. Open-Loop Gain vs. Power Supply Voltage 120 100 80 60 40 20 0 –20 –40 0.1 0 100 VS = ±15V TA = 25°C 20 Figure 19. Maximum Output Swing vs. Frequency VS = ±15V VIN = ±10mV TA = 25°C 15 OPEN-LOOP GAIN (dB) MAXIMUM OUTPUT (V) POSITIVE SWING NEGATIVE SWING 10 5 00316-017 1 10 100 1k 10k 100k 1M 10M 1k LOAD RESISTANCE TO GROUND (Ω) 10k FREQUENCY (Hz) Figure 17. Open-Loop Frequency Response Figure 20. Maximum Output Voltage vs. Load Resistance Rev. D | Page 9 of 16 00316-020 00316-019 0 0 1k 00316-018 –20 10 OP07 1000 ABSOLUTE VALUE OF OFFSET VOLTAGE (µV) TA = 25°C 30.0 VOS TRIMMED TO < 5µV AT 25°C NULLING POT = 20kΩ 22.5 OP07C 15.0 OP07C OP07E OP07E POWER CONSUMPTION (mW) 100 10 7.5 00316-021 0 10 20 30 40 50 60 –75 –50 –25 0 25 50 75 100 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) TEMPERATURE (°C) Figure 21. Power Consumption vs. Power Supply 35 OUTPUT SHORT-CIRCUIT CURRENT (mA) VS = ±15V TA = 25°C TOTAL DRIFT WITH TIME (µV) Figure 24. Trimmed Offset Voltage vs. Temperature 16 12 8 4 0 –4 –8 –12 0.3µV/MONTH TREND LINE 0.3µV/MONTH TREND LINE 0.3µV/MONTH TREND LINE 0.2µV/MONTH TREND LINE 0.2µV/MONTH TREND LINE 30 25 VIN (PIN 3) = +10mV, VO = –15V 0.2µV/MONTH TREND LINE 20 VIN (PIN 3) = –10mV, VO = +15V 00316-022 0 1 2 3 4 0 1 2 3 4 5 6 7 8 9 10 11 12 TIME FROM OUTPUT BEING SHORTED (Minutes) TIME (Months) Figure 22. Output Short-Circuit Current vs. Time 85.00 Figure 25. Offset Voltage Drift vs. Time ABSOLUTE VALUE OF OFFSET VOLTAGE (µV) VS = ±15V RS = 100Ω OP07C 63.75 42.50 OP07E 21.25 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 23. Untrimmed Offset Voltage vs. Temperature 00316-023 0 –75 Rev. D | Page 10 of 16 00316-025 15 –16 00316-024 1 0 –100 OP07 TYPICAL APPLICATIONS RF EIN R1 SUM MODE BIAS R3 10kΩ R4 10kΩ R5 10kΩ V+ V+ 7 V+ V+ 2 7 R3 3kΩ 2 – AD7115 OR AD8510 6 EO EIN ±10V – R1 10kΩ OP07C 3 R5 6 10kΩ R2 100kΩ 2 7 FD333 D1 2 7 – – 3 A1 + 4 V– + 4 V– 00316-026 OP07 3 6 3 FD333 D2 R2 10kΩ OP07 + 4 V– R1 R2 = R3 R4 6 EO 0V TO +10V + 4 V– EO = –EIN RF –IB RF R1 Figure 26. Typical Offset Voltage Test Circuit R1 Figure 29. Burn-In Circuit RF EIN SUM MODE BIAS V+ 7 R4 10kΩ R1 10kΩ R2 10kΩ R3 10kΩ V+ 2 7 R3 3kΩ 2 – E1 E2 E3 +15V 2 7 – OP07C 6 3 EO R1 6 10kΩ R2 100kΩ OP07C 3 6 A2 + 4 V– EO – A1 4 OP07C 3 R5 2.5kΩ + V– + 00316-027 –15V NOTES 1. PINOUT SHOWN FOR P PACKAGE Figure 27. Typical Low Frequency Noise Circuit Figure 30. High Speed, Low VOS Composite Amplifier R4 10kΩ R1 10kΩ R2 10kΩ R3 10kΩ E1 20kΩ – INPUT + 3 1 2 V+ 8 7 +15V 2 7 E2 E3 – – OP07 + 4 6 OP07 3 R5 2.5kΩ 6 EO OUT + 4 00316-031 00316-028 –15V NOTES 1. PINOUT SHOWN FOR P PACKAGE V– Figure 28. Optional Offset Nulling Circuit Figure 31. Adjustment-Free Precision Summing Amplifier Rev. D | Page 11 of 16 00316-030 4 EO = –EIN RF + IB RF R1 00316-029 OP07 R1 SENDING JUNCTION R3 APPLICATIONS INFORMATION The OP07 provides stable operation with load capacitance of up to 500 pF and ±10 V swings; larger capacitances should be decoupled with a 50 Ω decoupling resistor. 6 EO V+ 2 7 – REFERENCE JUNCTION OP07 R2 R4 3 + 4 V– R1 R2 = R3 R4 NOTES 1. PINOUT SHOWN FOR P PACKAGE Figure 32. High Stability Thermocouple Amplifier R3 10kΩ R4 10kΩ R5 10kΩ V+ V+ EIN ±10V R1 10kΩ 2 7 FD333 D1 6 3 FD333 D2 R2 10kΩ VA 00316-033 2 7 – – OP07 A1 3 OP07 A2 + 4 V– 6 EO 0V TO +10V + 4 V– NOTES 1. PINOUT SHOWN FOR P PACKAGE Figure 33. Precision Absolute-Value Circuit 00316-032 Stray thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals can degrade drift performance. Therefore, best operation is obtained when both input contacts are maintained at the same temperature, preferably close to the package temperature. Rev. D | Page 12 of 16 OP07 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45° 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 34. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 1 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 060506-A Figure 35. 8-Lead Plastic Dual-in-Line Package [PDIP] P-Suffix (N-8) Dimensions shown in inches and (millimeters) Rev. D | Page 13 of 16 070606-A OP07 ORDERING GUIDE Model OP07EP OP07EPZ 1 OP07CP OP07CPZ1 OP07CS OP07CS-REEL OP07CS-REEL7 OP07CSZ1 OP07CSZ-REEL1 OP07CSZ-REEL71 1 Temperature Range 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option N-8 (P-Suffix) N-8 (P-Suffix) N-8 (P-Suffix) N-8 (P-Suffix) R-8 (S-Suffix) R-8 (S-Suffix) R-8 (S-Suffix) R-8 (S-Suffix) R-8 (S-Suffix) R-8 (S-Suffix) Z = Pb-free part. Rev. D | Page 14 of 16 OP07 NOTES Rev. D | Page 15 of 16 OP07 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00316-0-7/06(D) Rev. D | Page 16 of 16