OP275GSR

a FEATURES Excellent Sonic Characteristics Low Noise: 6 nV/√Hz Low Distortion: 0.0006% High Slew Rate: 22 V/ s Wide Bandwidth: 9 MHz Low Supply Current: 5 mA Low Offset Voltage: 1 mV Low Offset Current: 2 nA Unity Gain Stable SOIC-8 Package APPLICATIONS High Performance Audio Active Filters Fast Amplifiers Integrators GENERAL DESCRIPTION OUT A 1 –IN A 2 +IN A 3 V– 4 Dual Bipolar/JFET, Audio Operational Amplifier OP275* PIN CONNECTIONS 8-Lead Narrow-Body SO (S Suffix) 8 8-Lead Epoxy DIP (P Suffix) V+ OUT B –IN B +IN B OUT A –IN A +IN A V– 1 2 3 4 OP275 8 7 6 5 V+ OUT B –IN B +IN B OP275 7 6 5 The OP275 is the first amplifier to feature the Butler Amplifier front-end. This new front-end design combines both bipolar and JFET transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of JFETs. Total Harmonic Distortion plus Noise equals that of previous audio amplifiers, but at much lower supply currents. A very low l/f corner of below 6 Hz maintains a flat noise density response. Whether noise is measured at either 30 Hz or 1 kHz, it is only 6 nV/√Hz. The JFET portion of the input stage gives the OP275 its high slew rates to keep distortion low, even when large output swings are required, and the 22 V/µs slew rate of the OP275 is the fastest of any standard audio amplifier. Best of all, this low noise and high speed are accomplished using less than 5 mA of supply current, lower than any standard audio amplifier. Improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. Input offset voltage is guaranteed at 1 mV and is typically less than 200 µV. This allows the OP275 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. The output is capable of driving 600 Ω loads to 10 V rms while maintaining low distortion. THD + Noise at 3 V rms is a low 0.0006%. The OP275 is specified over the extended industrial (–40°C to +85°C) temperature range. OP275s are available in both plastic DIP and SOIC-8 packages. SOIC-8 packages are available in 2500 piece reels. Many audio amplifiers are not offered in SOIC-8 surface mount packages for a variety of reasons; however, the OP275 was designed so that it would offer full performance in surface mount packaging. *Protected by U.S. Patent No. 5,101,126. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 OP275–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = S 15.0 V, TA = +25 C unless otherwise noted) Conditions VIN = 3 V rms, RL = 2 kΩ, f = 1 kHz f = 30 Hz f = 1 kHz f = 1 kHz THD + Noise ≤ 0.01%, RL = 2 kΩ, VS = ± 18 V Min Typ Max Units Parameter AUDIO PERFORMANCE THD + Noise Voltage Noise Density Current Noise Density Headroom INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Symbol en in 0.006 7 6 1.5 >12.9 1 1.25 350 400 50 100 +10.5 % nV/√Hz nV/√Hz pA/√Hz dBu mV mV nA nA nA nA V dB V/mV V/mV V/mV µV/°C V V V dB dB VOS IB IOS VCM CMRR AVO ∆VOS/∆T VO –40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, –40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, –40°C ≤ TA ≤ +85°C VCM = ± 10.5 V, –40°C ≤ TA ≤ +85°C RL = 2 kΩ RL = 2 kΩ, –40°C ≤ TA ≤ +85°C RL = 600 Ω –10.5 80 250 175 100 100 2 2 106 Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing 200 2 –13.5 –13 ± 13.9 +13.5 ± 13.9 +13 +14, –16 111 RL = 2 kΩ RL = 2 kΩ, –40°C ≤ TA ≤ +85°C RL = 600 Ω, VS = ± 18 V VS = ± 4.5 V to ± 18 V VS = ± 4.5 V to ± 18 V, –40°C ≤ TA ≤ +85°C VS = ± 4.5 V to ± 18 V, VO = 0 V, RL = ∞, –40°C ≤ TA ≤ +85°C VS = ± 22 V, VO = 0 V, RL = ∞, –40°C ≤ TA ≤ +85°C POWER SUPPLY Power Supply Rejection Ratio PSRR 85 80 Supply Current ISY 4 ± 4.5 15 22 9 62 5 5.5 ± 22 mA mA V V/µs kHz MHz Degrees % Supply Voltage Range DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Gain Bandwidth Product Phase Margin Overshoot Factor Specifications subject to change without notice. VS SR BWP GBP øm RL = 2 kΩ VIN = 100 mV, AV = +1, RL = 600 Ω, CL = 100 pF 10 –2– REV. A OP275 WAFER TEST LIMITS (@ V = S 15.0 V, TA = +25 C unless otherwise noted) Symbol VOS IB IOS VCM CMRR PSRR AVO VO ISY Conditions VCM = 0 V VCM = 0 V VCM = ± 10.5 V V = ± 4.5 V to ± 18 V RL = 2 kΩ RL = 10 kΩ V O = 0 V , RL = ∞ Limit 1 350 50 ± 10.5 80 85 250 ± 13.5 5 Units mV max nA max nA max V min dB min dB min V/mV min V min mA max Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range1 Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 Guaranteed by CMRR test. Specifications subject to change without notice. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ± 7.5 V Output Short-Circuit Duration to GND3 . . . . . . . . . Indefinite Storage Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP275G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Type 8-Pin Plastic DIP (P) 8-Pin SOIC (S) θJA4 103 158 θJC 43 43 Units °C/W °C/W ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Model OP275GP OP275GS OP275GSR OP275GBC Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C +25°C Package Option 8-Pin Plastic DIP 8-Pin SOIC SO-8 Reel, 2500 pcs. DICE DICE CHARACTERISTICS NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages greater than ± 22 V, the absolute maximum input voltage is equal to the supply voltage. 3 Shorts to either supply may destroy the device. See data sheet for full details. 4 θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered in circuit board for SOIC package. Die Size 0.070 × 0.108 in. (7,560 sq. mils) Substrate is connected to V– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP275 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A –3– OP275–Typical Performance Curves 25 20 TA = +25°C RL = 2kΩ +VOM 1500 VS = ±15V VO = ±10V +GAIN RL = 2kΩ 1000 –GAIN RL = 2kΩ +GAIN RL = 600Ω –GAIN RL = 600Ω GAIN – dB 40 30 20 10 0 –10 –20 –30 –40 75 100 10k 100k 1M OUTPUT VOLTAGE SWING – V 1250 OPEN-LOOP GAIN – V/mV 15 10 5 0 –5 –10 –15 –20 –25 0 ±5 VS = ±15V TA = +25°C 180 135 PHASE – Degrees PHASE – Degrees 90 45 0 –45 –90 –135 –180 10M 750 500 –VOM 250 ±10 ±15 ±20 SUPPLY VOLTAGE – V ±25 0 –50 –25 0 25 50 TEMPERATURE – °C FREQUENCY – Hz Output Voltage Swing vs. Supply Voltage Open-Loop Gain vs. Temperature Closed-Loop Gain and Phase, AV = +1 50 60 VS = ±15V TA = +25°C 50 VS = ±15V TA = +25°C AVCL = +1 AVCL = +10 30 AVCL = +100 60 50 40 GAIN – dB MARKER 15 309.059Hz MAG (A/H) 60.115dB CLOSED-LOOP GAIN – dB VS = ±15V TA = +25°C 40 30 20 AVCL = +100 30 20 10 0 –10 –20 10k 100k 1M 10M MARKER 15 309.058Hz PHASE (A/R 90.606Deg 135 90 45 0 –45 –90 PHASE – Degrees AVCL = +10 10 0 –10 IMPEDANCE – Ω 40 AVCL = +1 20 10 –20 –30 1k 10k 100k 1M 10M FREQUENCY – Hz 100M 0 100 1k 10k 100k FREQUENCY – Hz 1M 10M FREQUENCY – Hz Open-Loop Gain, Phase vs. Frequency Closed-Loop Gain vs. Frequency Closed-Loop Output Impedance vs. Frequency 100 80 VS = ±15V RL = 2kΩ TA = +25°C Ø m = 58° 0 45 90 135 180 225 270 10k 100k 1M 10M FREQUENCY – Hz 100M 120 COMMON-MODE REJECTION – dB 120 POWER SUPPLY REJECTION – dB 100 VS = ±15V TA = +25°C 100 OPEN-LOOP GAIN – dB GAIN +PSRR 60 40 PHASE 20 0 –20 –40 –60 1k 80 80 VS = ±15V TA = +25°C –PSRR 60 60 40 40 20 20 0 100 1k 10k 100k FREQUENCY – Hz 1M 10M 0 10 100 1k 10k 100k FREQUENCY – Hz 1M Common-Mode Rejection vs. Frequency Power Supply Rejection vs. Frequency Open-Loop Gain, Phase vs. Frequency –4– REV. A OP275 11 65 100 90 10 60 MAXIMUM OUTPUT SWING – V 16 GAIN BANDWIDTH PRODUCT – MHz AVCL = +1 NEGATIVE EDGE 14 12 10 8 6 4 2 OVERSHOOT – % Øm PHASE MARGIN – Degrees 80 70 60 50 40 30 20 10 VS = ±15V RL = 2kΩ VIN = 100mV p-p AVCL = +1 POSITIVE EDGE –VOM 9 GBW 8 55 +VOM 50 TA = +25°C VS = ±15V 7 –50 –25 0 25 50 TEMPERATURE – °C 75 40 100 0 0 200 300 400 100 LOAD CAPACITANCE – pF 500 0 100 1k LOAD RESISTANCE – Ω 10k Gain Bandwidth Product, Phase Margin vs. Temperature Small-Signal Overshoot vs. Load Capacitance Maximum Output Voltage vs. Load Resistance 30 5.0 120 ABSOLUTE OUTPUT CURRENT – mA 110 100 90 80 70 60 50 40 30 20 –50 –25 SOURCE SINK VS = ±15V MAXIMUM OUTPUT SWING – V 25 SUPPLY CURRENT – mA 4.5 TA = +85°C 4.0 TA = +25°C TA = –40°C 3.5 20 15 TA = +25°C VS = ±15V AVCL = +1 RL = 2kΩ 10 5 0 1k 10k 100k 1M FREQUENCY – Hz 10M 3.0 0 ±5 ±10 ±15 ±20 SUPPLY VOLTAGE – V ±25 0 25 50 TEMPERATURE – °C 75 100 Maximum Output Swing vs. Frequency Supply Current vs. Supply Voltage Short Circuit Current vs. Temperature 300 5 500 VS = ±15V TA = +25°C CURRENT NOISE DENSITY – pA/ Hz VS = ±15V INPUT BIAS CURRENT – nA VS = ±15V –40°C to +85°C 400 BASED ON 920 OP AMPS 250 4 200 3 300 150 UNITS 2 1 200 100 100 50 0 –50 0 –25 0 25 50 TEMPERATURE – °C 75 100 10 100 1k FREQUENCY – Hz 100k 0 1 2 3 4 5 67 TCVOS – µ V/ °C 8 9 10 Input Bias Current vs. Temperature Current Noise Density vs. Frequency TCVOS Distribution REV. A –5– OP275–Typical Performance Curves 200 BASED ON 920 OP AMPS 160 VS = ±15V TA = +25°C 10 8 6 4 STEP SIZE – V 50 TA = +25°C VS = ±15V 45 +0.1% +0.01% SLEW RATE – V/µs 40 120 2 0 –2 –4 –0.1% –6 –8 –0.01% UNITS 35 –SR 80 30 +SR 25 40 0 –500–400–300–200–100 0 100 200 300 400 500 INPUT OFFSET VOLTAGE – µV –10 20 0 100 200 300 400 500 600 700 800 900 SETTLING TIME – ns 0 200 300 400 100 CAPACITIVE LOAD – pF 500 Input Offset (VOS) Distribution 40 35 SLEW RATE – V/µs 30 25 20 15 10 5 0 0 .2 .4 .6 VS = ±15V RL = 2kΩ TA = +25°C Settling Time vs. Step Size 50 VS = ±15V RL = 2kΩ Slew Rate vs. Capacitive Load 45 –SR SLEW RATE – V/µs 40 35 30 +SR 25 .8 1.0 20 –50 –25 DIFFERENTIAL INPUT VOLTAGE – V 0 25 50 TEMPERATURE – °C 75 100 Slew Rate vs. Differential Input Voltage Slew Rate vs. Temperature 100 90 100 90 10 0% 10 0% 5V 200ns 5V 200ns Negative Slew Rate RL = 2 kΩ, VS = ± 15 V, AV = +1 Positive Slew Rate RL = 2 kΩ, VS = ± 15 V, AV = +1 CH A: 80.0 µV FS MKR: 6.23 nV/√Hz 100 90 10.0 µV/DIV 10 0% 50mV 100ns 0 Hz MKR: 1 000 Hz 2.5 kHz BW: 15.0 MHz Small Signal Response RL = 2 kΩ, VS = ± 15 V, AV = +1 Voltage Noise Density vs. Frequency VS = ± 15 V –6– REV. A OP275 The OP275 has been designed with inherent short circuit protection to ground. An internal 30 Ω resistor, in series with the output, limits the output current at room temperature to ISC + = 40 mA and ISC– = –90 mA, typically, with ± 15 V supplies. However, shorts to either supply may destroy the device when excessive voltages or currents are applied. If it is possible for a user to short an output to a supply, for safe operation, the output current of the OP275 should be design-limited to ± 30 mA, as shown in Figure 1. Total Harmonic Distortion THD + NOISE – % APPLICATIONS Short Circuit Protection 0.010 VS = ±18V RL = 600Ω 0.001 0.0001 0.5 1 OUTPUT SWING – V rms 10 Figure 4. Headroom, THD + Noise vs. Output Amplitude (V rms); RLOAD = 600 Ω, VSUP = ± 18 V Total Harmonic Distortion + Noise (THD + N) of the OP275 is well below 0.001% with any load down to 600 Ω. However, this is dependent upon the peak output swing. In Figure 2 it is seen that the THD + Noise with 3 V rms output is below 0.001%. In the following Figure 3, THD + Noise is below 0.001% for the 10 kΩ and 2 kΩ loads but increases to above 0.1% for the 600 Ω load condition. This is a result of the output swing capability of the OP275. Notice the results in Figure 4, showing THD vs. VIN (V rms). This figure shows that the THD + Noise remains very low until the output reaches 9.5 volts rms. This performance is similar to competitive products. RFB The output of the OP275 is designed to maintain low harmonic distortion while driving 600 Ω loads. However, driving 600 Ω loads with very high output swings results in higher distortion if clipping occurs. A common example of this is in attempting to drive 10 V rms into any load with ± 15 volt supplies. Clipping will occur and distortion will be very high. To attain low harmonic distortion with large output swings, supply voltages may be increased. Figure 5 shows the performance of the OP275 driving 600 Ω loads with supply voltages varying from ± 18 volts to ± 20 volts. Notice that with ± 18 volt supplies the distortion is fairly high, while with ± 20 volt supplies it is a very low 0.0007%. 0.0001 FEEDBACK A1 RX 332Ω VOUT A1 = 1/2 OP275 THD – % 0.001 RL = 600Ω VOUT = 10 Vrms @ 1kHz 0.01 Figure 1. Recommended Output Short Circuit Protection 0.010 THD + NOISE – % RL = 600Ω, 2k, 10k VS = ±15V VIN = 3V rms AV = +1 0.1 0.001 0 ±17 ±18 ±19 ±20 SUPPLY VOLTAGE – V ±21 ±22 0.0005 20 100 1k 10k 20k FREQUENCY – Hz Figure 5. THD + Noise vs. Supply Voltage Figure 2. THD + Noise vs. Frequency vs. RLOAD 1 THD + NOISE – % 0.1 600Ω AV = +1 VS = ±18V VIN = 10V rms 80kHz FILTER 2k The voltage noise density of the OP275 is below 7 nV/√Hz from 30 Hz. This enables low noise designs to have good performance throughout the full audio range. Figure 6 shows a typical OP275 with a 1/f corner at 2.24 Hz. CH A: 80.0 µV FS MKR: 45.6 µV/√Hz 10.0 µV/DIV Noise 0.010 0.001 10k 0.0001 20 100 1k 10k 20k FREQUENCY – Hz Figure 3. THD + Noise vs. RLOAD; VIN =10 V rms, ± 18 V Supplies 0 Hz MKR: 2.24 Hz 10 Hz BW: 0.145 Hz Figure 6. 1/f Noise Corner, VS = ± 15 V, AV = 1000 REV. A –7– OP275 Noise Testing For audio applications the noise density is usually the most important noise parameter. For characterization the OP275 is tested using an Audio Precision, System One. The input signal to the Audio Precision must be amplified enough to measure it accurately. For the OP275 the noise is gained by approximately 1020 using the circuit shown in Figure 7. Any readings on the Audio Precision must then be divided by the gain. In implementing this test fixture, good supply bypassing is essential. 100Ω 909Ω this effect from occurring in noninverting applications. For these applications, the fix is a simple one and is illustrated in Figure 9. A 3.92 kΩ resistor in series with the noninverting input of the OP275 cures the problem. RFB* VOUT VIN RS 3.92kΩ *RFB IS OPTIONAL RL 2kΩ A Figure 9. Output Voltage Phase Reversal Fix OP37 OP37 OUTPUT 909Ω 100Ω 4.42kΩ 490Ω OP275 B Overload, or Overdrive, Recovery 100Ω 909Ω Figure 7. Noise Test Fixture Input Overcurrent Protection Overload, or overdrive, recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output voltage from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event. The circuit shown in Figure 10 was used to evaluate the OP275’s overload recovery time. The OP275 takes approximately 1.2 µs to recover to VOUT = +10 V and approximately 1.5 µs to recover to VOUT = –10 V. R1 1kΩ 2 3 VIN 4V p-p @100Hz RS 909Ω A1 1 RL 2.43kΩ VOUT R2 10kΩ The maximum input differential voltage that can be applied to the OP275 is determined by a pair of internal Zener diodes connected across its inputs. They limit the maximum differential input voltage to ± 7.5 V. This is to prevent emitter-base junction breakdown from occurring in the input stage of the OP275 when very large differential voltages are applied. However, in order to preserve the OP275’s low input noise voltage, internal resistances in series with the inputs were not used to limit the current in the clamp diodes. In small signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large transient currents can flow through these diodes. Although these diodes have been designed to carry a current of ± 5 mA, external resistors as shown in Figure 8 should be used in the event that the OP275’s differential voltage were to exceed ± 7.5 V. 1.4kΩ 2 – OP275 + 6 A1 = 1/2 OP275 Figure 10. Overload Recovery Time Test Circuit Measuring Settling Time 1.4kΩ 3 Figure 8. Input Overcurrent Protection Output Voltage Phase Reversal The design of OP275 combines high slew rate and wide gainbandwidth product to produce a fast-settling (tS < 1 µs) amplifier for 8- and 12-bit applications. The test circuit designed to measure the settling time of the OP275 is shown in Figure 11. This test method has advantages over false-sum node techniques in that the actual output of the amplifier is measured, instead of an error voltage at the sum node. Common-mode settling effects are exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum-node method. Of course, a reasonably flat-top pulse is required as the stimulus. The output waveform of the OP275 under test is clamped by Schottky diodes and buffered by the JFET source follower. The signal is amplified by a factor of ten by the OP260 and then Schottky-clamped at the output to prevent overloading the oscilloscope’s input amplifier. The OP41 is configured as a fast integrator which provides overall dc offset nulling. High Speed Operation Since the OP275’s input stage combines bipolar transistors for low noise and p-channel JFETs for high speed performance, the output voltage of the OP275 may exhibit phase reversal if either of its inputs exceed its negative common-mode input voltage. This might occur in very severe industrial applications where a sensor, or system, fault might apply very large voltages on the inputs of the OP275. Even though the input voltage range of the OP275 is ± 10.5 V, an input voltage of approximately –13.5 V will cause output voltage phase reversal. In inverting amplifier configurations, the OP275’s internal 7.5 V input clamping diodes will prevent phase reversal; however, they will not prevent As with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. Recommended circuit configurations for inverting and noninverting applications are shown in Figures 12 and Figure 13. –8– REV. A OP275 16–20V – + +15V 0.1µF V+ DUT V– 0.1µF D1 D2 RF 2kΩ 10kΩ 10kΩ RG 222Ω 2N2222A 1N4148 15kΩ SCHOTTKY DIODES D1–D4 ARE HEWLETT-PACKARD HP5082-2835 IC1 IS 1/2 OP260AJ IC2 IS PMI OP41EJ IC2 RL 1kΩ 2N4416 1/2 OP260AJ 1µF D3 D4 1kΩ OUTPUT (TO SCOPE) + – 16–20V ±5V 750Ω –15V Figure 11. OP275’s Settling Time Test Fixture CFB +15V 10µF + RFB 0.1µF 2 RS CS 8 1/2 OP275 1 RL 2kΩ VOUT CIN VOUT VIN 3 4 0.1µF 10µF + Figure 14. Compensating the Feedback Pole Attention to Source Impedances Minimizes Distortion –15V Figure 12. Unity Gain Follower +15V 10µF + 0.1µF 10pF VIN 4.99kΩ 2 8 1/2 OP275 4 1 4.99kΩ Since the OP275 is a very low distortion amplifier, careful attention should be given to source impedances seen by both inputs. As with many FET-type amplifiers, the p-channel JFETs in the OP275’s input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. In an inverting configuration, the inverting input is held at a virtual ground and, as such, does not vary with input voltage. Thus, since the gate-to-source voltage is constant, there is no distortion due to input capacitance modulation. In noninverting applications, however, the gate-to-source voltage is not constant. The resulting capacitance modulation can cause distortion above 1 kHz if the input impedance is > 2 kΩ and unbalanced. VOUT 3 2.49kΩ 2kΩ 0.1µF 10µF + Figure 15 shows some guidelines for maximizing the distortion performance of the OP275 in noninverting applications. The best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors (R F and RG) is less than 2 kΩ. Keeping the values of these resistors small has the added benefits of reducing the thermal noise RG RF –15V Figure 13. Unity Gain Inverter In inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capacitance (RS and CS) and the OP275’s input capacitance (CIN), as shown in Figure 14. With RS and RF in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor, CFB, in parallel and RFB eliminates this problem. By setting RS (CS + CIN) = RFBCFB, the effect of the feedback pole is completely removed. RS* VIN 0P275 VOUT * RS = RG//RF IF RG//RF > 2kΩ FOR MINIMUM DISTORTION Figure 15. Balanced Input Impedance to Minimize Distortion in Noninverting Amplifier Circuits REV. A –9– OP275 of the circuit and dc offset errors. If the parallel combination of R F and RG is larger than 2 kΩ, then an additional resistor, R S, should be used in series with the noninverting input. The value of RS is determined by the parallel combination of RF and RG to maintain the low distortion performance of the OP275. Driving Capacitive Loads importance. Like the transformer based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily set to noninverting, inverting, or differential operation. A 3-Pole, 40 kHz Low-Pass Filter The OP275 was designed to drive both resistive loads to 600 Ω and capacitive loads of over 1000 pF and maintain stability. While there is a degradation in bandwidth when driving capacitive loads, the designer need not worry about device stability. The graph in Figure 16 shows the 0 dB bandwidth of the OP275 with capacitive loads from 10 pF to 1000 pF. 10 9 8 BANDWIDTH – MHz 7 6 5 4 3 2 1 0 0 200 400 600 CLOAD – pF 800 1000 The closely matched and uniform ac characteristics of the OP275 make it ideal for use in GIC (Generalized Impedance Converter) and FDNR (Frequency-Dependent Negative Resistor) filter applications. The circuit in Figure 18 illustrates a linear-phase, 3-pole, 40 kHz low-pass filter using an OP275 as an inductance simulator (gyrator). The circuit uses one OP275 (A2 and A3) for the FDNR and one OP275 (A1 and A4) as an input buffer and bias current source for A3. Amplifier A4 is configured in a gain of 2 to set the pass band magnitude response to 0 dB. The benefits of this filter topology over classical approaches are that the op amp used in the FDNR is not in the signal path and that the filter’s performance is relatively insensitive to component variations. Also, the configuration is such that large signal levels can be handled without overloading any of the the filter’s internal nodes. As shown in Figure 19, the OP275’s symmetric slew rate and low distortion produce a clean, wellbehaved transient response. R1 95.3kΩ 2 VIN 3 A1 1 C1 2200pF Figure 16. Bandwidth vs. CLOAD High Speed, Low Noise Differential Line Driver R2 787Ω C2 2200pF R3 1.82kΩ C3 2200pF R4 1.87kΩ R6 4.12kΩ C4 2200pF 7 R7 100kΩ 5 6 A4 The circuit of Figure 17 is a unique line driver widely used in industrial applications. With ± 18 V supplies, the line driver can deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The high slew rate and wide bandwidth of the OP275 combine to yield a full power bandwidth of 130 kHz while the low noise front end produces a referred-to-input noise voltage spectral density of 10 nV/√Hz. R3 2k 2 3 A2 1 R9 50 VO1 R11 1k R4 2k R7 2k VO2 – VO1 = VIN P1 10k R5 2k R6 2k 6 A1 = 1/2 OP275 A2, A3 = 1/2 OP275 GAIN = R1 SET R2, R4, R5 = R1 AND R6, R7, R8 = R3 R3 7 VOUT 5 6 A3 2 1 A2 3 R9 1kΩ R8 1kΩ A1, A4 = 1/2 OP275 A2, A3 = 1/2 OP275 R5 1.82kΩ R1 2k VIN 3 2 A1 1 Figure 18. A 3-Pole, 40 kHz Low-Pass Filter 100 90 R2 2k 5 A3 7 R8 2k R10 50 R12 1k VO2 VOUT 10Vp-p 10kHz 10 0% Figure 17. High Speed, Low Noise Differential Line Driver SCALE: VERTICAL–2V/ DIV HORIZONTAL–10µs/ DIV The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount Figure 19. Low-Pass Filter Transient Response –10– REV. A OP275 OP275 SPICE Model * * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * * .SUBCKT OP275 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHz * R3 5 51 2.188 R4 6 51 2.188 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 364E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) 26 28 0.5E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.672 R6 8 4 1.672 D1 2 36 DZ D2 1 36 DZ EN 3 1 10 0 1 GN1 0 2 13 0 1E-3 GN2 0 1 16 0 1E-3 * EREF 98 0 28 0 1 EP 97 0 99 0 1 EM 51 0 50 0 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 32 Hz * R7 18 98 1.09E6 C3 18 98 4.55E-9 G1 98 18 5 6 4.57E-1 V2 97 19 1.35 V3 20 51 1.35 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz * R8 21 98 1E-3 R9 21 22 1.25E-3 C4 22 98 47.2E-12 G2 98 21 18 28 1E-3 * * POLE AT 100 MHz * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 21 28 1 * * POLE AT 100 MHz * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 23 28 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz * R12 25 26 1E6 C7 25 26 1.5915E-12 R13 26 98 1 E2 25 98 POLY(2) 1 98 2 98 0 2.50 2.50 * * POLE AT 100 MHz * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 24 28 1 * * OUTPUT STAGE * R15 28 99 100E3 R16 28 50 100E3 C9 28 50 1E-6 ISY 99 50 1.85E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 27 29 10E-3 G7 33 50 29 27 10E-3 G8 29 99 99 27 10E-3 G9 50 29 27 50 10E-3 V4 30 29 1.3 V5 29 31 3.8 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS REV. A –11– OP275 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.1968 (5.00) 0.1890 (4.80) 8 5 0.430 (10.92) 0.348 (8.84) 8 5 0.2440 (6.20) 0.2284 (5.80) 1 4 0.1574 (4.00) 0.1497 (3.80) 1 4 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) PIN 1 PIN 1 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) 0.0098 (0.25) BSC 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC –12– REV. A PRINTED IN U.S.A. C1652a–2–7/95 8-Lead Narrow-Body SOIC (S Suffix) 8-Lead Epoxy DIP (P Suffix)