OP492GS

a FEATURES Single-Supply Operation: 4.5 V to 33 V Input Common-Mode Includes Ground Output Swings to Ground High Slew Rate: 3 V/ s High Gain Bandwidth: 4 MHz Low Input Offset Voltage High Open-Loop Gain No Phase Inversion Low Cost APPLICATIONS Disk Drives Mobile Phones Servo Controls Modems and Fax Machines Pagers Power Supply Monitors and Controls Battery-Operated Instrumentation GENERAL DESCRIPTION 1 2 3 4 Dual/Quad Single-Supply Operational Amplifiers OP292/OP492 PIN CONNECTIONS 8-Lead Narrow-Body SOIC (S-Suffix) 8 8-Lead Epoxy DIP (P-Suffix) OP292 OUTA INA INA V 1 2 3 4 8 7 6 5 V OUTB INB INB OP292 7 6 5 14-Lead Narrow-Body SOIC (S-Suffix) 1 2 3 4 5 6 7 14 14-Lead Epoxy DIP (P-Suffix) OP-292 OUTA 1 INA 2 INA 3 V 4 14 OUTD 13 12 13 TOP VIEW 12 OP492 (NOT TO S CALE) 11 10 9 8 IND IND V INC INC OUTC OP492 11 10 9 8 The OP292/OP492 are low cost, general purpose dual and quad operational amplifiers designed for single-supply applications and are ideal for 5 olt systems. Fabricated on Analog Devices’ CBCMOS process, the OP292/ OP492 series has a PNP input stage that allows the input voltage range to include ground. A BiCMOS output stage enables the output to swing to ground while sinking current. The OP292/OP492 series is unity-gain stable and features an outstanding combination of speed and performance for singleor dual-supply operation. The OP292/OP492 provide high slew rate, high bandwidth, with open-loop gain exceeding 40,000 and offset voltage under 800 (OP292) and 1 mV (OP492). With these combinations of features and low supply current, the OP292/OP492 series is an excellent choice for battery-operated applications. The OP292/OP492 series performance is specified for single- or dual-supply voltage operation over the extended industrial temperature range (–40∞C to +125∞C). Package options for the OP292 and OP492 include plastic DIP, SO-8 (OP292) and SO-14. INB 5 INB 6 OUTB 7 R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 OP292/OP492–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = 5 V, VC S M = O V, VO = 2 V, TA = 25 C unless otherwise noted.) Min Typ Max Unit Parameter INPUT CHARACTERISTICS Offset Voltage OP292 Symbol Conditions VOS VOS IB IOS OP492 –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C VCM = 0 V to 4.0 V –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C RL = 10 k , VO = 0.1 V to 4 V –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +125∞C Note 1 –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C Input Bias Current Input Offset Current 0.1 0.3 0.5 0.1 0.3 0.5 450 0.75 3.0 7 100 0.4 0 75 70 65 25 10 5 95 93 90 200 100 50 2 1 6 400 1.5 2 Input Voltage Range Common-Mode Rejection Ratio 0.8 1.2 2.5 1 1.5 2.5 700 2.5 5.0 50 700 1.2 4.0 CMRR Large-Signal Voltage Gain AVO DVOS /DT DVOS /DT DIB /DT DIOS /DT Offset Voltage Drift Long-Term VOS Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing High 10 mV mV mV mV mV mV nA mA mA nA nA mA V dB dB dB V/mV V/mV V/mV mV/∞C mV/Month pA/∞C pA/∞C pA/∞C pA/∞C VOUT Low VOUT Short-Circuit Current Limit POWER SUPPLY Power Supply Rejection Ratio Supply Current Per Amp OP292, OP492 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density ISC PSRR ISY RL = 100 k to GND –40∞C £ TA £ +125∞C RL = 2 k to GND –40∞C £ TA £ +125∞C RL = 100 k to V+ –40∞C £ TA £ +125∞C RL = 2 k to V+ –40∞C £ TA £ +125∞C 4.0 3.8 3.7 5 75 70 4.3 4.1 3.9 8 12 280 300 8 95 90 0.8 20 20 450 550 V V V mV mV mV mV mA dB dB VS = 4.5 V to 30 V, VO = 2 V –40∞C £ TA £ +125∞C VO = 2 V 1.2 mA V/ms V/ms MHz Degrees dB mV p-p nV/÷Hz pA/÷Hz SR GBP m R L = 10 k –40∞C £ TA £ +125∞C fO = 1 kHz 0.1 Hz to 10 Hz f = 1 kHz 1 CS en p-p en in 3 2 4 75 100 25 15 0.7 NOTES 1 Long-term offset voltage drift is guaranteed by 1,000 hours life test performed on three independent wafer lots at 125 ∞C with LTPD of 1.3. Specifications subject to change without notice. –2– REV. B OP292/OP492 ELECTRICAL CHARACTERISTICS (@ V = 5 V, VC S M = O V, VO = 2 V, TA = 25∞C unless otherwise noted.) Min Typ Max Unit Parameter INPUT CHARACTERISTICS Offset Voltage OP292 Symbol Conditions VOS VOS IB IOS OP492 –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C Note 1 VCM = 11 V –40∞C £ TA £ +125∞C RL = 10 k , VO = 10 V –40∞C £ TA £ +85∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +125∞C –40∞C £ TA £ +125∞C RL = 2 k to GND –40∞C £ TA £ +125∞C RL = 100 k to GND –40∞C £ TA £ +125∞C Short Circuit to GND VS = 2.25 V to 15 V 40∞C £ TA £ +125∞C VO = 0 V Input Bias Current Input Offset Current 1.0 1.2 1.5 1.4 1.7 2 375 0.5 7 20 0.4 –11 78 75 25 10 5 100 95 120 75 60 4 3 12.2 11 14.3 14.0 10.5 86 83 1 Input Voltage Range Common-Mode Rejection Ratio Large-Signal Voltage Gain 2.0 2.5 3 2.5 2.8 3 700 1 50 100 1.2 11 CMRR AVO DVOS/DT DIB/DT VO Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing 10 mV mV mV mV mV mV nA mA nA nA mA V dB dB V/mV V/mV V/mV mV/∞C pA/∞C V V V mV mA dB dB 11 10 13.8 13.5 8 75 70 Short-Circuit Current Limit POWER SUPPLY Power Supply Rejection Ratio Supply Current Per Amp OP292, OP492 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density ISC PSRR ISY 1.4 mA V/ms V/ms MHz Degrees dB mV p-p nV/÷Hz pA/÷Hz GBP m SR RL =10 k –40∞C £ TA £ +125∞C fO = 1k Hz 0.1 Hz to 10 Hz f = 1k Hz 2.5 2 CS en p-p en in 4 3 4 75 100 25 15 0.7 NOTES 1 Input voltage range is guaranteed by CMRR tests. Specifications subject to change without notice. REV. B –3– OP292/OP492 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +14 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . V Output Short-Circuit Duration . . . . . . . . . . . . UNLIMITED Storage Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C Operating Temperature Range OP292/OP492 P, S . . . . . . . . . . . . . . . . –40∞C to +125∞C Junction Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . –65∞C to +125∞C Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300∞C Package Type 8-Pin Plastic DIP (P) 14-Pin Plastic DIP (P) 8-Pin SOIC (S) 14-Pin SOIC (S) JA 3 JC Unit C/W C/W C/W C/W 103 83 158 120 43 39 43 36 NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless other wise noted. 2 For supply voltages less than 36 V, the absolute maximum input voltage is equal to the supply voltage. 3 JA is specified for the worst-case conditions, i.e., JA is specified for device in socket for P-DIP package; JA is specified for device soldered in circuit board for SOIC package. ORDERING GUIDE Model OP292GP* OP292GS OP492GP* OP492GS Temperature Range –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C –40∞C to +125∞C Package Option N-8 RN-8 N-14 RN-14 *Not for new design, obsolete April 2002. –4– REV. B Typical Performance Characteristics– OP292/OP492 200 175 150 125 UNITS VS = 5V VCM = 0V TA = 25 C 720 OP AMPS 160 140 120 100 UNITS VS = 5V VCM = 0V TA = 25 C 600 OP AMPS 100 75 50 25 0 500 80 60 40 20 0 400 300 200 100 0 100 200 300 µV 400 500 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 mV 0.4 0.5 0.6 INPUT OFFSET VOLTAGE, V OS INPUT OFFSET VOLTAGE, V OS TPC 1. OP292 Input Offset Voltage Distribution @ 5 V TPC 4. OP492 Input Offset Voltage Distribution @ 5 V 320 280 240 200 UNITS 240 15V VCM = 0V TA = 25 C 720 OP AMPS VS = 200 VS = 15V VCM = 0V TA = 25 C 600 OP AMPS 160 UNITS 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 mV 1.8 2.0 160 120 120 80 80 40 0 INPUT OFFSET VOLTAGE, V OS 40 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 mV 1.8 2.0 INPUT OFFSET VOLTAGE, V OS TPC 2. OP292 Input Offset Voltage Distribution @ ± 15 V TPC 5. OP492 Input Offset Voltage Distribution @ ± 15 V 160 140 120 100 UNITS 160 VS = 5V VCM = 0V 40 C TA 600 OP AMPS 140 125 C 120 100 UNITS VS = 5V VCM = 0V 40 C TA 125 C 600 OP AMPS 80 60 40 20 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 TCVOS – µ V/ C 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TCVOS – µ V/ C TPC 3. OP292 Temperature Drift (TCVOS) Distribution @ 5 V TPC 6. OP492 Temperature Drift (TCVOS) Distribution @ 5 V REV. B –5– OP292/OP492 240 210 180 150 VS = 5V VCM = 0V 40 C TA 600 OP AMPS 125 C 200 175 150 125 UNITS VS = 15V VCM = 0V 40 C TA 600 OP AMPS 125 C UNITS 120 90 60 30 0 0 1 2 3 4 5 TCVOS µ V/ C 6 7 8 100 75 50 25 0 0 1 2 3 4 5 TCVOS µ V/ C 6 7 8 TPC 7. OP292 Temperature Drift (TCVOS) Distribution @ ±15 V TPC 10. OP492 Temperature Drift (TCVOS) Distribution @ ± 15 V 600 VS = 5V VO = 4V 900 800 700 RL = 10k V S = 5V VO = 4V 500 OPEN-LOOP GAIN – V/mV OPEN-LOOP GAIN – V/mV 400 600 500 400 300 RL = 2k 200 100 0 50 300 R L = 10k 200 100 RL = 2k 0 50 25 0 25 50 C 75 100 125 25 0 TEMPERATURE 25 50 TEMPERATURE 75 C 100 125 TPC 8. OP292 Open-Loop Gain vs. Temperature @ 5 V TPC 11. OP492 Open-Loop Gain vs. Temperature @ 5 V 250 VS = VO = 200 V/mV OPEN-LOOP GAIN – V/mV 400 15V 10V 350 300 250 200 150 100 50 VS = VO = 15V 10V OPEN-LOOP GAIN 150 RL = 10k 100 RL = 2k 50 RL = 10k RL = 2k 0 50 25 0 25 50 C 75 100 125 TEMPERATURE 0 50 25 0 25 50 75 TEMPERATURE – C 100 125 TPC 9. OP292 Open-Loop Gain vs. Temperature @ ± 15 V TPC 12. OP492 Open-Loop Gain vs. Temperature @ ± 15 V –6– REV. B OP292/OP492 1.4 mA mA SUPPLY CURRENT PER AMPLIFIER 1.4 1.2 VS = 15V 1.2 SUPPLY CURRENT PER AMPLIFIER 1.0 1.0 VS = 0.8 15V 0.8 VS = +5V 0.6 0.6 VS = 0.4 5V 0.4 0.2 50 25 0 25 50 TEMPERATURE 75 C 100 125 0.2 50 25 0 25 50 TEMPERATURE 75 C 100 125 TPC 13. OP292 Supply Current per Amplifier vs. Temperature TPC 16. OP492 Supply Current per Amplifier vs. Temperature 6 VS = VO = 5 15V 10V SR 6 VS = VO = 5 15V 10V SR V/µs V/µs 4 SR SR 4 SR 3 SR 2 SR SLEW RATE 3 2 SR 1 SLEW RATE 1 VS = 5V VO = 0.1V, 4V VS = 5V VO = 0.1V, 4V 50 25 0 25 50 TEMPERATURE 75 C 100 125 0 50 25 0 25 50 TEMPERATURE 75 C 100 125 0 TPC 14. OP292 Slew Rate vs. Temperature TPC 17. OP492 Slew Rate vs. Temperature 90 80 70 60 dB 90 TA = 25 C V = 5V V = 0V RL = 10k GAIN 80 70 60 TA = 25 C VS = 10k RL = 10k 50 40 dB 50 40 GAIN GAIN GAIN Degrees PHASE 20 10 0 10 1k 10k 100k FREQUENCY Hz 1M 90 45 20 PHASE 10 90 45 0 45 1k 10k 100k FREQUENCY Hz 1M 10M PHASE 0 45 10M 0 10 TPC 15. OP292/OP492 Open-Loop Gain and Phase vs. Frequency @ 5 V TPC 18. OP292/OP492 Open-Loop Gain/Phase vs. Frequency @ ± 15 V REV. B –7– PHASE Degrees 30 PHASE MARGIN = 83 135 30 PHASE MARGIN = 92 135 OP292/OP492 50 TA = 25 C V = 5V V = 0V 50 TA = 25 C VS = 15V 40 40 dB CLOSED-LOOP GAIN 20 CLOSED-LOOP GAIN 1k 10k 100k FREQUENCY – Hz 1M 10M 30 dB 30 20 10 10 0 0 10 10 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 19. OP292/OP492 Closed-Loop Gain/Phase vs. Frequency @ 5 V TPC 22. OP292/OP492 Closed-Loop Gain/Phase vs. Frequency @ ± 15 V 120 TA = 25 C V = 5V V = 0V 120 TA = 25 C VS = 15V dB dB COMMON-MODE REJECTION 1M 100 100 COMMON-MODE REJECTION 80 80 60 60 40 40 20 20 0 100 1k 10k FREQUENCY 100k Hz 0 100 1k 10k FREQUENCY 100k Hz 1M TPC 20. OP292/OP492 CMR vs. Frequency @ 5 V TPC 23. OP292/OP492 CMR vs. Frequency @ ± 15 V 120 TA = 25 C VS = 5V 120 TA = 25 C VS = 15V dB 80 POWER SUPPLY REJECTION – dB 100 100 POWER SUPPLY REJECTION 80 PSRR 60 PSRR 60 40 40 20 20 0 100 1k 10k FREQUENCY – Hz 100k 1M 0 100 1k 10k FREQUENCY – Hz 100k 1M TPC 21. OP292/OP492 PSR vs. Frequency @ 5 V TPC 24. OP292/OP492 PSR vs. Frequency @ ± 15 V –8– REV. B OP292/OP492 4.8 VS = 5V V 15.0 V VS = 15V RL = 100k OUTPUT SWING 14.0 13.0 12.0 11.0 RL = 10k RL = 2k 4.6 RL = 100k 4.4 RL = 10k OUTPUT VOLTAGE SWING OUTPUT SWING – V 4.2 10.0 14.0 14.5 15.0 250 RL = 2k RL = 10k 225 0 25 50 TEMPERATURE – C 75 RL = 100k 4.0 RL = 2k 3.8 50 25 0 25 50 75 TEMPERATURE – C 100 125 100 125 TPC 25. OP292/OP492 VOUT Swing vs. Temperature @ 5 V TPC 28. OP292/OP492 VOUT Swing vs. Temperature @ ± 15 V 10.0 VS = 5V VCM = 0V 600 VS = 15V VCM = 0V 5.0 500 nA 2.0 A INPUT BIAS CURRENT INPUT BIAS CURRENT 400 OP492 300 OP292 200 1.0 OP492 0.5 OP292 0.2 0.1 50 25 0 25 50 TEMPERATURE 75 C 100 125 100 0 50 25 0 25 50 C 75 100 125 TEMPERATURE TPC 26. OP292/OP492 Input Bias Current vs. Temperature @ 5 V TPC 29. OP292/OP492 Input Bias Current vs. Temperature @ ± 15 V 140 120 100 80 60 40 20 0 0 10 100 1k 10k 100k FREQUENCY – Hz VS = 5V, 15V RL = 2k VO = 3Vp–p 0.50 0.48 0.46 0.44 0.42 0.40 0.38 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 0.20 0.18 01 2 3 4 5 RAIL +15V IB – nA A V IN –15V RAIL 6 78 9 VIN – V 10 11 12 13 14 15 TPC 27. OP292/OP492 Channel Separation TPC 30. OP292/OP492 IB Current vs. Common-Mode Voltage REV. B –9– OP292/OP492 CH A: 800dV FS MKR: 16.9 V/ Hz 100dV/DIV Power Supply Considerations The OP292/OP492 are designed to operate equally well at single 5 V or 15 V supplies. The lowest supply voltage recommended is 4.5 V. It is a good design practice to bypass the supply pins with a 0.1 mF ceramic capacitor. It helps improve filtering of high frequency noise. For dual supply operation, the negative supply (V–) must be applied at the same time, or before V . If V is applied before V–, or in the case of a loss of V– supply, while either input is connected to ground or other low impedance source, excessive input current may result. Potentially damaging levels of input current can destroy the amplifier. If this condition can exist, simply add a l k or larger resistor in series with the input to eliminate the problem. TYPICAL APPLICATIONS Direct Access Arrangement for Telephone Line Interface 0Hz MKR: 1000 Hz 25 kHz BW: 150 Hz TPC 31. Voltage Noise Density APPLICATION INFORMATION Phase Reversal The OP492 has built-in protection against phase reversal when the input voltage goes to either supply rail. In fact, it is safe for the input to exceed either supply rail by up to 0.6 V with no risk of phase reversal. However, the input should not go beyond the positive supply rail by more than 0.9 V, otherwise the output will reverse phase. If this condition can occur, the problem can be fixed by adding a 5 k current limiting resistor in series with the input pin. With this addition, the input can go to more than 5 V beyond the positive rail without phase reversal. An input voltage that is as much as 5 V below the negative rail will not result in phase reversal. Figure 3 shows a 5 V- only transmit/receive telephone line interface for a modem circuit. It allows full duplex transmission of modem signals on a transformer-coupled 600 V line in a differential manner. The transmit section gain can be set for the specific modem device output. Similarly the receive amplifier gain can be appropriately selected based on the modem device input requirements. The circuit operates on a single 5 V supply. The standard value resistors allow the use of a SIP-packaged resistor array; coupled with a quad op amp in a single package, this offers a compact, low part-count solution. TX GAIN ADJUST 50k 1V 100 To Telephone Line 20k 1:1 300k 300k 1/4 OP492 20k 20k 0.1 F TRANSMIT TXA 5V OV 11.8V p-p OP492 2K 90 T1 10 0% 6.2V 5µS 6.2V 5V dc 5k 1/4 OP492 MODEM Figure 1. Output Phase Reverse If Input Exceeds the Positive Supply (V+) by More Than 0.9 V 100pF 5k 20k 5V 0.1 F 20k 20k 1/4 OP492 10 F 1V 5V 100 RX GAIN ADJUST 20k 50k 0.1 F RECEIVE RXA OV 10V p-p OP492 90 20k 2k 10 0% 5µS Figure 3. A Universal Direct Access Arrangement for Telephone Line Interface A Single-Supply Instrumentation Amplifier Figure 2. No Negative Rail Phase Reversal, Even with Input Signal at 5 V Below Ground A low-cost, single-supply instrumentation amplifier can be built as shown in Figure 4. The circuit utilizes two op amps to form a high-input impedance differential amplifier. Gain can be set by selecting resistor RG which can be calculated using the transfer function equation. Normally, VREFERENCE is set to 0 V. Then the output voltage is a function of the gain times the differential input –10– REV. B OP292/OP492 voltage. However, the output can be offset by setting VREFERENCE from 0 V to 4 V, as long as the input common-mode voltage of the amplifier is not exceeded. A 50 Hz/60 Hz Single-Supply Notch Filter 5V 5 VIN 1/2 OP292 8 1/2 OP292 7 VOUT 1 4 Figure 6 shows a notch filter that achieves nearly 30 dB of 60 Hz rejection while powered by only a single 12 V supply. The circuit also works well on 5 V systems. The filter utilizes a twin-T configuration whose frequency selectivity depends heavily on the relative matching of the capacitors and resistors in the twin-T section. Mylar is a good choice for the twin-T’s capacitors, and the relative matching of the capacitors and resistors determines the filter’s passband symmetry. Using 1% resistors and 5% capacitors produces satisfactory results. The amount of rejection and the Q of the filter is solely determined by one resistor, and is shown in the table. The bottom amplifier is used to split the supply to bias the amplifier to midlevel. The circuit can be modified to reject 50 Hz by simply changing the resistors in the twin-T section (Rl through R4) from 2.67 k to 3.16 k , and changing R5 to 1⁄2 of 3.16 k . For best results, the common value resistors can be from a resistor array for optimum matching characteristics. VREF 20k 5k 5k 20k 40k RG VOUT = 5 RG + VREF Figure 4. A Single-Supply Instrumentation Amplifier In this configuration, while the output can swing to near zero volts, one needs to be careful because the input’s common-mode voltage range cannot operate to zero volts. This is because of the limitation of the circuit configuration where the first amplifier must be able to swing below ground in order to attain a 0 V common-mode voltage, which it cannot do. Depending on the gain of the instrumentation amplifier, the input common-mode extends to within about 0.3 V of zero. One can easily calculate the worst-case common-mode limit for a given gain. DAC Output Amplifier R2 2.67k R1 2.67k 1/4 OP492 R3 2.67k C3 2F (1 F 2) C1 1F C2 1F 12V 1/4 OP492 VIN VOUT The OP292/OP492 are ideal for buffering the output of singlesupply D/A converters. Figure 5 shows a typical amplifier used to buffer the output of a CMOS DAC that is connected for singlesupply operation. To do that, the normally current output 12-bit CMOS DAC (R-2R ladder type) is connected backward to produce a voltage output. This operating configuration necessitates a low voltage reference. In this case, a 1.235 V low-power reference is used. The relatively high output impedance (10 k ) is buffered by the OP292 and at the same time gained up to a much more usable level. The potentiometer provides an accurate gain trim for a 4.095 V full-scale, allowing 1mV increment per LSB of control resolution. The DAC8043 device comes in an 8-pin DIP package providing a cost-effective, compact solution to a 12-bit analog channel. R6 100k R4 2.67k R5 1.335k (2.67k 2) R7 1k RQ 8k 12V R8 100k R9 100k C4 1F 1/4 OP492 6V NOTE FOR 50Hz APPLICATION CHANGE R12 R4 TO 3.16k 2) AND R5 TO 1.58k (3.16k FILTER Q RQ (k ) REJECTION (dB) VOLTAGE GAIN 0.75 1.00 1.25 2.50 5.00 10.00 1.0 2.0 3.0 8.0 18 38 40 35 30 25 20 15 1.33 1.50 1.60 1.80 1.90 1.95 5V 1/2 OP292 Figure 6. A Single-Supply 50 Hz/60 Hz Notch Filter VOUT 1mV/LSB 0V 4.095V FS 5V 5V 7.5k 1.235V Ad589 DAC8043 VDD 8 1 VREF DD 5V 2 5k 5V 8 1 4 1.1k NC 2 VFB 3 t0 4 VND Clk CLK 7 6 0.022 F 1/2 OP292 5 14.3k 2200pF 7 VOUT 20k 8.45k Sri SRI 6 LD 5 VIN 0.01 F 1/2 3 OP292 16.2k 500k 100 F 1.78k 5k 3300pF LD SRI CLK DIGITAL CONTROL Figure 7. A 4-Pole Bessel Low-Pass Filter Using Sallen-Key Topology A 4-Pole Bessel Low-Pass Filter Figure 5. A 12-Bit Single-Supply DAC with Serial Bus Control The linear phase filter in Figure 7 is designed to roll off at a voiceband cutoff frequency of 3.6 kHz. The 4 poles are formed by two cascading stages of two-pole Sallen-Key filters. –11– REV. B OP292/OP492 A Low-Cost, Linearized Thermistor Amplifier An inexpensive thermometer amplifier circuit can be implemented using low-cost thermistors. One such implementation is shown in Figure 8. The circuit measures temperature over the range of 0∞C to 70∞C to an accuracy of ± 0.3∞C as the linearization circuit works well within a narrow temperature range. However, it can measure higher temperature but at a slightly reduced accuracy. To achieve the aforementioned accuracy, the thermistor’s nonlinearity must be corrected. This is done by connecting the thermistor in parallel with the 10 k in the feedback loop of the first stage amplifier. A constant operating current of 281 A is supplied by the resistor R1 with the 5 V reference from the REF-195 such that the thermistor’s self-heating error is kept below 0.1∞C. In many cases, the thermistor is placed some distance from the signal conditioning circuit. Under this condition, a 0.1 mF capacitor placed across R2 will help to suppress noise pickup. This linearization network creates an offset voltage that is corrected by summing a compensating current with potentiometer P1. The temperature dependent signal is amplified by the second stage, producing a transfer coefficient of –10 mV/∞C at the output. To calibrate, a precision decade box can be used in place of the thermistor. For 0∞C trim, the decade box is set to 32.650 k , and P1 is adjusted until the circuit’s output reads 0 V. To trim the circuit at the full-scale temperature of 70∞C, the decade box is then set to 1.752 k and P2 is adjusted until the circuit reads –0.70 V. feedback diodes begin to conduct, shunting the feedback current, and thus reducing the gain. Although distorting the waveform, the diodes effectively maintain a relatively constant amplitude even with large signals that otherwise would saturate the amplifier. In addition, this design is considerably more stable than the feedback type AGC. The overall circuit has a gain range from –2 to –400, where the inversion comes from the band-pass filter stage. Operating with a Q of 5, the filter restores a clean, undistorted signal to the output. The circuit also works well with 5 V supply systems. 12V 600k RECEIVER 1M 1/4 OP492 68pF 12V 12V 7.5V 1/4 OP492 14k 68pF 56.2k 1/4 OP492 VOUT 12V 600k PANASONIC EFR-RTB40K2 390k 10k 0.01 F 100k 10k 0.01 F 0.01 F 6.04k 1F 7.5V 1M RT 15V R1* 17.8k 1.0 F REF195 1F 5V R4 41.2k R5 806k NOTES + = ALPHA THERMISTOR 13A1002-C3 * = 0.1% IMPERIAL ASTRONICS M015 ALL RESISTORS ARE 1%, 25 ppm/ C EXCEPT R5 = 1%, 100 ppm/ C 1/2 OP292 Figure 9. A 40 kHz Ultrasonic Clamping/Limiting Receiver Amplifier Precision Single-Supply Voltage Comparator 10k NTC R1* 17.8k 1/2 OP292 R3 10k R6 7.87k P2 200 70 C TRIM The OP292/OP492 have excellent overload recovery characteristics, making them suitable for precision comparator applications. Figure 10 shows the saturation recovery characteristics of the OP492. The amplifier exhibits very little propagation delay. The amplifier compares a signal precisely to less than 0.5 mV offset error. VOUT 10mV/ C P1 10k 0 C TRIM 15V 1k 3Vp-p OP492 100 90 1V 2k 15V Figure 8. A Low Cost Linearized Thermistor Amplifier A Single-Supply Ultrasonic Clamping/Limiting Receiver Amplifier 2.21k 20k 10 0% 5V 5µs Figure 9 shows an ultrasonic receiver amplifier using the nonlinear impedance of low-cost diodes to effectively control the gain for wide dynamic range. This circuit amplifies a 40 kHz ultrasonic signal through a pair of low-cost clamping amplifiers before feeding a band-pass filter to extract a clean 40 kHz signal for processing. The signal is ac-coupled into the false-ground bias node by virtue of the capacitive piezoelectric sensing element. Rather than using an amplifier to generate a supply splitting bias, the false ground voltage is generated by a low-cost resistive voltage divider. Each amplifier stage provides ac gain while passing on the dc selfbias. As long as the output signal at each stage is less than a diode’s forward voltage, each amplifier has unrestricted gain to amplify low level signals. However, as the signal strength increases, the Figure 10. The OP492 Has Fast Overload Recovery for Comparator Applications Programmable Precision Window Comparator The OP292/OP492 can be used for precise level detection such as in test equipment where a signal is measured within a range. Figure 11 shows such an implementation. The threshold voltage level is set by a pair of 12-bit DIA converters. The DACs have serial interface thus minimizing interconnection requirements. The DAC85 12 has a control resolution of 1 mV/bit. Thus for 5 V supply operation, maximum DAC output is 4.095 V. However, the OP292 will accept a maximum input of 4.0 V. –12– REV. B OP292/OP492 5V DAC8512 1 REF ADDRESS CLK SDI DECODE 2 3 4 CONTROL DAC 7 6 5 2 8 3 5V 8 1/2 OP292 1 HIGH 4 LD CLR 5V DAC8512 1 REF 2 3 4 ANALOG INPUT CONTROL DAC 7 6 5 5 8 6 1/2 OP292 7 LOW Figure 11. Programmable Window Comparator with 12-Bit Threshold Level Control REV. B –13– OP292/OP492 * OP292 SPICE Macro-model REV. B, 6/93 * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and provisions * in the License Statement. * * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * .SUBCKT OP292 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40 MHz * Il 99 4 5OE-6 IOS 2 l 10E-9 EOS 2 3 POLY(l) (21,30) 1.5E-3 75 CIN 1 2 3E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 966 R6 4 8 966 C1 5 6 .995E12 * * GAIN STAGE * EREF 98 0 (30,0) 1 G1 98 9 (5,6) 5OOE-6 R7 9 98 210.819E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6 MHz/12 MHz * E1 12 98 (9,30) 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15 MHz * E2 14 98 (13,30) lE6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON-MODE STAGE WITH ZERO AT 40 kHz * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 1 C5 20 21 3.979E-12 * –14– REV. B OP292/OP492 * POLE AT 100 MHz * G2 98 16 R12 16 98 C6 16 98 * * OUTPUT STAGE * RS1 99 30 RS2 30 50 ISY 99 50 G3 31 50 R16 31 50 DCL 50 31 I2 99 32 RCL 33 50 M1 32 31 M2 34 31 CC 31 32 Q3 99 32 Q4 33 32 Q5 31 33 (15,30) 1 1 1.592E-9 1E6 1E6 .44E-3 POLY(1) (16,30) -1.635E-6 4E-6 1E6 DZ 250E-6 56 50 50 MN L=9E-6 W=1000E-6 AD=15E-AS=15E-9 50 50 MN L=9E-6 W=1OOOE-6 AD=15E-9 AS=15E-9 14E-12 34 QNA 34 QPA 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM= 132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE= 1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR= 15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=l.lE-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=l.OE-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL QP PNP(BF=61.5) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS OP292 REV. B –15– OP292/OP492 * OP492 SPICE Macro-model REV. B, 6/93 * ARG / PMI * * Copyright 1993 by Analog Devices * * Refer to “README.DOC” file for License Statement. Use of * this model indicates your acceptance of the terms and pro* visions in the License Statement. * * Node assignments * noninverting input * inverting input * positive supply * negative supply * output .SUBCKT OP492 2 1 99 50 34 * * INPUT STAGE AND POLE AT 40 MHz I1 99 4 50E-6 IOS 2 1 10E-9 EOS 2 3 POLY(1) (21,30) 1.5E-3 75 CIN 1 2 3E-12 Q1 5 1 7 QP Q2 6 3 8 QP R3 5 50 2E3 R4 6 50 2E3 R5 4 7 966 R6 4 8 966 C1 5 6 .995E-12 * * GAIN STAGE * * EREF 98 0 (30,0) 1 G1 98 9 (5,6) 500E-6 R7 9 98 210.819E3 D1 9 10 DX D2 11 9 DX V1 99 10 .6 V2 11 50 .6 * * ZERO/POLE AT 6 MHz/12 MHz * E1 12 98 (9,30) 2 R8 12 13 1 R9 13 98 1 C3 12 13 26.526E-9 * * ZERO AT 15 MHz * E2 14 98 (13,30) 1E6 R10 14 15 1E6 R11 15 98 1 C4 14 15 10.610E-15 * * COMMON-MODE STAGE WITH ZERO AT 40 kHz * ECM 20 98 POLY(2) (1,30) (2,30) 0 0.5 0.5 R20 20 21 1E6 R21 21 98 1 C5 20 21 3.979E-12 –16– REV. B OP292/OP492 * POLE AT 100 MHz * G2 98 16 R12 16 98 C6 16 98 * * OUTPUT STAGE * RS1 99 30 RS2 30 50 ISY 99 50 G3 31 50 R16 31 50 DCL 50 31 I2 99 32 RCL 33 50 M1 32 31 M2 34 31 CC 31 32 Q3 99 32 Q4 33 32 Q5 31 33 (15,30) 1 1 1.592E-9 1 E6 1E6 .44E-3 POLY(1) (16,30) –1.635E-6 4E-6 1E6 DZ 250E-6 56 50 50 MN L=9E-6 W=1OOOE-6 AD=15E-9 AS=15E-9 50 50 MN L=9E-6 W=1OOOE-6 AD=15E-9 AS=15E-9 14E-12 34 QNA 34 QPA 50 QNA .MODEL QNA NPN(IS=1.19E-16 BF=253 NF=0.99 VAF=193 IKF=2.76E-3 + ISE=2.57E-13 NE=5 BR=0.4 NR=0.988 VAR=15 IKR=1.465E-4 + ISC=6.9E-16 NC=0.99 RB=2.0E3 IRB=7.73E-6 RBM=132.8 RE=4 RC=209 + CJE=2.1E-13 VJE=0.573 MJE=0.364 FC=0.5 CJC=1.64E-13 VJC=0.534 MJC=0.5 + CJS=1.37E-12 VJS=0.59 MJS=0.5 TF=0.43E-9 PTF=30) .MODEL QPA PNP(IS=5.21E-17 BF=131 NF=0.99 VAF=62 IKF=8.35E-4 + ISE=1.09E-14 NE=2.61 BR=0.5 NR=0.984 VAR=15 IKR=3.96E-5 + ISC=7.58E-16 NC=0.985 RB=1.52E3 IRB=1.67E-5 RBM=368.5 RE=6.31 RC=354.4 + CJE=l.lE-13 VJE=0.745 MJE=0.33 FC=0.5 CJC=2.37E-13 VJC=0.762 MJC=0.4 + CJS=7.11E-13 VJS=0.45 MJS=0.412 TF=1.OE-9 PTF=30) .MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 + TOX=8.5E-8 LD=1.48E-6 WD=1E-6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5 + XJ=1.75E-6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E-4 PB=0.837 + MJ=0.407 CJSW=0.5E-9 MJSW=0.33) .MODEL QP PNP(BF=61.5) .MODEL DX D .MODEL DZ D(BV=3.6) .ENDS OP492 REV. B –17– OP292/OP492 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 5 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 1 4 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) MIN SEATING PLANE 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075) 0.50 (0.0196) 0.25 (0.0099) 45 0.180 (4.57) MAX 0.100 (2.54) BSC 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.51 (0.0201) 0.33 (0.0130) 1.27 (0.0500) 0.41 (0.0160) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) 14-Lead Plastic Dual-in-Line Package [PDIP] (N-14) Dimensions shown in inches and (millimeters) 0.685 (17.40) 0.665 (16.89) 0.645 (16.38) 14 1 8 7 14-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-14) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 14 1 8 7 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 6.20 (0.2441) 5.80 (0.2283) 0.100 (2.54) BSC 0.015 (0.38) MIN 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) SEATING PLANE 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 45 0.022 (0.56) 0.060 (1.52) 0.018 (0.46) 0.050 (1.27) 0.014 (0.36) 0.045 (1.14) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.51 (0.0201) 0.33 (0.0130) SEATING PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.19 (0.0075) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095-AB CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 10/02 - Change from Rev. A to REV. B Page Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1/02 - Change from Rev. 0 to REV. A Deleted Wafer Test Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 –18– REV. B – 19– – 20– C00310-0-10/02 (B) PRINTED IN U.S.A.