OP497AY

a FEATURES Low Offset Voltage: 50 V max Low Offset Voltage Drift: 0.5 V/ C max Very Low Bias Current 25 C: 100 pA max –55 C to +125 C: 450 pA max Very High Open-Loop Gain: 2000 V/mV min Low Supply Current (per Amplifier): 625 A max Operates from 2 V to 20 V Supplies High Common-Mode Rejection: 120 dB min APPLICATIONS Strain Gage and Bridge Amplifiers High Stability Thermocouple Amplifiers Instrumentation Amplifiers Photo-Current Monitors High Gain Linearity Amplifiers Long-Term Integrators/Filters Sample-and-Hold Amplifiers Peak Detectors Logarithmic Amplifiers Battery-Powered Systems GENERAL DESCRIPTION Precision Picoampere Input Current Quad Operational Amplifier OP497 PIN CONNECTIONS 16-Lead Wide Body SOIC (S-Suffix) OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7 NC 8 NC = NO CONNECT – + + – – + + – 16 OUT D 15 –IN D 14 +IN D OP497 13 V– 12 +IN C 11 –IN C 10 OUT C 9 NC 14-Lead Plastic Dip (P-Suffix) 14-Lead Ceramic Dip (Y-Suffix) OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7 – + + – – + + – 14 OUT D 13 –IN D 12 +IN D The OP497 is a quad op amp with precision performance in the space-saving, industry standard 16-lead SOlC package. Its combination of exceptional precision with low power and extremely low input bias current makes the quad OP497 useful in a wide variety of applications. Precision performance of the OP497 includes very low offset, under 50 µV, and low drift, below 0.5 µV/°C. Open-loop gain exceeds 2000 V/mV ensuring high linearity in every application. Errors due to common-mode signals are eliminated by the OP497’s common-mode rejection of over 120 dB. The OP497’s power supply rejection of over 120 dB minimizes offset voltage changes experienced in battery-powered systems. Supply current of the OP497 is under 625 µA per amplifier, and it can operate with supply voltages as low as ± 2 V. The OP497 utilizes a superbeta input stage with bias current cancellation to maintain picoamp bias currents at all temperatures. This is in contrast to FET input op amps whose bias currents start in the picoamp range at 25°C, but double for every 10°C rise in temperature, to reach the nanoamp range above 85°C. Input bias current of the OP497 is under 100 pA at 25°C and is under 450 pA over the military temperature range. Combining precision, low power, and low bias current, the OP497 is ideal for a number of applications, including instrumentation amplifiers, log amplifiers, photo-diode preamplifiers, and long-term integrators. For a single device, see the OP97; for a dual device, see the OP297. R EV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. OP497 11 V– 10 +IN C 9 –IN C 8 OUT C 1000 INPUT CURRENT – PA VS = 15V VCM = 0V 100 –IB +IB IOS 10 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE – C Input Bias, Offset Current vs. Temperature One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 OP497–SPECIFICATIONS (@ V = 15 V, T = 25 C, unless otherwise noted.) S A Parameter Symbol Condition A F Min Typ Max Min Typ Max 20 40 0.2 0.1 30 80 50 100 0.5 40 70 80 0.4 75 150 150 1.0 C/G Min Typ Max 80 150 120 250 140 300 0.6 1.5 Unit µV INPUT CHARACTERISTICS Offset Voltage Vos –40°C ≤ +85°C –55°C ≤ +125°C TMIN – TMAX Average Input Offset Voltage Drift Long-Term Input Offset Voltage Stability Input Bias Current TCVOS µV/°C µV/Mo pA IB VCM = 0 V –40° ≤ TA ≤ +85°C –55° ≤ TA ≤ +125°C –40° ≤ TA ≤ +85°C –55° ≤ TA ≤ +125°C VCM = OV –40° ≤ TA ≤ +85°C –55° ≤ TA ≤ +125°C + 13 +13 120 114 100 450 0.1 40 150 60 200 110 600 0.3 0.7 30 50 60 0.3 tl4 +13.5 135 120 0.1 60 200 80 300 130 600 0.3 0.7 50 80 90 0.4 +14 +13.5 135 120 Average Input Bias Current Drift Input Offset Current TCIB Ios 0.5 15 35 0.2 +14 +13.5 140 130 100 400 150 200 600 200 300 600 pA/°C pA Average Input Offset Current Drift Input Voltage Range1 TCIOS IVR TMIN – TMAX VCM = ± 13 V TMIN – TMAX VO = ± 10 V, RL = 2 kΩ –40° ≤ TA ≤ +85°C –55° ≤ TA ≤ +125°C Common-Mode Rejection CMR Large Signal Voltage Gain AVO +13 +13 114 108 +13 +13 114 108 pA/°C V dB 2000 6000 1200 4000 30 500 3 1500 4000 800 2000 1000 3000 30 500 3 ± 13 ± 13.7 ± 13 ± 14 ± 13 ± 13.5 ± 25 114 135 108 120 525 580 ±2 ± 2.5 0.05 0.15 500 150 0.3 17 15 20 1200 4000 800 2000 800 3000 30 500 3 ± 13 ± 13.7V ± 13 ± 14 ± 13 ± 13.5 ± 25 114 135 108 120 525 625 580 750 ±2 ± 20 ± 2.5 ± 20 0.05 0.15 500 150 0.3 17 15 20 V/mV Input Resistance Differential Mode Input Resistance Common Mode Input Capacitance RIN RINCM CIN RL = 2 kΩ RL = 10 kΩ TMIN – TMAX RL = 10 kΩ MΩ GΩ pF OUTPUT CHARACTERISTICS Output Voltage Swing VO ± 13 ± 13.7 ± 13 ± 14 ± 13 ± 13.5 ± 25 120 140 114 130 525 580 ±2 ± 2.5 0.05 0.15 500 Short Circuit POWER SUPPLY Power Supply Rejection Ratio Supply Current (per Amplifier) Supply Voltage Range ISC PSRR Vs = ± 2 V to ± 20 V Vs = ± 2.5 V to ± 20 V TMIN – TMAX No Load TMIN – TMAX Operating Range TMIN – TMAX mA dB µA V ISY VS 625 750 ± 20 ± 20 625 750 ± 20 ± 20 DYNAMIC PERFORMANCE Slew Rate SR Gain Bandwidth Product GBW Channel Separation CS NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density V/µS kHz dB µV/p-p nV/√Hz nV/√Hz fA/√Hz VO = 20 Vp-p, fo = 10 Hz 150 0.3 17 15 20 en p-p 0.1 Hz to 10 Hz en = 10 Hz en = 1 kHz in = 10 Hz NOTE 1 Guaranteed by CMR Test. Specifications subject to change without notice. –2– REV. D OP497 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP497A, C (Y) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C OP497F, G (Y) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C OP497F, G (P, S) . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C Package Type 14-Pin Cerdip (Y) 14-Pin Plastic DIP (P) 16-Pin SOIC (S) JA 3 JC Model OP497AY* OP497CY* OP497FP OP497FS OP497GP OP497GS Temperature Range –55°C to +125°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 14-Lead Cerdip 14-Lead Cerdip 14-Lead Plastic DIP 16-Lead SOIC 14-Lead Plastic DIP 16-Lead SOIC Package Option Q-14 Q-14 N-14 R-16 N-14 R-16 *Not for new design; obsolete April 2002. For a military processed devices, please refer to the Standard Microcircuit Drawing (SMD) available at www.dscc.dla.mil/ programs.milspec./default.asp. SMD Part Number 5962–9452101M2A* 5962–9452101MCA ADI Part Number OP497BRC OP497BY Unit °C/W °C/W °C/W 94 76 92 10 33 23 *Not for new designs; obsolete April 2002. NOTES 1 Absolute Maximum Ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages less than ± 20 V, the absolute maximum input voltage is equal to the supply voltage. 3 HIA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for cerdip, P-DIP packages; JA is specified for device soldered to printed circuit board for SOIC package. DICE CHARACTERISTICS – 1/4 OP497 + 2k V1 20V p–p @ 10Hz 50k 50 – 1/4 OP497 + V1 (V2 /10000 ) V2 CHANNEL SEPARATION = 20 log Channel Separation Test Circuit CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP497 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. D –3– OP497–Typical Performance Characteristics (25 C, Vs = 15 V, unless otherwise noted.) 50 TA = 25 C VS = 15V VCM = 0V PERCENTAGE OF UNITS 50 TA = 25 C VS = 15V VCM = 0V PERCENTAGE OF UNITS 60 TA = 25 C VS = 15V VCM = 0V PERCENTAGE OF UNITS 40 40 50 40 30 30 30 20 20 20 10 10 10 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 V INPUT OFFSET VOLTAGE – 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 INPUT BIAS CURRENT – pA 0 0 10 20 30 40 50 60 INPUT OFFSET CURRENT – pA TPC 1. Typical Distribution of Input Offset Voltage TPC 2. Typical Distribution of Input Bias Current TPC 3. Typical Distribution of Input Offset Current 50 VS = 15V VCM = 0V PERCENTAGE OF UNITS 40 INPUT CURRENT – pA 1000 VS = 15V VCM = 0V 70 60 INPUT BIAS CURRENT – pA 50 40 30 20 10 TA = 25 C VS = 15V –IB 30 100 +IB 20 –IB +IB IOS 10 0 0 0.1 0.2 0.3 0.4 0.5 TCVOS – V/ C 0.6 0.7 0.8 10 –75 –50 –25 0 25 50 75 100 125 0 –15 –10 –5 0 5 10 15 TEMPERATURE – C COMMON-MODE VOLTAGE – Volts TPC 4. Typical Distribution of TCVOS TPC 5. Input Bias, Offset Current vs. Temperature TPC 6. Input Bias Current vs. Common-Mode Voltage 3 DEVIATION FROM FINAL VALUE – TA = 25 C VS = 15V VCM = 0V 2 V 10000 BALANCED OR UNBALANCED VS = 15V VCM = 0V V/ C 100 BALANCED OR UNBALANCED VS = 15V VCM = 0V EFFECTIVE OFFSET VOLTAGE – V EFFECTIVE OFFSET VOLTAGE – 1000 10 1 100 –55 C TA 125 C T A = +25 C 10 10 1 0 0 1 5 2 3 4 TIME AFTER POWER APPLIED – Minutes 100 1k 10k 100k 1M 10M 0.1 100 1k SOURCE RESISTANCE – 10k 100k 1M 10M SOURCE RESISTANCE – 100M TPC 7. Input Offset Voltage Warm-Up Drift TPC 8. Effective Offset Voltage vs. Source Resistance TPC 9. Effective TCVOS vs. Source Resistance –4– REV. D OP497 1000 10 VOLTAGE NOISE DENSITY – nV/ Hz CURRENT NOISE DENSITY – fA / Hz V/ Hz TA = 25 C VS = 2V TO 20V TA = 25 C VS = 2V TO 20V 5mV 1s NOISE VOLTAGE – 100mV/DIV 100 90 CURRENT NOISE VOLTAGE NOISE 10 TOTAL NOISE DENSITY – 100 1 10Hz 1kHz 0.1 10 0% VS = 15V TA = 25 C 1 1 10 100 FREQUENCY – Hz 1000 0.01 102 103 104 105 106 107 0 2 SOURCE RESISTANCE – 4 6 TIME – Secs 8 10 TPC 10. Voltage Noise Density vs. Frequency TPC 11. Total Noise Density vs. Source Resistance TPC 12. 0.1 Hz to 10 Hz Noise Voltage DIFFERENTIAL INPUT VOLTAGE – 10 V/ DIV 100 80 GAIN OPEN-LOOP GAIN – dB OPEN - LOOP GAIN – V/ MV PHASE SHIFT – DEG 60 40 20 0 –20 –40 100 PHASE VS = 15V CL = 30pF RL = 1M TA = 25 C 10000 TA = –55 C TA = +25C RL = 2k VS = 15V VCN = 10V TA= +125 C TA = +125 C 1000 90 135 180 225 TA= +25 C TA= –55 C VS = VO = 100 1 15V 10V 10 LOAD RESISTANCE – k 20 1k 10k 100k 1M FREQUENCY – Hz 10M –15 –10 –5 0 5 10 OUTPUT VOLTAGE – V 15 TPC 13. Open-Loop Gain, Phase vs. Frequency TPC 14. Open-Loop Gain vs. Load Resistance TPC 15. Open-Loop Gain Linearity 160 160 POWER SUPPLY REJECTION – dB 35 COMMON - MODE REJECTION – dB 140 120 100 80 60 40 20 0 1 10 100 1k 10k FREQUENCY – Hz VS = 15V TA= 25 C 140 120 100 80 60 40 20 0 +PSR –PSR VS = 15V TA = 25 C OUTPUT SWING – Vp-p 30 25 20 15 10 5 0 100 VS= 15V TA= 25 C AVCL= +1 1%THD RL = 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY – Hz 1k 10k FREQUENCY – Hz 100k TPC 16. Common-Mode Rejection vs. Frequency TPC 17. Power Supply Rejection vs. Frequency TPC 18. Maximum Output Swing vs. Frequency REV. D –5– OP497 INPUT COMMON-MODE VOLTAGE – Volts (REFERRED TO SUPPLY VOLTAGES) +VS TA = 25 C –0.5 OUTPUT SWING – Vp-p 35 OUTPUT VOLTAGE SWING – V (REFERRED TO SUPPLY VOLTAGES) +VS –0.5 –1.0 –1.5 –1.0 –1.5 VS = 15V TA = 25 C 30 AVCL= +1 1%THD 25 fO = 1kHz 20 15 10 5 0 10 TA = 25 C RL = 10k 1.5 1.0 0.5 –VS 1.5 1.0 0.5 –VS 0 0 5 10 15 SUPPLY VOLTAGE – V 20 100 1k LOAD RESISTANCE – 10k 5 10 15 20 SUPPLY VOLTAGE – V TPC 19. Input Common-Mode Voltage Range vs. Supply Voltage TPC 20. Maximum Output Swing vs. Load Resistance TPC 21. Output Voltage Swing vs. Supply Voltage A 700 NO LOAD 600 +125 C +25 C 500 –55 C 1000 SHORT CIRCUIT CURRENT – mA 35 SUPPLY CURRENT (PER AMPLIFIER) – VS = 15V TA = 25 C 100 TA = –55 C 30 25 20 15 TA = +25 C TA = +125 C VS = 15V OUTPUT SHORTED TO GROUND TA = +125 C TA = +25 C 10 1 400 AV = +1 0.1 –15 –20 –25 –30 TA = –55 C –35 0 1 2 3 TIME FROM OUTPUT SHORT – Mins 4 300 0.01 200 0 5 10 15 20 0.001 1 10 100 1k 10k 100k SUPPLY VOLTAGE – V TPC 22. Supply Current (per Amplifier) vs. Supply Voltage TPC 23. Closed-Loop Output Impedance vs. Frequency TPC 24. Short-Circuit Current vs. Time Temperature 70 60 50 40 30 –IN 20 10 2.5k 0 10 +IN 100 1k LOAD CAPACITANCE – pF 10k 2.5k VS = 15V TA = 25 C AVCL = +1 VOUT = 100mV p–p V+ OVERSHOOT – % VOUT TPC 25. Small-Signal Overshoot vs. Capacitance Load V– TPC 26. Simplified Schematic Showing One Amplifier –6– REV. D OP497 APPLICATIONS INFORMATION Extremely low bias current over the full military temperature range makes the OP497 attractive for use in sample-and-hold amplifiers, peak detectors, and log amplifiers that must operate over a wide temperature range. Balancing input resistances is not necessary with the OP497. Offset voltage and TCVOS are degraded only minimally by high source resistance, even when unbalanced. The input pins of the OP497 are protected against large differential voltage by back-to-back diodes and current-limiting resistors. Common-mode voltages at the inputs are not restricted, and may vary over the full range of the supply voltages used. The OP497 requires very little operating headroom about the supply rails, and is specified for operation with supplies as low as ± 2 V. Typically, the common-mode range extends to within 1 V of either rail. The output typically swings to within 1 V of the rails when using a 10 kΩ load. AC PERFORMANCE 100 90 10 0% 2V 50 s Figure 3. Large-Signal Transient Response (AVCL = 1) GUARDING AND SHIELDING The OP497’s ac characteristics are highly stable over its full operating temperature range. Unity-gain small-signal response is shown in Figure 1. Extremely tolerant of capacitive loading on the output, the OP497 displays excellent response even with 1000 pF loads (Figure 2). 100 90 To maintain the extremely high input impedances of the OP497, care must be taken in circuit board layout and manufacturing. Board surfaces must be kept scrupulously clean and free of moisture. Conformal coating is recommended to provide a humidity barrier. Even a clean PC board can have 100 pA of leakage currents between adjacent traces, so guard rings should be used around the inputs. Guard traces are operated at a voltage close to that on the inputs, as shown in Figure 4, so that leakage currents become minimal. In noninverting applications, the guard ring should be connected to the common-mode voltage at the inverting input. In inverting applications, both inputs remain at ground, so the guard trace should be grounded. Guard traces should be on both sides of the circuit board. UNITY GAIN FOLLOWER NONINVERTING AMPLIFIER – 1/4 10 0% – 1/4 OP497 + OP497 + 20mV 5s INVERTING AMPLIFIER MINI-DIP BOTTOM VIEW 8 1/4 1 A B Figure 1. Small-Signal Transient Response (CLOAD = 100 pF, AVCL = 1) – OP497 + 100 90 Figure 4. Guard Ring Layout and Connections 10 0% 20MV 5s Figure 2. Small-Signal Transient Response (CLOAD = 1000 pF, AVCL = 1) REV. D –7– OP497 OPEN-LOOP GAIN LINEARITY PRECISION CURRENT PUMP The OP497 has both an extremely high gain of 2000 V/mv minimum and constant gain linearity. This enhances the precision of the OP497 and provides for very high accuracy in high closed-loop gain applications. Figure 5 illustrates the typical open-loop gain linearity of the OP 497 over the military temperature range. DIFFERENTIAL INPUT VOLTAGE – 10µV/ DIV Maximum output current of the precision current pump shown in Figure 7 is ± 10 mA. Voltage compliance is ± 10 V with ± 15 V supplies. Output impedance of the current transmitter exceeds 3 MΩ with linearity better than 16 bits. R3 10k RL = 10k VS = 15V VCM = 0V TA = +125 C – VIN + R1 10k R2 10k 2 1/4 3 OP497 1 +15V 8 R5 10k IOUT 10mA TA = +25C R4 10k V V IOUT = IN = IN = 10mA/ V R5 100 5 6 7 1/4 OP497 4 TA = –55 C –15V Figure 7. Precision Current Pump PRECISION POSITIVE PEAK DETECTOR –15 –10 –5 0 5 10 15 OUTPUT VOLTAGE – Volts Figure 5. Open-Loop Linearity of the OP497 APPLICATIONS Precision Absolute Value Amplifier In Figure 8, the CH must be of polystyrene, Teflon*, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the OP497. 1k +15V 0.1 F 6 2N930 1k CH 1k 1/4 8 7 VOUT The circuit of Figure 6 is a precision absolute value amplifier with an input impedance of 30 MΩ. The high gain and low TCVOS of the OP497 ensure accurate operation with microvolt input signals. In this circuit, the input always appears as a common-mode signal to the op amps. The CMR of the OP497 exceeds 120 dB, yielding an error of less than 2 ppm. +15V 1N4148 2 1/4 VIN 1k 3 1 OP497 OP497 5 4 0.1 F –15V RESET R1 1k C1 30pF D1 1N4148 R3 1k C2 0.1 F Figure 8. Precision Positive Peak Detector SIMPLE BRIDGE CONDITIONING AMPLIFIER 6 1/4 2 3 8 1/4 1 D2 1N4148 R2 2k OP497 C3 4 0.1 F 5 OP497 7 0V < VOUT < 10V Figure 9 shows a simple bridge conditioning amplifier using the OP497. The transfer function is: VIN  ∆R  RF VOUT = VREF    R + ∆R  R The REF43 provides an accurate and stable reference voltage for the bridge. To maintain the highest circuit accuracy, RF should be 0.1% or better with a low temperature coefficient. –15V Figure 6. Precision Absolute Value Amplifier *Teflon is a registered trademark of the Dupont Company. –8– REV. D OP497 +5V 2 2.5 V VREF REF43 6 R 4 R RF R 2 1/4 R+ R 3 C2 100pF 6 R2 33k 1/4 OP497 1 VOUT 1 2 Q1 3 6 7 Q2 5 8 R1 133k V+ IIN 2 1/4 3 8 1 C1 100pF IO 5 OP497 7 VOUT +5V 6 1/4 5 8 VOUT = VREF ( 7 R R )F R+ R R MAT-04E Q3 10 9 14 IREF Q4 12 13 OP497 4 –5V VIN OP497 4 V– Figure 9. A Simple Bridge Conditioning Amplifier Using the OP497 NONLINEAR CIRCUITS R3 50k R4 50k –15V Figure 10. Squaring Amplifier Due to its low input bias currents, the OP497 is an ideal log amplifier in nonlinear circuits such as the square and square root circuits shown in Figures 10 and 11. Using the squaring circuit of Figure 10 as an example, the analysis begins by writing a voltage-loop equation across transistors Q1, Q2, Q3, and Q4. A similar analysis made for the square-root circuit of Figure 11 leads to its transfer function: VOUT = R2 (VIN )(IREF ) R1 I I  I  I  VT 1In  IN  + VT 2 In  IN  = VT 3 In  I O  + VT 4 In  REF   IS 1   IS 2   IS 4   IS 3  All the transistors of the MAT04 are precisely matched and at the same temperature, so the IS and VT terms cancel, giving: 2InI IN = InIO + InIREF = In ( IO × IREF ) Exponentiating both sides of thick equation leads to: In these circuits, IREF is a function of the negative power supply. To maintain accuracy, the negative supply should be well regulated. For applications where very high accuracy is required, a voltage reference may be used to set IREF. An important consideration for the squaring circuit is that a sufficiently large input voltage can force the output beyond the operating range of the output op amp. Resistor R4 can be changed to scale IREF, or Rl and R2 can be varied to keep the output voltage within the usable range. R2 33k IO (I IN )2 = IREF IO IIN C1 100pF V+ VIN R1 33k 2 3 8 1/4 6 Q1 1 2 3 6 5 C2 100pF 1/4 Op amp A2 forms a current-to-voltage converter which gives VOUT = R2 × IO. Substituting (VIN/R1) for IIN and the above equation for IO, yields: OP497 7 VOUT MAT-04E 14 13 8 9 Q4 12 IREF VOUT  R2  VIN  =    IREF   R1  2 7 Q3 Q2 5 10 OP497 4 V– 1 R5 2k R3 50k R4 50k –15V Figure 11. Square-Root Amplifier Unadjusted accuracy of the square-root circuit is better than 0.1% over an input voltage range of 100 mV to 10 V. For a similar input voltage range, the accuracy of the squaring circuit is better than 0.5%. REV. D –9– OP497 OP497 SPICE MACRO-MODEL Figure 12 and Table I show the node and net list for a SPICE macro-model of the OP497. The model is a simplified version of the actual device and simulates important dc parameters such as VOS, IOS, IB, AVO, CMR, VO, and ISY. AC parameters such as slew rate, gain and phase response, and CMR change with frequency are also simulated by the model. The model uses typical parameters for the OP497. The poles and zeros in the model were determined from the actual open and closed-loop gain and phase response of the OP497. In this way, the model presents an accurate ac representation of the actual device. The model assumes an ambient temperature of 25°C. 99 V1 R3 C2 5 2 –IN RIN2 8 Q1 R1 CIN RIN1 1 7 IOS R2 +IN –+ EOS 9 D1 D2 10 R5 Q2 11 98 R6 EREF 14 I1 50 CCM RCM1 15 ECM RCM2 16 17 ENZ RNZ2 CNZ RNZ1 18 G2 19 R10 20 R15 C5 V2 D4 G1 R7 C3 6 R4 12 13 D3 C5 G2 98 99 R16 ISY 21 20 D7 D8 –+ 22 –+ V4 D5 23 24 V3 G6 R18 L1 VO 27 R19 R17 D9 25 G4 26 G5 D6 D10 G7 50 Figure 12. OP497 Macro Model –10– REV. D OP497 Table I. OP497 SPICE Net-List * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * *SUBCKT OP497 1 2 99 50 27 * * INPUT STAGE AND POLE AT 6 MHz * RIN1 1 7 2500 RIN2 2 8 2500 R1 8 3 6.782E8 R2 7 3 6.782E8 R3 5 99 542.57 R4 6 99 542.57 CIN 7 8 3E-12 C2 5 6 24.445E-12 I1 4 50 0.1E-3 IOS 7 8 15E-12 EOS 9 7 POLY(1) 16 21 40E-6 1 Q1 5 8 10 QX Q2 6 9 11 QX R5 10 4 25.374 R6 11 4 25.374 D1 8 9 DX D2 9 8 DX * EREF 98 0 21 0 1 * *GAIN STAGE AND DOMINANT POLE AT 0.11 Hz * R7 1 98 2.1703E9 C3 2 98 666.67E-12 G1 98 12 5 V1 99 13 1.275 V2 11 9 1.275 D3 12 13 DX D4 14 12 DX * *COMMON-MODE GAIN NETWORK WITH ZERO AT 50 MHz * RCM1 15 16 1E6 CCM 15 16 3.18E-9 RCM2 16 98 1 ECM 15 98 3 21 177.83E-3 * NEGATIVE ZERO AT 1.8 MHz * E1 17 98 12 21 1E6 R8 17 18 1E6 C4 17 18 –88.419E-15 R9 18 98 1 * * POLE AT 6 MHz * G2 98 19 18 21 1E-6 R15 20 98 1E6 C8 20 98 26.526E-15 * * POLE AT 1.8 MHz * G6 98 20 19 21 1E-6 R20 20 98 1E6 C10 20 98 88.419E-15 * * OUTPUT STAGE * R16 99 21 160 k R17 21 50 160 k ISY 99 50 331E-6 V3 23 22 1.9 D5 20 23 DX V4 22 24 1.9 D6 24 20 DX D7 99 25 DX G4 25 50 20 22 5E-3 D9 50 25 DY D8 99 26 DX G5 26 50 22 20 5E-3 D10 50 26 DY G6 22 99 99 20 5E-3 R18 99 22 200 G7 50 22 20 50 5E-3 R19 22 50 200 L1 22 27 0.1E-6 * * MODELS USED * .MODEL QX NPN (BF = 1.25E6) .MODEL DX (IS = 1E-15) .MODEL DZ D(IS = 1E-15 BV = 50) .ENDS OP497 REV. D –11– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Ceramic DIP (Y-Suffix) 0.005 (0.13) MIN 14 PIN 1 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 1 0.785 (19.94) MAX PIN 1 16-Lead Wide-Body SOIC (S-Suffix) 0.4133 (10.50) 0.3977 (10.00) 0.098 (2.49) MAX 8 16 9 7 0.2992 (7.60) 0.2914 (7.40) 0.310 (7.87) 0.220 (5.59) 1 8 0.4193 (10.65) 0.3937 (10.00) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 0°–15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 0.050 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) 0.0098 (0.25) 45 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 8 0.0192 (0.49) SEATING 0 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 14-Lead Epoxy DIP (P-Suffix) 14 PIN 1 0.015 (0.381) MIN 1 0.795 (20.19) 0.725 (18.41) 7 8 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0°–15° 0.015 (0.38) 0.008 (0.20) 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.100 0.014 (0.36) (2.54) BSC Revision History Location 11/01—Data Sheet changed from REV. C to REV. D. Page Edits to PIN CONNECTIONS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 – 12– PRINTED IN U.S.A. C00309–0–2/02(D)