REF02DPZ

5 V Precision Voltage Reference/Temperature Transducer REF02 FEATURES PIN CONFIGURATIONS 5 V output: ±0.3% maximum Temperature voltage output: 1.96 mV/°C Adjustment range: ±3% minimum Excellent temperature stability: 8.5 ppm/°C maximum Low noise: 15 µV p-p maximum Low supply current: 1.4 mA maximum Wide input voltage range: 7 V to 40 V High load-driving capability: 10 mA No external components Short-circuit proof NC 8 NC 1 NC 7 VIN 2 VOUT 6 NC 3 5 TRIM 4 00375-F-001 GROUND (CASE) NC = NO CONNECT. DO NOT CONNECT ANYTHING ON THESE PINS. SOME OF THEM ARE RESERVED FOR FACTORY TESTING PURPOSES. 8 NC REF02 7 NC TOP VIEW (Not to Scale) 6 VOUT 5 TRIM NC 1 VIN 2 TEMP 3 GENERAL DESCRIPTION GND 4 00375-F-002 Figure 1. 8-Lead TO-99 (J-Suffix) NC = NO CONNECT. DO NOT CONNECT ANYTHING ON THESE PINS. SOME OF THEM ARE RESERVED FOR FACTORY TESTING PURPOSES. The REF02 precision voltage reference provides a stable 5 V output that can be adjusted over a ±6% range with minimal effect on temperature stability. Single-supply operation over an input voltage range of 7 V to 40 V, low current drain of 1 mA, and excellent temperature stability are achieved with an improved band gap design. Low cost, low noise, and low power make the REF02 an excellent choice whenever a stable voltage reference is required. Applications include DACs and ADCs, portable instrumentation, and digital voltmeters. The versatility of the REF02 is enhanced by its use as a monolithic temperature transducer. For new designs, refer to the ADR02. NC NC NC NC NC Figure 2. 8-Lead PDIP (P-Suffix), 8-Lead CERDIP (Z-Suffix) and 8-Lead SOIC (S-Suffix) 3 2 1 20 19 NC 4 18 NC REF02 17 NC TOP VIEW (Not to Scale) 16 NC 15 VOUT 14 NC NC 6 TEMP 7 NC NC TRIM 10 11 12 13 NC 9 GND NC 8 00375-F-003 VIN 5 NC = NO CONNECT. DO NOT CONNECT ANYTHING ON THESE PINS. SOME OF THEM ARE RESERVED FOR FACTORY TESTING PURPOSES. Figure 3. 20-Terminal LCC (RC-Suffix) OUTPUT RESISTORS INPUT R9 R11 R12 883C PRODUCT 18kΩ 2kΩ 6.1kΩ 4.5kΩ 15kΩ 2 R14 Q15 Q7 Q8 Q14 R15 Q13 Q18 Q9 Q12 Q16 Q11 Q10 R6 R3 Q6 OUTPUT 6 R13 R12* Q4 R5 Q17 Q5 R4 Q1 Q19 Q21 C1 Q3 Q20 Q2 R9* TRIM ≈1.23V 5 R11* 3 R1 R10 TEMP R2 GROUND 4 *SEE OUTPUT RESISTORS 00375-F-004 P, S, J, Z PACKAGES 18kΩ R7 R8 REF02 OPTION Figure 4. Simplified Schematic Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. REF02 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Output Adjustment ........................................................................ 10 Pin Configurations ........................................................................... 1 Temperature Monitoring........................................................... 11 Revision History ............................................................................... 2 Reference Stack with Excellent Line Regulation .................... 11 Specifications..................................................................................... 3 Precision Current Source .......................................................... 12 Electrical Specifications............................................................... 3 Supply Bypassing ........................................................................ 12 Absolute Maximum Ratings............................................................ 7 Outline Dimensions ....................................................................... 13 Thermal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 15 ESD Caution.................................................................................. 7 REVISION HISTORY 12/05—Rev. H to Rev. I Changes to Figure 14...................................................................... 10 Changes to Ordering Guide .......................................................... 15 5/05—Rev. G to Rev. H Updated Figure 4 .............................................................................. 1 Changes to Specifications ................................................................ 3 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 15 2/05—Rev. F to Rev. G Changes to Specifications ................................................................ 3 Change to Outline Dimensions .................................................... 13 7/04—Rev. E to Rev. F Updated Format..................................................................Universal Changes to Simplified Schematic ................................................... 1 Changes to Specifications ................................................................ 3 Changes to Specifications ................................................................ 4 Changes to Specifications ................................................................ 5 Changes to Specifications ................................................................ 6 Changes to Figure 18...................................................................... 10 Changes to Ordering Guide .......................................................... 15 10/03—Rev. C to Rev. D Updated TPCs.....................................................................Universal Changes to Features .........................................................................1 Changes to Electrical Specifications ..............................................2 Change to Absolute Maximum Ratings ........................................4 Changes to Ordering Guide .............................................................4 Deleted Typical Electrical Characteristics table ........................... 4 Deleted Wafer Test Limits ................................................................4 Deleted Figure 1.................................................................................4 10/02—Rev. B to Rev. C Changes to Features ..........................................................................1 Changes to General Description .....................................................1 Changes to Simplified Schematic ....................................................1 Changes to Specifications.................................................................2 Changes to Absolute Maximum Ratings .......................................5 Changes to Package Type ................................................................5 Changes to Ordering Guide .............................................................5 Updated to Outline Dimensions .................................................. 11 3/04—Rev. D to Rev. E Changes to Features.......................................................................... 1 Changes to Specifications ................................................................ 2 Changes to Ordering Guide ............................................................ 4 Replaced TPCs 3 and 4 .................................................................... 5 Added Temperature Monitoring section ...................................... 7 Updated Figure 5 ............................................................................. 7 Deleted Table I .................................................................................. 7 Updated Figure 6 ............................................................................. 7 Rev. I | Page 2 of 16 REF02 SPECIFICATIONS ELECTRICAL SPECIFICATIONS @ VIN = 15 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Output Voltage Output Adjustment Range Output Voltage Noise1 P, Z, and S Packages J Package 883 Parts Line Regulation2 Load Regulation2 Turn-On Settling Time1 Quiescent Supply Current Load Current Sink Current3 Short-Circuit Current Temperature Voltage Output4 883C Product P, S, J, and Z Packages Symbol VO ∆VTRIM en p-p tON ISY IL IS ISC Conditions IL = 0 mA RP = 10 kΩ 0.1 Hz to 10 Hz REF02A/REF02E Min Typ Max 4.985 5.000 5.015 ±3 ±6 REF02/REF02H Min Typ Max 4.975 5.000 5.025 ±3 ±6 15 20 10 0.006 0.005 5 1.0 15 20 10 0.006 0.006 5 1.0 VIN = 8 V to 40 V IL = 0 mA to 10 mA To ±0.1% of final value No load 10 −0.3 VO = 0 VT VT –0.5 30 630 550 1 Guaranteed by design. Line and load regulation specifications include the effect of self-heating. 3 During sink current test, the device meets the output voltage specified. 4 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF. 2 Rev. I | Page 3 of 16 15 0.010 0.010 1.4 10 –0.3 Unit V % –0.5 30 µV p-p µV p-p µV p-p %/V %/mA µs mA mA mA mA 630 550 mV mV 15 0.010 0.010 1.4 REF02 @ VIN = 15 V, −55°C ≤ TA ≤ +125°C for REF02A and REF02; 0°C ≤ TA ≤ 70°C for REF02E and REF02H; IL = 0 mA, unless otherwise noted. Table 2. Parameter Output Voltage Change with Temperature1, 2 Symbol ∆VOT Output Voltage Temperature Coefficient3 TCVO Change in VO Temperature Coefficient with Output Adjustment Line Regulation VIN = 8 V to 40 V4 Load Regulation IL = 0 mA to 8 mA4 Temperature Voltage Output Temperature Coefficient5 883C Product P, S, J, and Z Packages Conditions 0°C ≤ TA ≤ 70°C −55°C ≤ TA ≤ +125°C REF02A/REF02E Min Typ Max 0.02 0.06 0.06 0.15 3 8.5 RP = 10 kΩ 0.7 0°C ≤ TA ≤ 70°C −55°C ≤ TA ≤ +125°C 0°C ≤ TA ≤ 70°C −55°C ≤ TA ≤ +125°C 0.007 0.009 0.006 0.007 REF02/REF02H Min Typ Max 0.07 0.17 0.18 0.45 10 25 0.7 0.012 0.015 0.010 0.012 0.007 0.009 0.007 0.009 Unit % % ppm/°C ppm/% 0.012 0.015 0.012 0.015 %/V %/V %/mA %/mA TCVT 2.10 1.96 1 2.10 1.96 mV/°C mV/°C ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as a percentage of 5 V. − V MIN V ∆VOT = MAX × 100 5V 2 ∆VOT specification applies trimmed to 5,000 V or untrimmed. 3 TCVO is defined as ∆VOT divided by the temperature range. ∆VOT TCV O = 70°C 4 Line and load regulation specifications include the effect of self-heating. 5 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF. Rev. I | Page 4 of 16 REF02 @ VIN = 15 V, TA = 25°C, unless otherwise noted. Table 3. Parameter Output Voltage Output Adjustment Range Output Voltage Noise1 P, Z, and S Packages J Package 883 Parts Line Regulation2 Load Regulation2 Symbol VO ∆VTRIM en p-p Turn-On Settling Time1 Quiescent Supply Current Load Current Sink Current3 Short-Circuit Current Temperature Voltage Output4 883C Product P, S, J, and Z Packages tON ISY IL IS ISC Conditions IL = 0 mA RP = 10 kΩ 0.1 Hz to 10 Hz Min 4.950 ±2.7 REF02C Typ Max 5.000 5.050 ±6.0 15 20 12 0.009 0.006 VIN = 8 V to 40 V IL = 0 mA to 8 mA IL = 0 mA to 4 mA To ±0.1% of final value No load 5 1.0 8 −0.3 VO = 0 VT VT −0.5 30 630 550 1 Guaranteed by design. Line and load regulation specifications include the effect of self-heating. During sink current test, the device meets the output voltage specified. 4 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF. 2 3 Rev. I | Page 5 of 16 Min 4.900 ±2.0 REF02D Typ Max 5.000 5.100 ±6.0 −0.5 30 µV p-p µV p-p µV p-p %/V %/mA %/mA µs mA mA mA mA 630 550 mV mV 15 20 0.010 18 0.015 0.015 0.015 5 1.0 1.6 8 −0.3 Unit V % 0.04 0.04 2.0 REF02 @ VIN = 15 V, IL = 0 mA, 0°C ≤ TA ≤ 70°C for REF02CJ, REF02CZ, and REF02DP; and −40°C ≤ TA ≤ +85°C for REF02CP and REF02CS, unless otherwise noted. Table 4. Parameter Output Voltage Change with Temperature1, 2 Output Voltage Temperature Coefficient3 Change in VO Temperature Coefficient with Output Adjustment Line Regulation4 Load Regulation4 Temperature Voltage Output Temperature Coefficient5 883C Product P, S, J, and Z Packages Symbol ∆VOT Conditions TCVO Min REF02C Typ Max 0.14 0.45 Min REF02D Typ Max 0.49 1.7 Unit % 20 0.7 65 70 0.7 250 RP = 10 kΩ ppm/°C ppm/% VIN = 8 V to 40 V IL = 0 mA to 5 mA 0.011 0.008 0.018 0.018 0.012 0.016 0.05 0.05 %/V %/mA TCVT 2.10 1.96 1 2.10 1.96 mV/°C mV/°C ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed as a percentage of 5 V. V − VMIN ∆VOT = MAX × 100 5V 2 ∆VOT specification applies trimmed to 5,000 V or untrimmed. 3 TCVO is defined as ΔVOT divided by the temperature range. ∆VOT TCV O = 70°C 4 Line and load regulation specifications include the effect of self-heating. 5 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF. Rev. I | Page 6 of 16 REF02 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Input Voltage Output Short-Circuit Duration to Ground or VIN Storage Temperature Range J, RC, and Z Packages P Package Operating Temperature Range REF02A, REF02J, REF02RC REF02CJ, REF02CZ REF02CP, REF02CS, REF02E, and REF02H Lead Temperature Range (Soldering 10 sec) 1 Rating1 40 V Indefinite –65°C to +150°C –65°C to +125°C –55°C to +125°C 0°C to 70°C –40°C to +85°C 300°C Absolute maximum ratings apply to both DICE packaged parts, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 6. Package Type TO-99 (J) 8-Lead CERDIP (Z) 8-Lead PDIP (P) 20-Terminal Ceramic LCC (RC) 8-Lead SOIC (S) 1 θJA1 170 162 110 120 160 θJC 24 26 50 40 44 Unit °C/W °C/W °C/W °C/W °C/W θJA is specified for worst-case mounting conditions; device in socket for TO, CERDIP, PDIP, and LCC packages; and device soldered to printed circuit board for SOIC package. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. I | Page 7 of 16 REF02 TYPICAL PERFORMANCE CHARACTERISTICS 20 VIN = 15V TA = 25°C 1k 100 10 10 100 1k 10k FREQUENCY (Hz) 100k 19 18 17 16 15 00375-F-008 MAXIMUM LOAD CURRENT (mA) TA = 25°C 00375-F-005 OUTPUT NOISE (µV p-p) 10k 14 10 1M Figure 5. Output Wideband Noise vs. Bandwidth (0.1 Hz to Frequency Indicated) 15 20 25 30 INPUT VOLTAGE (V) 35 40 Figure 8. Maximum Load Current vs. Input Voltage 76 0.0031 1.4 66 0.0100 1.3 56 0.0310 46 0.1000 36 0.3100 26 1.0000 100 1k 10k FREQUENCY (Hz) 10.0000 1M 100k LOAD REG–T/LOAD REG (25°C) LINE REGULATION (%/V) Figure 6. Line Regulation vs. Frequency 1.2 1.1 1.0 0.9 0.8 00375-F-009 0 10 3.1000 00375-F-006 VIN = 15V TA = 25°C 16 0.7 0.6 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 Figure 9. Normalized Load Regulation (∆IL = 10 mA) vs. Temperature 1.4 0.016 VIN = 15V 1.3 0.012 0.010 0.008 0.006 0.004 0.002 0 –10 DEVICE IMMERSED IN 75°C OIL BATH 25°C 0 10 20 TIME (s) 30 40 1.2 1.1 1.0 0.9 0.8 00375-F-010 LINE REG–T/LINE REG (25°C) 0.014 00375-F-007 PERCENT CHANGE IN OUTPUT VOLTAGE (%) LINE REGULATION (dB) VIN = 15V 0.7 0.6 –60 50 Figure 7. Output Change Due to Thermal Shock –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 10. Normalized Line Regulation vs. Temperature Rev. I | Page 8 of 16 140 REF02 0.03 30 0.02 0.01 0 5 10 15 20 INPUT VOLTAGE (V) 25 VIN = 15V 1.1 1.0 0.9 0.8 00375-F-026 QUIESCENT CURRENT (mA) 1.2 –20 0 20 40 60 80 TEMPERATURE (°C) 100 15 10 5 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 13. Maximum Load Current vs. Temperature 1.3 –40 20 0 –60 30 Figure 11. Line Regulation vs. Input Voltage 0.7 –60 25 00375-F-012 MAXIMUM LOAD CURRENT (mA) VIN = 15V 00375-F-011 LINE REGULATION (%/V) TA = 25°C 120 140 Figure 12. Quiescent Current vs. Temperature Rev. I | Page 9 of 16 140 REF02 OUTPUT ADJUSTMENT The REF02 trim terminal can be used to adjust the output voltage over a 5 V ± 300 mV range. This feature lets the system designer trim system errors by setting the reference to a voltage other than 5 V. The output also can be set to exactly 5.00 V or to 5.12 V for binary applications. Adjustment of the output does not significantly affect the temperature performance of the device. The temperature coefficient change is approximately 0.7 ppm/°C for 100 mV of output adjustment. +15V 2 VIN VO U1 REF02 REF02 VO TEMP TRIM GND R1 470kΩ 5 10kΩ +15V 4 pot 10kΩ 0.1µF –5V OP02 5kΩ R2 1kΩ 00375-F-015 VOUT 10kΩ TEMP TRIM GND 00375-027 VIN –15V Figure 14. Output Adjustment Circuit Figure 16. ±5 V Reference V O+ +2.5V +5V 2 R1 5.6kΩ 6 REF02 +18V VREF R2 5.6kΩ VIN 7 4 6 REF02 VO+ = GND 4 –18V R1 R2 ), VO– = ) (V (V R1 + R2 REF R1 + R2 REF 4 +VO –2.5V Figure 17. ±2.5 V Reference Figure 15. Burn-In Circuit Rev. I | Page 10 of 16 – 2 OP02 –9V + 3 00375-F-016 2 00375-F-014 VIN 3 +5V 6 REF02 V+ (12V TO 32V) TEMPERATURE MONITORING The REF02 provides a TEMP output (Pin 3) that varies linearly with temperature. This output can be used to monitor the temperature change in the system. The voltage at VTEMP is approximately 550 mV at 25°C, and the temperature coefficient is approximately 1.96 mV/°C (see Figure 18). 850 800 R7 27kΩ 2 VIN VO HEATING ELEMENT REF02 TEMP R1 (9.2kΩ) 6 R6 2 R3 (1.3kΩ) 3 8 V+ + CMP02 V– 3 – 7 4 1 VIN = 9V SAMPLE SIZE = 6 GND (SEE NOTE 1) 4 R2 1.5kΩ R5 2.2kΩ R4 2.7kΩ Z PACKAGE AND 833 PRODUCT 700 ∆VTEMP/∆T = 2.1mV/°C NOTES 1. REF02 SHOULD BE THERMALLY CONNECTED TO SUBSTANCE BEING HEATED. 2. NUMBERS IN PARENTHESES ARE FOR A SETPOINT TEMPERATURE OF 60°C. 3. R3 = R1 || R2 || R6 650 600 ∆VTEMP/∆T = 1.96mV/°C 550 00375-F-019 TEMP PIN OUTPUT (mV) 750 Figure 20. Temperature Controller J, S, AND P PACKAGES 500 REFERENCE STACK WITH EXCELLENT LINE REGULATION 00375-F-017 450 –25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 18. Voltage at TEMP Pin vs. Temperature A voltage change of 39.2 mV at the TEMP pin corresponds to a 20°C change in temperature. The TEMP function is provided as a convenience rather than a precise feature. Since the voltage at the TEMP node is acquired from the band gap core, current pulling from this pin has a significant effect on VOUT. Care must be taken to buffer the TEMP output with a suitable low bias current op amp, such as the AD8601, AD820, or OP1177. Using any of these three op amps results in less than a 100 µV change in ΔVOUT (see Figure 19). Without buffering, even tens of microamps drawn from the TEMP pin can cause VOUT to fall out of specification. Two REF01s and one REF02 can be stacked to yield 5.00 V, 15.00 V, and 25.00 V outputs. An additional advantage is nearperfect line regulation of the 5.0 V and 15.0 V output. A 27 V to 55 V input change produces an output change that is less than the noise voltage of the devices. A load bypass resistor (RB) provides a path for the supply current (ISY) of the 15.00 V regulator. In general, any number of REF01s and REF02s can be stacked this way. For example, 10 devices yield 10 outputs in 5 V or 10 V steps. The line voltage can change from 100 V to 130 V. Care must be taken, however, to ensure that the total load currents do not exceed the maximum usable current (typically 21 mA). 27V TO 55V 2 VIN U1 REF02 VIN VTEMP 1.9mV/°C V+ U2 OP1177 V– VIN VOUT TEMP REF02 VO TRIM 5 10kΩ GND TRIM 4 GND 2 00375-F-018 15V 15V 6 VO VIN VO 6 10V REF02 Figure 19. Temperature Monitoring TRIM GND 2 VIN 6 5 4 10kΩ 5V VO REF02 TRIM 5 10kΩ RB 6.8kΩ GND 00375-F-020 400 –50 4 Figure 21. Reference Stack Rev. I | Page 11 of 16 REF02 PRECISION CURRENT SOURCE SUPPLY BYPASSING A current source with 35 V output compliance and excellent output impedance can be obtained using this circuit. REF02 keeps the line voltage and power dissipation constant in the device; the only important error consideration at room temperature is the negative supply rejection of the op amp. The typical 3 µV/V PSRR of the OP02E creates a 20 ppm change (3 µV/V × 35 V/5 V) in output current over a 25 V range. For example, a 5 mA current source can be built (R = 1 kΩ) with 350 MΩ output impedance. For best results, it is recommended that the power supply pin be bypassed with a 0.1 µF disc ceramic capacitor. IOUT VOLTAGE COMPLIANCE: –9V TO +25V 2 VIN VO 6 REF02 3 TEMP TRIM 5 IOUT = + R 5V + 1mA R GND +50V 4 2 VIN –15V VO Figure 24. Current Sink REF02 2 5kΩ 2 GND VIN 4 6 +15V +15V 2 VIN V O REF02 R (TRIM FOR CALIBRATION) C 1 GND 5kΩ LSB MSB 0.1µF REF02 6 5kΩ B1 B2 B3 B4 B5 B6 B7 B8 lO DAC08 5 V– V+ GND 4 R 4 CC lO VLC 4 OP02 2 5kΩ C +15V 7 6 2 OP02E –15V –15V Figure 25. DAC Reference VO = 0V TO 25V 3 +7.5V (±10%) +7.5V 4 IO = 00375-F-021 2 –5V 5V R VIN VO REF02HJ 6 VO(+) = +3V R1 20kΩ Figure 22. Precision Current Source GND 4 15V R2 13.3kΩ A1 1/2 OP04CK 2 VIN VO 6 –7.5V –7.5V REF02 TEMP TRIM 5 R IOUT = + 5V + 1mA R 1/2 OP04CK GND R4 2kΩ 4 VOLTAGE COMPLIANCE: –25V TO +8V 00375-F-022 3 VO(–) = –3V A2 R3 1kΩ –7.5V (±10%) IOUT Figure 26. ±3 V Reference Figure 23. Current Source Rev. I | Page 12 of 16 EO 00375-F-024 6 VO 00375-F-023 35V 20 ×10–6 × 5mA 00375-F-025 RO = REF02 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.055 (1.40) MAX 8 5 REFERENCE PLANE 0.310 (7.87) 0.220 (5.59) 1 0.1850 (4.70) 0.1650 (4.19) 4 0.5000 (12.70) MIN 0.2500 (6.35) MIN 0.0500 (1.27) MAX 0.1000 (2.54) BSC 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) SEATING PLANE 0.3350 (8.51) 0.3050 (7.75) 0.3700 (9.40) 0.3350 (8.51) 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.023 (0.58) 0.014 (0.36) 0.1600 (4.06) 0.1400 (3.56) 5 15° 0° 3 7 2 0.0400 (1.02) 0.0100 (0.25) 0.0450 (1.14) 0.0270 (0.69) 8 1 0.1000 (2.54) BSC 0.0190 (0.48) 0.0160 (0.41) 0.0400 (1.02) MAX 0.015 (0.38) 0.008 (0.20) 6 4 0.2000 (5.08) BSC 0.0340 (0.86) 0.0280 (0.71) 0.0210 (0.53) 0.0160 (0.41) 45° BSC BASE & SEATING PLANE CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-002-AK CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 27. 8-Lead Ceramic Dual In-Line Package [CERDIP] Z-Suffix (Q-8) Dimensions shown in inches and (millimeters) Figure 29. 8-Lead Metal Header Package [TO-99] J-Suffix (H-08) Dimensions shown in inches and (millimeters) 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 1 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.100 (2.54) 0.064 (1.63) 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 19 18 0.358 (9.09) 0.342 (8.69) SQ 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.358 (9.09) MAX SQ 0.088 (2.24) 0.054 (1.37) COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.055 (1.40) 0.045 (1.14) 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 14 13 0.050 (1.27) BSC 8 9 45° TYP 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body P-Suffix (N-8) Dimensions shown in inches and (millimeters) Figure 30. 20-Terminal Ceramic Leadless Chip Carrier [LCC] RC-Suffix (E-20A) Dimensions shown in inches and (millimeters) Rev. I | Page 13 of 16 REF02 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 0.50 (0.0196) × 45° 0.25 (0.0099) 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 31. 8-Lead Standard Small Outline Package [SOIC] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) Rev. I | Page 14 of 16 REF02 ORDERING GUIDE TA = 25°C Model REF02AJ/883C1 REF02AZ REF02AZ/883C1 REF02CJ REF02CP REF02CPZ2 REF02CS REF02CS-REEL REF02CS-REEL7 REF02CSZ2 REF02CSZ-REEL2 REF02CSZ-REEL72 REF02CZ REF02DP REF02DPZ2 REF02EJ REF02EZ REF02J REF02HJ REF02HZ REF02HP REF02HPZ2 REF02HS REF02HSZ2 REF02RC/8831 REF02Z 1 2 ∆VOS Max (mV) ±15 ±15 ±15 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±50 ±100 ±100 ±15 ±15 ±25 ±25 ±25 ±25 ±25 ±25 ±25 ±25 ±25 Temperature Range −55°C to +125°C −55°C to +125°C −55°C to +125°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −55°C to +125°C Consult sales for 883 data sheet. Z = Pb-free part. Rev. I | Page 15 of 16 Package Description 8-Lead TO-99 8-Lead CERDIP 8-Lead CERDIP 8-Lead TO-99 8-Lead PDIP Package Option J-Suffix (H-08) Z-Suffix (Q-8) Z-Suffix (Q-8) J-Suffix (H-08) P-Suffix (N-8) 8-Lead PDIP 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead TO-99 8-Lead CERDIP 8-Lead TO-99 8-Lead TO-99 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC 8-Lead SOIC 20-Lead LCC 8-Lead CERDIP P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) S-Suffix (R-8) Z-Suffix (Q-8) P-Suffix (N-8) P-Suffix (N-8) J-Suffix (H-08) Z-Suffix (Q-8) J-Suffix (H-08) J-Suffix (H-08) Z-Suffix (Q-8) P-Suffix (N-8) P-Suffix (N-8) S-Suffix (R-8) S-Suffix (R-8) RC-Suffix (E-20A) Z-Suffix (Q-8) REF02 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00375-0-12/05(I) Rev. I | Page 16 of 16