SC1889
Adaptive RF Power Amplifier Linearizer
and Dual RMS Power Measurement Unit
General Description
The SC1889 is part of Scintera’s 2nd generation RF
PA linearizer (RFPAL™) family providing increased
ACLR correction over the previous generation as well
as support for EVDO, TD-SCDMA, WiMAX®, HSDPA,
LTE, and TD-LTE waveforms. The SC1889 is a fullyadaptive, RFin/RFout predistortion linearization
solution that precisely compensates RF power
amplifier (PA) non-linearities including AM/AM and
AM/PM distortion, spectral regrowth, memory effects
and other system level impairments.
The SC1889 substantially increases the final stage
PA efficiency by reducing out-of-band energy. The
SC1889 is a complete system-on-chip (SoC) solution
optimized for Class A/AB and Doherty RF power
amplifiers operating at a power level of 5W to 60W
(RMS). The SC1889 measures the feedback signal
from the power amplifier output, and optimizes the
correction function by minimizing distortion. SC1889
correction function is generated using RF-domain
analog signal processing allowing the SC1889 to
operate over a wide bandwidth at very low power
consumption.
Applications
Features
SC1889 (PC = 00): RFPAL
RFin/RFout PA Linearizer SoC in Standard
CMOS
Fully Adaptive Compensation
Low Power Consumption:
o Duty Cycled (9 %) Feedback: 420mW
o Full Adaptation: 1.06W
Frequency Range: 698MHz to 2800MHz
Input Signal Bandwidth: Up to 60MHz
Up to 28dB ACLR and 38dB IMD Improvement*
Packaged in 9mmx9mm QFN Package
Operating Case Temperature: -40°C to +100°C
Fully RoHS Compliant, Green Materials
Pin Compatible with SC1887 and SC1869
SC1889 (PC = 11): RFPAL + PMU (Optional)**
Dual RMS Power Measurement Unit (RFIN and
RFFB)
o 30dB of Dynamic Range
o 0.10dB Typical Accuracy (Top 20dB)
o 0.50dB Typical Accuracy (Bottom 10dB)
Frequency Range: 698MHz to 2200MHz
Benefits
Cellular Infrastructure
o Single/Multicarrier, Multistandard:
WCDMA/EVDO, TD-SCDMA, WiMAX,
WCDMA/HSDPA, LTE, and TD-LTE
o Traditional In-Cabinet BTS Amplifiers, RRU,
Tower Mounted Power Amplifiers, Microwave
Backhaul, Booster Amplifiers, Microcells,
Picocells, DAS, AAS, and MIMO Systems
Other Applications
o Software Defined Radios (SDRs), Mobile
Military Communications, and TV White
Space
o Any Application Requiring PA Linearization
Wide Range of PAs and Output Power
o Amplifier: Class A/AB and Doherty
o PA Output Power: Up to 60W (RMS)
o PA Process: LDMOS, GaAs, and GaN
*Performance dependent on amplifier, bias, and waveform.
**Refer to the SC1889-PMU0011 data sheet for detailed
specifications.
Ease of Use
o Integrated RFin/RFout Solution
o Operates Over Wide Frequency Band
o Reduced Software Development
o No Algorithm Development or Control
Required—Automatically Adjusts to the
Signal and PA Environment
o Supports Wide Range of Modulation
Schemes
Smaller Total System Form Factors
o Reduced Heatsink Size and Weight
o Small Implementation Size (< 9cm2)
Reduces Operating Costs
o Reduces Energy Consumption Supporting
Green Initiatives
o Reduces Amplifier Power Consumption and
Thermal Dissipation
o Increases Amplifier Reliability
Reduces BOM Costs and Total Volume
o Power Supply, Heatsink, and Enclosure
o Reduced Back-Off Reduces Transistor Costs
19-6955; Rev 0.1; August 2014
1
Application Block Diagram
Introduction to Predistortion Using the SC1889
Wideband signals in today’s telecommunications systems have high peak-to-average ratios and stringent
spectral regrowth specifications. These specifications place high linearity demands on power amplifiers.
Linearity may be achieved by backing off output power at the price of reducing efficiency. However, this
increases the component and operating costs of the power amplifier. Better linearity may be achieved
through the use of digital predistortion and other linearization techniques, but many of these are time
consuming and costly to implement.
Wireless service providers are deploying networks with wider coverage, greater subscriber density, and
higher data rates. These networks require more efficient power amplifiers. Additionally, the emergence of
distributed architectures and active antenna systems is driving the need for smaller and more efficient
power amplifier implementations. Further, there continues to be a strong push toward reducing the total
capital and operating costs of base stations.
With the SC1889, the complex signal processing is done in the RF domain resulting in a simple system-onchip that offers wide signal bandwidth, broad frequency of operation, and very low power consumption. It is
an elegant solution that reduces development costs and speeds time to market. Applicable across a broad
range of signals — including 2G, 3G, 4G wireless, and other modulation types—the powerful analog signal
processing engine is capable of linearizing the most efficient power amplifier topologies. The SC1889 is a
true RFin and RFout solution, supporting modular power amplifier designs that are independent of the
baseband and transceiver subsystems. The SC1889 delivers the required efficiency and performance
demanded by today’s wireless systems.
19-6955; Rev 0.1; August 2014
2
DVDD18
RESERVED8
TESTSEL2
TESTSEL1
TESTSEL0
DVDD18
DVDD33
STATO
TXENB
DVDD18
SDO
SDI
SSN
SCLK
WDTEN
RESETN
Pin Configuration (Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DVDD18
1
48
DVDD18
RESERVED1
2
47
AVDD18
RESERVED2
3
46
XTALO
AVDD18
4
45
XTALI
AVDD33
5
44
FLTCAP3N
GND
6
43
FLTCAP3P
GND
7
42
AVDD18
RFOUTP
8
41
AVDD18
RFOUTN
9
40
FLTCAP2N
SC1889
GND
10
39
FLTCAP2P
AVDD18
11
38
FLTCAP1N
AVDD18
12
37
FLTCAP1P
ENVOUTP
13
36
AVDD18
ENVOUTN
14
35
AVDD18
34
FLTCAP0N
33
FLTCAP0P
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
AVDD18
AVDD33
ADCIN1P
ADCIN1N
ADCIN2P
ADCIN2N
AVDD33
GND
RFFBP
RFFBN
GND
16
RFINN
BGRES
RFINP
15
GND
GND
AVDD33
65 - GNDPAD
3
Pin Description
PIN
1
NAME
DVDD18
2
RESERVED1
3
RESERVED2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD18
AVDD33
GND
GND
RFOUTP
RFOUTN
GND
AVDD18
AVDD18
ENVOUTP
ENVOUTN
GND
BGRES
AVDD33
GND
RFINP
RFINN
GND
AVDD18
AVDD33
ADCIN1P
ADCIN1N
ADCIN2P
ADCIN2N
AVDD33
GND
RFFBP
RFFBN
GND
TYPE
Supply
Analog Out
Reserved
Analog Out
Reserved
Supply
Supply
Supply
RF Shield
Analog Out
RF Shield
Supply
Supply
Analog Out
Reserved
FUNCTION
+1.8V DC Supply Voltage for digital circuits.
Do not connect. Reserved for internal use.
Do not connect. Reserved for internal use.
+1.8V DC Supply Voltage for analog circuits.
+3.3V DC Supply Voltage for analog circuits.
Ground.
Ground for shield of RF signal.
RF Output Signal, differential output. See S-parameters for
complex impedance values.
Ground for shield of RF signal.
+1.8V DC Supply Voltage for analog circuits.
+1.8V DC Supply Voltage for analog circuits.
Envelope Out. Do not connect. Reserved for future use.
Supply
Analog In
Supply
RF Shield
Ground.
Bandgap Resistor.
+3.3V DC Supply Voltage for analog circuits.
Ground for shield of RF signal.
Analog In
RF Input Signal, differential input. See S-parameters for complex
impedance values.
RF Shield
Supply
Supply
Ground for shield of RF signal.
+1.8V DC Supply Voltage for analog circuits.
+3.3V DC Supply Voltage for analog circuits.
Analog In
Reserved
Do not connect. Reserved for future use. .
Analog In
Reserved
Do not connect. Reserved for future use.
Supply
RF Shield
+3.3V DC Supply Voltage for analog circuits.
Ground for shield of RF signal.
Analog In
RF Feedback Signal, differential input. See S-parameters for
complex impedance values.
RF Shield
Ground for shield of RF signal.
4
Pin Description (continued)
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
NAME
FLTCAP0P
FLTCAP0N
AVDD18
AVDD18
FLTCAP1P
FLTCAP1N
FLTCAP2P
FLTCAP2N
AVDD18
AVDD18
FLTCAP3P
FLTCAP3N
XTALI
XTALO
AVDD18
DVDD18
RESETN
TYPE
Analog In
Analog Out
Supply
Supply
Digital In
50
WDTEN
Digital In
51
52
53
54
55
SCLK
SSN
SDI
SDO
DVDD18
Digital In
Digital In
Digital In
Digital Out
Supply
56
TXENB
Digital In
Reserved
57
STATO
Digital Out
58
59
DVDD33
DVDD18
Supply
Supply
60
TESTSEL0
Digital In
61
TESTSEL1
62
TESTSEL2
63
RESERVED8
64
DVDD18
Digital In
Reserved
Digital In
Reserved
Digital In
Reserved
Supply
65
GNDPAD
Supply
Analog Out
Supply
Supply
FUNCTION
Dedicated external filter capacitor #0.
+1.8V DC Supply Voltage for analog circuits.
+1.8V DC Supply Voltage for analog circuits.
Analog Out
Dedicated external filter capacitor #1.
Analog Out
Dedicated external filter capacitor #2.
Supply
Supply
Analog Out
+1.8V DC Supply Voltage for analog circuits.
+1.8V DC Supply Voltage for analog circuits.
Dedicated external filter capacitor #3.
20 MHz clock reference from crystal or resonator.
+1.8V DC Supply Voltage for analog circuits.
+1.8V DC Supply Voltage for digital circuits.
Reset when "Low". Has internal pullup to DVDD33.
Watch Dog Timer Enable. WDTEN enabled when high. Has
internal pullup to DVDD33. See applications schematic for
further details.
SPI clock. Has internal pulldown to GND.
SPI slave select enabled "Low". Has internal pullup to DVDD33.
SPI slave data input to RFPAL. Has internal pulldown to GND.
SPI slave data output from RFPAL. Three-state. DVDD33 logic.
+1.8V DC Supply Voltage for digital circuits.
Transmit Enable. Do not connect. Reserved for future use.
Has internal pullup to DVDD33. See applications schematic for
further details.
General purpose Status Output as defined in Firmware Release
Notes. Open-drain output with internal pullup to DVDD33.
+3.3V DC Supply Voltage for digital circuits.
+1.8V DC Supply Voltage for digital circuits.
Test Select 0. Required for FW upgrades. Has internal pulldown
to GND. See applications schematic for further details.
Do not connect. Reserved for internal use.
Has internal pulldown to GND.
Do not connect. Reserved for internal use.
Has internal pulldown to GND.
Do not connect. Reserved for internal use.
Has internal pulldown to GND.
+1.8V DC Supply Voltage for digital circuits.
Common Ground for entire integrated circuit. Also provides path
for thermal dissipation.
5
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD33 to GND) ...... -0.3V to +3.8V
Supply Voltage (VDD18 to GND) ..... -0.2 V to +2.2V
Input Voltage (1.8V pins) ... -0.2V to (VDD18 + 0.2V)
Input Voltage (3.3V pins) ... -0.3V to (VDD33 + 0.3V)
Input into the Balun (RMS) ........................... +7dBm
Junction Temperature .................................. +150°C
Storage Temperature ..................... -65°C to +150°C
OPERATING RATING
Operating Case Temperature……-40°C to +100°C
Warning: Any stress beyond the ranges indicated may damage
the device permanently. The specified stress ratings do not imply
functional performance in these ranges. Exposure of the device
to the absolute maximum ratings for extended periods of time is
likely to degrade the reliability of this product.
DC CHARACTERISTICS
PARAMETER
Supply Voltage (VDD33 to GND)
Supply Voltage (VDD18 to GND)
Supply Peak Current (VDD33 to GND)1,2,3, 5
Supply Peak Current (VDD18 to GND)1,2,3, 5
Average Power Dissipation: Full-Scale Adaptation, Track, and PMU3, 5
Average Power Dissipation: Duty-Cycled Feedback2,4,5
MIN
3.1
1.7
TYP
3.3
1.8
59
592
1060
420
MAX
3.5
1.9
UNITS
V
V
mA
mA
mW
mW
Note 1: Peak current includes supply decoupling network. Refer to Hardware Design Guide for proper sizing of the on-board regulators.
Note 2: Characterized at typical voltages, +25°C operating case temperature and 20MHz input signal BW.
Note 3: Continuous adaptation, tracking (100% duty-cycled feedback) and Power Measurement Unit active or inactive.
Note 4: Duty-cycled feedback power dissipations averaged over ON time of 100ms (9%) and OFF time of 1.024s (91%).
Note 5: Power dissipation may be FW dependent. Refer to the FW release notes for any changes to values listed above.
RADIO FREQUENCY SIGNALS
PARAMETER
SYMBOL
Operating Frequency1
f
RFIN_BLN Range for
PRFIN_BLN_P
Maximum Correction
RFIN_BLN Range for
PRFIN_BLN
Maximum Correction
RFFB_BLN Range for
PRFFB_BLN_P
Maximum Correction
RFFB_BLN Range for
PRFFB_BLN
Maximum Correction
RFIN_BLN
PRFIN_BLN
Operating Range
RFFB_BLN Operating
PRFFB_BLN
Range
RF Input Signal
PARIN
Peak-to Avg. Ratio3
Input Signal Bandwidth
BWsignal
Noise Power6
CONDITIONS
MIN
698
RECOMMENDED
MAX
2800
UNITS
MHz
Peak power
-4
4
6
dBm
RMS power2
-9
-6
-4
dBm
Peak power
-14
-4
-2
dBm
RMS power2
-19
-14
-12
dBm
RMS power2
-40
-4
dBm
RMS power2
-45
-12
dBm
CCDF4
probability=10-4
5 to 10
1.2
Referred to
0dBm at PA
input
dB
40 or 60
-138
-135
5
MHz
dBm/Hz
Note 1: See Operating Frequency Ranges table for frequency limits of each defined band.
Note 2: A peak to average ratio (PAR) of 5dB to 10dB is used for this table.
Note 3: Higher PAR values can be supported but at a reduction to a combination of the input signal range and IM correction limits.
Note 4: CCDF = Complementary cumulative distribution function; a measurement of peak to average ratio or crest factor.
Note 5: > 40MHz operation requires a fully occupied signal bandwidth.
Note 6: Worst case over PVT guaranteed by bench characterization.
6
OPERATING FREQUENCY RANGES
FREQUENCY RANGE1
698MHz to 960MHz
800MHz to 1450MHz
1350MHz to 2450MHz
1600MHz to 2800MHz
RECOMMENDED APPLICATIONS
Lowband cellular (698MHz to 960MHz)
IF for SATCOMM (1000MHz to 1400MHz)
LTE for Japan (1400MHz to 1510MHz)
Highband cellular (1600MHz to 2800MHz)
DESIGNATION
-04
-05
-06
-07
Note 1: Default is -07. May be reprogrammed by user for other ranges listed above. Refer to Design Guide for programming information.
DIGITAL I/O—DC CHARACTERISTICS
PARAMETER
SYMBOL
CMOS Input Logic-Low
VIL
CMOS Input Logic-High
VIH
CMOS Output Logic-Low
VOL
CMOS Output Logic-High
VOH
SDO CMOS Output Current
IOL/IOH
STATO CMOS Output Current
IOL/IOH
CONDITIONS
VDD = 3.3V
MIN
-0.3
2.0
TYP
MAX
0.8
0.4
VDD = 3.3V
Three-State
Open Drain
2.4
-4.0
-4.0
SERIAL PERIPHERAL INTERFACE (SPI) BUS SPECIFICATIONS
PARAMETER
SYMBOL CONDITIONS
MIN
Select Setup Time
tSS
100
Select Hold Time
tSH
250
Select Disable Time
tDIS
100
Data Setup Time
tDS
25
Data Hold Time
tDH
45
Rise Time
tR
Fall Time
tF
Clock Period
tCP
250
Clock High Time
tCH
100
Time to Output Valid
tOV
Output Data Disable
tOD
+4.0
0.0
TYP
MAX
25
25
100
0
UNITS
V
V
V
V
mA
mA
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Use of the SPI interface offers the user access to certain monitoring and diagnostic functions as well as
other planned advanced features. The SPI bus interface is also used to program the internal EEPROM,
allowing changes to the operating frequency range, field upgrades and firmware updates.
7
CRYSTAL REQUIREMENTS
PARAMETER
ESR
Capacitive Load to Ground
Frequency Accuracy
SYMBOL
CONDITIONS
MIN
TYP
10
Including aging and
temperature
Frequency Drift
MAX
50
12
250
UNITS
pF
ppm
100
ppm
Top Mark
SCINTERA
SC1889A
XXXXXXXXXX
WWYYRRRR
LINE
1
2
2
TOP MARK
SCINTERA
SC1889
A
2
-11
3
XXXXXXXXXX
4
4
4
WW
YY
RRRR
SCINTERA
SC1889A-11
XXXXXXXXXX
WWYYRRRR
DESCRIPTION
Company Name
Product Part Number
Product Revision
Product Configuration (PC):
BLANK = RFPAL Base Configuration
-11 = RFPAL + PMU configuration
Foundry Lot Number
(up to 10 characters)
Date Code - Work Week
Date Code - Year
Reserved
ESD
ESD (Electrostatic Discharge) sensitive device. Although this product incorporates ESD
protection circuitry, permanent damage may occur on devices subjected to electrostatic
discharges. Proper ESD precautions are recommended to avoid performance degradation or
device failure.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION CHARACTERISTICS
TEST METHODOLOGY
CLASS
Human Body Model (per JESD22-A114)
1C
Charge Device Model (per JESD22-C101)
II
VOLTAGE
1000
250
UNIT
V
V
8
Ordering Information
PART
SC1889A-00B00
SC1889A-00B11
DESCRIPTION
IC, RFPAL, 698MHz to 2800MHz, FW3.0.17.62
IC, RFPAL+PMU, 698MHz to 2800MHz,
FW3.0.17.62
Note: Parts are lead(Pb)-free and RoHS-compliant.
Shipping designator:
E = 7” tape and reel.
Append shipping designator (E) at end of part number. If left blank, designates bulk shipping option.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
64 QFN
K6499MK+1
21-0765
LAND PATTERN NO.
90-0605
9
Revision History
REVISION
NUMBER
0.1
REVISION
DATE
8/14
DESCRIPTION
PAGES
CHANGED
—
Scintera and RFPAL are trademarks of Maxim Integrated Products, Inc.
WiMAX is a registered certification mark and registered service mark of WiMAX Forum.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are
implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the
Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
© 2014 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
10
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