Octal Sample-and-Hold
with Multiplexed Input
SMP08*
a
FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
FUNCTIONAL BLOCK DIAGRAM
INPUT
(LSB)
A
B
(MSB)
C
INH
3
11
10
9
6
8 DGND
1 OF 8 DECODER
16 VDD
SW
APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
SW
SW
SW
SW
SW
SW
GENERAL DESCRIPTION
The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
± 1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual supply operation.
The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.
SW
13 CH0OUT
14 CH1OUT
15 CH2OUT
12 CH3OUT
1
CH4OUT
5
CH5OUT
2
CH6OUT
4 CH7OUT
HOLD CAPS
(INTERNAL)
7 VSS
SMP08
The SMP08 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP08 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, or surfacemount SOIC package.
*Protected by U.S. Patent No. 4,739,281.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
SMP08–SPECIFICATIONS(@ V
ELECTRICAL CHARACTERISTICS
Parameter
Linearity Error
Buffer Offset Voltage
Symbol
Hold Step
VHS
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
∆VCH/∆t
ISOURCE
ISINK
VOS
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Acquisition Time3
Hold Mode Settling Time
Channel Select Time
Channel Deselect Time
Inhibit Recovery Time
Slew Rate
Capacitive Load Stability
Analog Crosstalk
VINH
VINL
IIN
DD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
unless otherwise noted)
Conditions
–3 V ≤ VIN ≤ +3 V
TA = +25°C, VIN = 0 V
–40°C ≤ TA ≤ +85°C, VIN = 0 V
VIN = 0 V, TA = +25°C to +85°C
VIN = 0 V, TA = –40°C
TA = +25°C, VIN = 0 V
VIN = 0 V1
VIN = 0 V1
RL = 20 kΩ
Min
Typ
0.01
2.5
3.5
2.5
2
1.2
0.5
–3.0
Max
+3.0
Units
%
mV
mV
mV
mV
mV/s
mA
mA
V
0.8
1
V
V
µA
10
20
4
5
20
2.4
VIN = 2.4 V
0.5
TA = +25°C, –3 V to +3 V to 0.1%
To ± 1 mV of Final Value
3.6
1
90
45
90
3
500
–72
2
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
tAQ
tH
tCH
tDCS
tIR
SR
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