SMP08FS

a FEATURES Internal Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD4051 Pinout Low Cost APPLICATIONS Multiple Path Timing Deskew for ATE Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control INPUT 3 Octal Sample-and-Hold with Multiplexed Input SMP08* FUNCTIONAL BLOCK DIAGRAM (LSB) A 11 B 10 (MSB) C 9 INH 6 8 DGND 1 OF 8 DECODER 16 VDD SW 13 CH0OUT SW 14 CH1OUT SW 15 CH2OUT SW 12 CH3OUT SW 1 CH4OUT SW 5 CH5OUT SW 2 CH6OUT GENERAL DESCRIPTION The SMP08 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP08 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to ± 1/2 LSB in less than 7 microseconds. The SMP08’s output swing includes the negative supply in both single and dual supply operation. The SMP08 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP08 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. *Protected by U.S. Patent No. 4,739,281. SW HOLD CAPS (INTERNAL) 4 CH7OUT 7 VSS SMP08 The SMP08 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain adjustments. One or more SMP08s can be used with single or multiple DACs to provide multiple set points within a system. The SMP08 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, or surfacemount SOIC package. R EV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 SMP08–SPECIFICATIONS(@ V ELECTRICAL CHARACTERISTICS Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current Output Sink Current Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE Acquisition Time3 Hold Mode Settling Time Channel Select Time Channel Deselect Time Inhibit Recovery Time Slew Rate Capacitive Load Stability Analog Crosstalk 2 DD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = – 40 C to +85 C for SMP08F, unless otherwise noted) Symbol VOS VHS ∆VCH/∆t ISOURCE ISINK Conditions –3 V ≤ VIN ≤ +3 V TA = +25°C, VIN = 0 V –40°C ≤ TA ≤ +85°C, VIN = 0 V VIN = 0 V, TA = +25°C to +85°C VIN = 0 V, TA = –40°C TA = +25°C, VIN = 0 V VIN = 0 V1 VIN = 0 V1 RL = 20 kΩ Min Typ 0.01 2.5 3.5 2.5 2 Max 10 20 4 5 20 +3.0 1.2 0.5 –3.0 2.4 Units % mV mV mV mV mV/s mA mA V V V µA µs µs ns ns ns V/µs pF dB dB mA mA VINH VINL IIN tAQ tH tCH tDCS tIR SR VIN = 2.4 V TA = +25°C, –3 V to +3 V to 0.1% To ± 1 mV of Final Value 0.5 3.6 1 90 45 90 3 500 –72 60 75 4 5 0.8 1 7