SMP18FPZ

Octal Sample-and-Hold with Multiplexed Input SMP18 a FEATURES High Speed Version of SMP08 Internal Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD4051 Pinout Low Cost FUNCTIONAL BLOCK DIAGRAM INPUT (LSB) A B (MSB) C INH 3 11 10 9 6 8 DGND 1 OF 8 DECODER 16 VDD SW APPLICATIONS Multiple Path Timing Deskew for A.T.E. Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control SW SW SW SW SW GENERAL DESCRIPTION The SMP18 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP18 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to ± 1/2 LSB in less than 2.5 microseconds. The SMP18’s output swing includes the negative supply in both single and dual supply operation. The SMP18 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP18 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. SW SW 13 CH0OUT 14 CH1OUT 15 CH2OUT 12 CH3OUT 1 CH4OUT 5 CH5OUT 2 CH6OUT 4 CH7OUT HOLD CAPS (INTERNAL) 7 VSS SMP18 The SMP18 offers significant cost and size reduction over discrete designs. It is available in a 16-pin plastic DIP, a narrow body SO-16 surface-mount SOIC package or the thin TSSOP-16 package. The SMP18 is a higher speed direct replacement for the SMP08. The SMP18 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain adjustments. One or more SMP18s can be used with single or multiple DACs to provide multiple set points within a system. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 SMP18–SPECIFICATIONS(@ V ELECTRICAL CHARACTERISTICS Parameter Symbol Linearity Error Buffer Offset Voltage VOS Hold Step VHS Droop Rate Output Source Current Output Sink Current Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE2 Acquisition Time3 Hold Mode Settling Time Channel Select Time Channel Deselect Time Inhibit Recovery Time Slew Rate Capacitive Load Stability Analog Crosstalk SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current ∆VCH/∆t ISOURCE ISINK VINH VINL IIN tAQ tH tCH tDCS tIR SR DD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP18F, unless otherwise noted) Conditions Min –3 V ≤ VIN ≤ +3 V TA = +25°C, VIN = 0 V –40°C ≤ TA ≤ +85°C, VIN = 0 V VIN = 0 V, TA = +25°C to +85°C VIN = 0 V, TA = –40°C TA = +25°C, VIN = 0 V VIN = 0 V1 VIN = 0 V1 RL = 20 kΩ 0.01 2.5 3.5 4 2 1.2 0.5 –3.0 Max VIN = 2.4 V 0.5 TA = +25°C, –3 V to +3 V to 0.1% To ± 1 mV of Final Value 3.5 1 90 45 90 6 500 –72 VSS = ± 5 V to ± 6 V TA = +25°C –40°C ≤ TA ≤ +85°C 60 Units +3.0 % mV mV mV mV mV/s mA mA V 0.8 1 V V µA 10 20 6 8 40 2.4