SSM2160S-REEL

6-Channel, Serial Input Master/Balance Volume Controls SSM2160 FEATURES Clickless Digitally Controlled Level Adjustment SSM2160: 6 Channels 7-Bit Master Control Gives 128 Levels of Attenuation 5-Bit Channel Controls Give 32 Levels of Gain Master/Channel Step Size Set by External Resistors 100 dB Dynamic Range Automatic Power-On Mute Excellent Audio Characteristics: 0.01% THD+N 0.001% IMD (SMPTE) –90 dBu Noise Floor –80 dB Channel Separation 90 dB SNR Single-and Dual-Supply Operation APPLICATIONS Home Theater Receivers Surround Sound Decoders Circle Surround® and AC-3® Decoders DSP Soundfield™ Processors HDTV and Surround TV Audio Systems Automotive Surround Sound Systems Multiple Input Mixer Consoles and Amplifiers GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM V+ V– VREF POWER SUPPLY AND REFERENCE GENERATOR VCA CH1 IN CH1 OUT 5-BIT CHANNEL DAC CH2 IN VCA CH2 OUT 5-BIT CHANNEL DAC CH3 IN VCA CH3 OUT 5-BIT CHANNEL DAC CH4 IN VCA CH4 OUT The SSM2160 allows digital control of volume of six audio channels, with a master level control and individual channel controls. Low distortion VCAs (voltage controlled amplifiers) are used in the signal path. By using controlled rate-of-change drive to the VCAs, the “clicking” associated with switched resistive networks is eliminated in the master control. Each channel is controlled by a dedicated 5-bit DAC providing 32 levels of gain. A master 7-bit DAC feeds every control port giving 128 levels of attenuation. Step sizes are nominally 1 dB and can be changed by external resistors. Channel balance is maintained over the entire master control range. Upon power-up, all outputs are automatically muted. A 3-wire or 4-wire serial data bus enables interfacing with most popular microcontrollers. Windows® software and an evaluation board for controlling the SSM2160 are available. The SSM2160 can be operated from single supplies of +10 V to +20 V or dual supplies from ± 5 V to ± 10 V. An on-chip reference provides the correct analog common voltage for single-supply applications. The SSM2160 comes in a SOIC package; see the Ordering Guide for details. 5-BIT CHANNEL DAC CH5 IN VCA CH5 OUT 5-BIT CHANNEL DAC CH6 IN VCA CH6 OUT 5-BIT CHANNEL DAC 7-BIT MASTER DAC STEP SIZE ADJUST CH SET MSTR SET MSTR OUT CLK DATA LD WRITE SHIFT REGISTER AND ADDRESS DECODER SSM2160 R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. = 2 C, A = 0 B, f R SSM2160–SPECIFICATIONS (V ==10 6k V,,Tunless5 otherwisednoted.) = 1 kHz, f S A V AUDIO L CLOCK = 250 kHz, Parameter AUDIO PERFORMANCE Noise Floor Total Harmonic Distortion + Noise Symbol NFL THD+N Conditions VIN = GND, BW= 20 kHz, AV = 0 dB1 Second and Third Harmonics Only, VOUT = 0 dBu2 AV = 0 dB Any Channel to Another NFL to Clip Point VS = ± 10 V Any Channel VS = ± 10 V, All Conditions of Master Attenuation and Channel Gain Min Typ –90 Max Unit dBu Channel Separation Dynamic Range ANALOG INPUT Maximum Level Impedance ANALOG OUTPUT Maximum Level3 Impedance Offset Voltage Minimum Resistive Load Maximum Capacitive Load MASTER ATTENUATOR ERROR AV = 0 dB AV = –20 dB AV = –40 dB AV = –60 dB CHANNEL MATCHING CHANNEL GAIN ERROR AV = 0 dB AV = 10 dB AV = 31 dB MUTE ATTENUATION VOLTAGE REFERENCE Accuracy Output Impedance CONTROL LOGIC Logic Thresholds High (1) Low (0) Input Current Clock Frequency Timing Characteristics POWER SUPPLIES Voltage Range SSM2160 SSM2160 Supply Current VREF ZOUT RL min CL max VIN max ZIN 0.01 80 100 0.035 % dB dB V rms kΩ 1.8 10 1.8 10 20 10 50 V rms Ω mV kΩ pF Measured from Best Fit of All Channels from 0 dB and –127 dB (or Noise Floor) Channel Gain = 0 dB Channel Gain = 0 dB Channel Gain = 0 dB Channel Gain = 0 dB ± 0.5 ± 1.0 ± 2.0 ± 2.5 ± 1.0 dB dB dB dB dB dB dB dB dB % Ω Master Attenuation = 0 dB ± 0.5 ± 1.0 ± 2.0 VIN = 0 dBu Percent of (V + ) + (V – ) 2 –95 ±5 5 Re: DGND 2.0 0.8 ±1 1000 1 See Timing Diagrams V V µA kHz VS V+, V– Single Supply Dual Supply No Load 10 ±5 20 20 ± 10 28 V V mA NOTES 1 Master = 0 dB; Channel = 0 dB. 2 Input level adjusted accordingly. 0 dBu = 0.775 V rms. 3 For other than ± 10 V supplies, maximum is V S/4. Specifications subject to change without notice. –2– R EV. A SSM2160 TIMING CHARACTERISTICS Timing Symbol tCL tCH tDS tDH tCW tWC tLW tWL tL tW3 Description Input Clock Pulsewidth, Low Input Clock Pulsewidth, High Data Setup Time Data Hold Time Positive CLK Edge to End of Write Write to Clock Setup Time End of Load Pulse to Next Write End of Write to Start of Load Load Pulsewidth Load Pulsewidth (3-Wire Mode) Min 200 200 50 75 100 50 50 50 250 250 Typ Max Unit ns ns ns ns ns ns ns ns ns ns NOTES 1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge. 2. For SPI™ or Microwire™ 3-wire bus operation, tie LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.) 3. If an idle HI clock is used, t CW and tWL are measured from the final negative transition to the idle state. 4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table. 5. Data must be sent MSB first. 0 CLK 1 1 DATA 0 1 WRITE 0 1 LD 0 D7 D6 D5 D4 D3 D2 D1 D0 tCH 1 CLK 0 tDS 1 DATA 0 1 WRITE 0 1 LD 0 tWC MSB D7 tCL tDH tCW tL tWL tLW Figure 1. Timing Diagrams R EV. A –3– SSM2160 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION 24-Lead SOIC V+ 1 AGND 2 VREF 3 CH1 OUT 4 CH1 IN 5 CH3 OUT 6 24 CH SET 23 MSTR OUT 22 MSTR SET 21 CH2 OUT Supply Voltage Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Single2 (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5 V Operating Temperature Range . . . . . . . . . . . . . . . 0°C to 70°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature Range . . . . . . . . . . . . . –65°C to +165°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C ESD Ratings SSM2160 20 CH2 IN 883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 2.5 kV PACKAGE THERMAL INFORMATION TOP VIEW 19 CH4 OUT (Not to Scale) 18 CH4 IN CH3 IN 7 17 CH6 OUT 16 CH6 IN 15 DATA 14 CLK 13 DGND CH5 OUT 8 CH5 IN 9 WRITE 10 LD 11 V– 12 Package Type 24-Lead SOIC JA 3 JC Unit °C/W 71 23 NOTES 1 Absolute maximum ratings apply at 25 °C, unless otherwise noted. 2 VS is the total supply span from V+ to V–. 3 JA is specified for the worst-case conditions for device soldered onto a circuit board for SOIC packages. ORDERING GUIDE Model SSM2160S SSM2160S-REEL EVAL-SSM2160EB Temperature Range 0°C to 70°C 0°C to 70°C Package Description 24-Lead SOIC 24-Lead SOIC Evaluation Board Package Option R-24 R-24 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2160 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– R EV. A SSM2160 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 Mnemonic V+ AGND Function Positive Power Supply. Refer to the Application Information section for details on the power supply. Internal Ground Reference for the Audio Circuitry. When operating the SSM2160 from dual supplies, AGND should be connected to ground. When operating from a single supply, AGND should be connected to VREF, the internally generated voltage reference. AGND may also be connected to an external reference. Refer to the Application Information section for more information on the power supply. VREF is the internally generated ground reference for the audio circuitry obtained from a buffered divider between V+ and V–. In a dual-supply application with the AGND pin connected to ground, VREF should be left floating. In a single-supply application, VREF should be connected to AGND. Refer to the Application Information section for more information on the power supply. Audio Output from Channel 1 Audio Input to Channel 1 Audio Output from Channel 3 Audio Input to Channel 3 Audio Output from Channel 5 Audio Input to Channel 5 A logic low voltage enables the SSM2160 to receive information at the DATA input (Pin 15). A logic high retains data at their previous settings (Figure 1). Serves as CHIP SELECT. Loads the Information Retained by WRITE into the SSM2160 at logic low (Figure 1). Negative Power Supply. Connect to ground in a single-supply application. Refer to the Application Information section for details on the power supply. Digital Ground Reference. This pin should always be connected to ground. All digital inputs, including WRITE, LD, CLK, and DATA are TTL input compatible; drive currents are returned to DGND. Clock Input. It is positive edge triggered (Figure 1). Channel and master control information flows MSB first into the DATA pin. Refer to the Address/Data Decoding Truth Table, Figure 7, for information on how to control the VCAs. Audio Input to Channel 6 Audio Output from Channel 6 Audio Input to Channel 4 Audio Output from Channel 4 Audio Input to Channel 2 Audio Output from Channel 2 Connected to the inverting input of an I-V converting op amp. It is used to generate a master control voltage from the master control DAC current output. A resistor connected from MSTR OUT to MSTR SET reduces the step size of the master control. See the Master/Channel Step Sizes section for more details. A 10 µF capacitor should be connected from MSTR OUT to MSTR SET to eliminate the zipper noise in the master control. Connected to the output of the I-V converting op amp. See MSTR SET description. The step size of the channel control can be increased by connecting a resistor from CH SET to V+. No connection to CH SET is required if the default value of 1 dB per step is desired. Minimum of 10 Ω external resistor. See the Master/Channel Step Sizes section for details. 3 VREF 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CH1 OUT CH1 IN CH3 OUT CH3 IN CH5 OUT CH5 IN WRITE LD V– DGND CLK DATA CH6 IN CH6 OUT CH4 IN CH4 OUT CH2 IN CH2 OUT MSTR SET 23 24 MSTR OUT CH SET R EV. A –5– SSM2160–Typical Performance Characteristics 10 1.0 1.0 TA = 25 C VS = 6V VIN = 0dBu RL = 10k CL = 50pF THD+N – % 0.5 VS = 10V VS = 15V 0.1 VS = 20V THD+N – % 0.1 TA = 25 C DUAL-SUPPLY OPERATION VIN = SINEWAVE @ 1kHz RL = 10k , CL = 50pF MASTER/CHANNEL = 0dB THD+N – % 0.1 0.01 VS = 12V VS = 6V 0.01 0.001 –70 –60 –40 –20 0 GAIN – dB 10 20 0.001 0.01 TA = 25 C SINGLE-SUPPLY OPERATION VIN = SINEWAVE @ 1kHz RL = 10k , CL = 50pF MASTER/CHANNEL = 0dB 1.0 0.1 INPUT VOLTAGE – V rms 10 0.01 0.005 0.05 VS = 5V 0.1 1.0 INPUT VOLTAGE – V rms 10 TPC 1. THD vs. Gain TPC 2. THD+N % vs. Amplitude TPC 3. THD+N % vs. Amplitude 0.1 –40 CHANNEL SEPARATION – dB OUTPUT – dB TA = 25 C DUAL-SUPPLY OPERATION VIN = 300mV rms@1kHz RL = 10k , CL = 50pF MASTER/CHANNEL = 0dB LPF: < 22kHz –40 –50 –60 –70 –80 –90 TA = 25 C VS = 6V VIN = 1V rms @ 1kHz RL = 10k , CL = 50pF THD+N – % TA = 25 C –50 VS = 6V VIN = 1V rms @ 1kHz –60 VIN = GND (NONSELECTED CH) RL = 100k , CL = 50pF –70 LPF: < 22kHz –80 –90 –100 –110 VS = 0.01 VS = 6V 12V –100 –110 0.001 20 100 1k FREQUENCY – Hz 10k 30k –120 20 100 1k FREQUENCY – Hz 10k 20k –120 20 100 1k FREQUENCY – Hz 10k 30k TPC 4. THD+N % vs. Frequency TPC 5. Channel Separation vs. Frequency TPC 6. Mute vs. Frequency –60 –65 –70 –75 TA = 25 C VS = 6V VIN = GND NOISE – dBu –80 –85 –90 –95 –100 –105 –110 –70 –60 –40 –30 –20 –10 0 10 GAIN – dB 20 30 40 TPC 7. Noise vs. Gain –6– R EV. A Typical Performance Characteristics–SSM2160 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 TA = 25 C VS = 12V VIN = 0dBu @ 1kHz RL = 100k MASTER = 20dB CHANNEL = 0dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 AMPLITUDE – dBu AMPLITUDE – dBu AMPLITUDE – dBu TA = 25 C VS = 12V VIN = –31dBu @ 1Hz RL = 100k MASTER = 0dB CHANNEL = 0dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 4 TA = 25 C VS = 12V VIN = –31dBu @ 1kHz RL = 100k MASTER = 0dB CHANNEL = 31dB 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY – kHz 0 2 4 6 8 10 12 14 16 18 20 22 FREQUENCY – kHz 6 8 10 12 14 16 18 20 22 FREQUENCY – kHz TPC 8. THD vs. Frequency (FFT) TPC 9. THD vs. Frequency (FFT) TPC 10. THD vs. Frequency (FFT) 0.100 TA = 25 C VS = 12V SMPTE 4:1 IM-FREQ 60Hz/7kHz RL = 100k 0.010 0.001 0.0001 0.05 0.1 1.0 INPUT AMPLITUDE – V rms 5.0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 2 AMPLITUDE – dBu 1MD (SMPTE) – % TA = 25 C VS = 12V RL = 100k A MASTER = 0dB CHANNEL = +31dB B MASTER/CHANNEL = 0dB –20 TA = 25 C –30 VS = 6V 10% LPF =