SSM2301-EVALZ

Filterless High Efficiency Mono 1.4 W Class-D Audio Amplifier SSM2301 FEATURES Filterless Class-D amplifier with Σ-Δ modulation No sync necessary when using multiple Class-D amplifiers from Analog Devices, Inc. 1.4 W into 8 Ω at 5.0 V supply with less than 1% THD + N 85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker Greater than 98 dB SNR (signal-to-noise ratio) Single-supply operation from 2.5 V to 5.0 V 20 nA ultralow shutdown current Short-circuit and thermal protection Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP packages Pop-and-click suppression Built-in resistors reduce board component count Fixed and user-adjustable gain configurations The SSM2301 operates with 85% efficiency at 1.4 W into 8 Ω from a 5.0 V supply and has a signal-to-noise ratio (SNR) that is greater than 98 dB. Spread-spectrum modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The SSM2301 has a micropower shutdown mode with a maximum shutdown current of 30 nA. Shutdown is enabled by applying a logic low to the SD pin. The device also includes pop-and-click suppression circuitry. This minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. The fully differential input of the SSM2301 provides excellent rejection of common-mode noise on the input. Input coupling capacitors can be omitted if the dc input common-mode voltage is approximately VDD/2. The SSM2301 also has excellent rejection of power supply noise, including noise caused by GSM transmission bursts and RF rectification. PSRR is typically 63 dB at 217 Hz. The gain can be set to 6 dB or 12 dB by utilizing the gain control select pin connected respectively to ground or to VDD. Gain can also be adjusted externally by inserting a resistor in series with each input pin. The SSM2301 is specified over the commercial temperature range (−40°C to +85°C). It has built-in thermal shutdown and output short-circuit protection. It is available in both an 8-lead, 3 mm × 3 mm lead-frame chip scale package (LFCSP) and an 8-lead MSOP package. APPLICATIONS Mobile phones MP3 players Portable gaming Portable electronics Educational toys GENERAL DESCRIPTION The SSM2301 is a fully integrated, high efficiency, Class-D audio amplifier designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.0 V supply. It is capable of delivering 1.4 W of continuous output power with less than 1% THD + N driving an 8 Ω load from a 5.0 V supply. The SSM2301 features a high efficiency, low noise modulation scheme that does not require external LC output filters. The modulation provides high efficiency even at low output power. FUNCTIONAL BLOCK DIAGRAM 10µF 0.1µF 0.01µF1 AUDIO IN+ AUDIO IN– 0.01µF 1 VBATT 2.5V TO 5.0V VDD OUT+ GAIN CONTROL MODULATOR FET DRIVER OUT– SSM2301 IN+ IN– GAIN SD BIAS SHUTDOWN OSCILLATOR GND POP/CLICK SUPPRESSION NOTES 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 06163-001 SSM2301 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution.................................................................................. 4 Pin Configurations and Function Descriptions ........................... 5 Typical Performance Characteristics ............................................. 6 Typical Application Circuits ......................................................... 10 Applications Information .............................................................. 12 Overview ..................................................................................... 12 Gain Selection............................................................................. 12 Pop-and-Click Suppression ...................................................... 12 Layout .......................................................................................... 12 Input Capacitor Selection.......................................................... 12 Proper Power Supply Decoupling ............................................ 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 10/07—Rev. 0 to Rev. A Added MSOP Package .......................................................Universal Changes to Features.......................................................................... 1 Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Deleted Evaluation Board Information Section ......................... 14 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 1/07—Revision 0: Initial Version Rev. A | Page 2 of 16 SSM2301 SPECIFICATIONS VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Symbol PO Conditions VDD = 5.0 V, RL = 8 Ω, THD = 1% f = 1 kHz, 20 kHz BW VDD = 5.0 V, RL = 8 Ω, THD = 10% f = 1 kHz, 20 kHz BW VDD = 3.6 V, RL = 8 Ω, THD = 1% f = 1 kHz, 20 kHz BW VDD = 3.6 V, RL = 8 Ω, THD = 10% f = 1 kHz, 20 kHz BW VDD = 2.5 V, RL = 8 Ω, THD = 1% f = 1 kHz, 20 kHz BW VDD = 2.5 V, RL = 8 Ω, THD = 10% f = 1 kHz, 20 kHz BW POUT = 1.4 W, 8 Ω, VDD = 5.0 V PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V PO = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 1.0 VCM = 2.5 V ± 100 mV at 217 Hz G = 6 dB; G = 12 dB Guaranteed from PSRR test VDD = 2.5 V to 5.0 V, dc input floating/ground VRIPPLE = 100 mV at 217 Hz, inputs are ac grounded, CIN = 0.01 μF, input referred VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V SD = GND GAIN pin = 0 V GAIN pin = VDD SD = VDD, SD = GND 2.5 70 55 1.8 2.0 5.0 85 63 4.2 3.5 2.9 20 6 12 150 210 1.2 0.5 30 5 >100 35 98 Min Typ 1.22 1.52 590 775 275 345 85 0.1 0.04 VDD − 1.0 Max Unit W W mW mW mW mW % % % V dB MHz mV V dB dB mA mA mA nA dB dB kΩ kΩ V V ms μs kΩ μV dB Efficiency Total Harmonic Distortion + Noise Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio η THD + N VCM CMRRGSM fSW VOOS VDD PSRR PSRRGSM ISY Supply Current Shutdown Current GAIN CONTROL Closed-Loop Gain Differential Input Impedance SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio ISD AV0 AV1 ZIN VIH VIL tWU tSD ZOUT en SNR ISY ≥ 1 mA ISY ≤ 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND VDD = 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are ac grounded, sine wave, AV = 6 dB, A weighting POUT = 1.4 W, RL = 8 Ω Rev. A | Page 3 of 16 SSM2301 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 2. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 6V VDD VDD −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 8-lead, 3 mm × 3 mm LFCSP 8-lead MSOP θJA 62 210 θJC 20.8 45 Unit °C/W °C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 4 of 16 SSM2301 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SD 1 GAIN 2 IN+ 3 IN– 4 PIN 1 INDICATOR 8 OUT– 7 GND 6 VDD 5 OUT+ 06163-002 SD 1 GAIN 2 IN+ 3 IN– 4 8 SSM2301 TOP VIEW (Not to Scale) SSM2301 TOP VIEW (Not to Scale) OUT– GND OUT+ 06163-103 7 6 5 VDD Figure 2. LFCSP Pin Configuration Figure 3. MSOP Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic SD GAIN IN+ IN− OUT+ VDD GND OUT− Description Shutdown Input. Active low digital input. Gain Selection. Digital input. Noninverting Input. Inverting Input. Noninverting Output. Power Supply. Ground. Inverting Output. Rev. A | Page 5 of 16 SSM2301 TYPICAL PERFORMANCE CHARACTERISTICS 100 RL = 8Ω, 15µH GAIN = 6dB VDD = 2.5V 100 10 VDD = 5.0V GAIN = 12dB RL = 8Ω, 15µH 10 1 THD + N (%) VDD = 3.6V 1 THD + N (%) 0.5W 0.1 1W 0.01 0.1 VDD = 5V 0.01 0.0001 0.25W 0.001 06163-004 0.001 0.01 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k OUTPUT POWER (W) Figure 4. THD + N vs. Output Power into 8 Ω, AV = 6 dB Figure 7. THD + N vs. Frequency, VDD = 5.0 V, AV = 12 dB, RL = 8 Ω 100 RL = 8Ω, 15µH GAIN = 12dB VDD = 2.5V 100 10 VDD = 3.6V GAIN = 6dB RL = 8Ω, 15µH 10 1 THD + N (%) THD + N (%) VDD = 3.6V 1 0.5W 0.1 0.25W 0.125W 0.01 0.1 VDD = 5V 0.01 0.0001 0.001 06163-003 0.001 0.01 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k OUTPUT POWER (W) Figure 5. THD + N vs. Output Power into 8 Ω, AV = 12 dB Figure 8. THD + N vs. Frequency, VDD = 3.6 V, AV = 6 dB, RL = 8 Ω 100 10 VDD = 5.0V GAIN = 6dB RL = 8Ω, 15µH 100 10 VDD = 3.6V GAIN = 12dB RL = 8Ω, 15µH 1 THD + N (%) 1 0.5W 1W THD + N (%) 0.5W 0.1 0.25W 0.125W 0.1 0.01 0.25W 0.01 0.001 0.001 06163-007 100 1k FREQUENCY (Hz) 10k 100k 100 1k FREQUENCY (Hz) 10k 100k Figure 6. THD + N vs. Frequency, VDD = 5.0 V, AV = 6 dB, RL = 8 Ω Figure 9. THD + N vs. Frequency, VDD = 3.6 V, AV = 12 dB, RL = 8 Ω Rev. A | Page 6 of 16 06163-010 0.0001 10 0.0001 10 06163-009 0.0001 10 06163-008 0.0001 10 SSM2301 100 VDD = 2.5V GAIN = 6dB RL = 8Ω, 15µH SHUTDOWN CURRENT (µA) 12 10 10 1 THD + N (%) 0.25W 0.125W 0.075W 8 VDD = 5.0V 6 VDD = 2.5V 4 VDD = 3.6V 2 0.1 0.01 0.001 100 1k FREQUENCY (Hz) 10k 100k 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 SHUTDOWN VOLTAGE (V) Figure 10. THD + N vs. Frequency, VDD = 2.5 V, AV = 6 dB, RL = 8 Ω Figure 13. Shutdown Current vs. Shutdown Voltage 100 10 VDD = 2.5V GAIN = 12dB RL = 8Ω, 15µH f = 1kHz GAIN = 6dB 1.4 RL = 8Ω 1.2 1.6 1 0.25W 0.125W OUTPUT POWER (W) THD + N (%) 1.0 10% 0.8 0.6 0.4 1% 0.1 0.075W 0.01 0.001 0.2 0 2.5 100 1k FREQUENCY (Hz) 10k 100k 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 11. THD + N vs. Frequency, VDD = 2.5 V, AV = 12 dB, RL = 8 Ω Figure 14. Maximum Output Power vs. Supply Voltage, AV = 6 dB, RL = 8 Ω, 5.0 4.5 4.0 1.8 f = 1kHz GAIN = 12dB 1.6 RL = 8Ω 1.4 SUPPLY CURRENT (mA) OUTPUT POWER (W) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 06163-019 1.2 1.0 0.8 0.6 0.4 0.2 06163-022 10% 1% 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 12. Supply Current vs. Supply Voltage, No Load Figure 15. Maximum Output Power vs. Supply Voltage, AV = 12 dB, RL = 8 Ω Rev. A | Page 7 of 16 06163-021 06163-012 0.0001 10 06163-020 06163-011 0.0001 10 0 SSM2301 100 90 80 70 VDD = 2.5V VDD = 3.6V RL = 8Ω, 15µH 350 VDD = 5.0V 300 250 200 VDD = 2.5V 150 100 50 0 VDD = 3.6V 400 RL = 8Ω, 15µH EFFICIENCY (%) VDD = 5.0V 60 50 40 30 20 10 06163-025 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 OUTPUT POWER (W) OUTPUT POWER (W) Figure 16. Efficiency vs. Output Power into 8 Ω Figure 19. Supply Current vs. Output Power into 8 Ω, One Channel 0.20 VDD = 3.6V 0.18 RL = 8Ω, 15µH 0.16 0 –10 –20 –30 POWER DISSIPATION (W) 0.14 PSRR (dB) 0.12 0.10 0.08 0.06 0.04 0.02 06163-050 –40 –50 –60 –70 –80 –90 06163-033 06163-034 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 –100 10 100 1k FREQUENCY (Hz) 10k 100k OUTPUT POWER (W) Figure 17. Power Dissipation vs. Output Power into 8 Ω at VDD = 3.6 V Figure 20. Power Supply Rejection Ratio vs. Frequency 0.30 VDD = 5.0V RL = 8Ω, 15µH 0 –10 –20 RL = 8Ω, 33µH GAIN = 6dB 0.25 POWER DISSIPATION (W) 0.20 CMRR (dB) –30 –40 –50 –60 0.15 0.10 0.05 –70 –80 10 06163-051 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 OUTPUT POWER (W) 100 1k FREQUENCY (Hz) 10k 100k Figure 18. Power Dissipation vs. Output Power into 8 Ω at VDD = 5.0 V Figure 21. Common-Mode Rejection Ratio vs. Frequency Rev. A | Page 8 of 16 06163-031 0 SUPPLY CURRENT (mA) SSM2301 7 6 5 4 7 6 5 4 SD INPUT 3 2 1 0 –1 06163-035 OUTPUT SD INPUT VOLTAGE (V) VOLTAGE (V) 3 2 1 0 –1 06163-036 OUTPUT –2 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 TIME (ms) –2 –20 0 20 40 60 80 100 120 140 160 180 TIME (ms) Figure 22. Turn-On Response Figure 23. Turn-Off Response Rev. A | Page 9 of 16 SSM2301 TYPICAL APPLICATION CIRCUITS 10µF 0.1µF VBATT 2.5V TO 5.0V VDD OUT+ GAIN CONTROL MODULATOR FET DRIVER OUT– SSM2301 0.01µF1 AUDIO IN+ AUDIO IN– VDD 0.01µF 1 GAIN SD IN+ IN– SHUTDOWN BIAS OSCILLATOR GND POP/CLICK SUPPRESSION Figure 24. Differential Input Configuration, Gain = 12 dB 10µF 0.1µF VBATT 2.4V TO 5.0V VDD OUT+ SSM2301 0.01µF AUDIO IN IN+ IN– 0.01µF GAIN SD GAIN CONTROL MODULATOR FET DRIVER OUT– SHUTDOWN BIAS OSCILLATOR GND POP/CLICK SUPPRESSION 06163-038 Figure 25. Single-Ended Input Configuration, Gain = 6 dB EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)] 10µF 0.1µF VBATT 2.4V TO 5.0V VDD OUT+ SSM2301 AUDIO IN+ AUDIO IN– 0.01µF1 V DD 0.01µF1 R R IN+ IN– GAIN SD GAIN CONTROL MODULATOR FET DRIVER OUT– SHUTDOWN BIAS OSCILLATOR GND POP/CLICK SUPPRESSION Figure 26. Differential Input Configuration, User-Adjustable Gain Rev. A | Page 10 of 16 06163-039 NOTES 1 INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. 06163-037 NOTES 1 INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. SSM2301 EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)] 10µF 0.1µF VBATT 2.4V TO 5.0V VDD OUT+ GAIN CONTROL MODULATOR FET DRIVER OUT– SSM2301 0.01µF AUDIO IN R R 0.01µF V DD IN+ IN– GAIN SD SHUTDOWN BIAS OSCILLATOR GND POP/CLICK SUPPRESSION 06163-040 Figure 27. Single-Ended Input Configuration, User-Adjustable Gain EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)] 10µF 0.1µF VBATT 2.4V TO 5.0V VDD OUT+ SSM2301 AUDIO IN+ AUDIO IN– 0.01µF1 GAIN SD 0.01µF1 R R IN+ IN– GAIN CONTROL MODULATOR FET DRIVER OUT– SHUTDOWN BIAS OSCILLATOR GND POP/CLICK SUPPRESSION Figure 28. Differential Input Configuration, User-Adjustable Gain EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)] 10µF 0.1µF VBATT 2.4V TO 5.0V VDD OUT+ SSM2301 0.01µF AUDIO IN R IN+ IN– 0.01µF R GAIN SD GAIN CONTROL MODULATOR FET DRIVER OUT– SHUTDOWN BIAS OSCILLATOR GND POP/CLICK SUPPRESSION 06163-042 Figure 29. Single-Ended Input Configuration, User-Adjustable Gain Rev. A | Page 11 of 16 06163-041 NOTES 1 INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. SSM2301 APPLICATIONS INFORMATION OVERVIEW The SSM2301 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces external component count, conserving board space and, thus, reducing system cost. The SSM2301 does not require an output filter but, instead, relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square-wave output. While most Class-D amplifiers use some variation of pulse-width modulation (PWM), the SSM2301 uses a Σ-Δ modulation to determine the switching pattern of the output devices. This provides a number of important benefits. Σ-Δ modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. Σ-Δ modulation reduces the amplitude of spectral components at high frequencies, thereby reducing EMI emission that might otherwise be radiated by speakers and long cable traces. The SSM2301 also offers protection circuitry for output shortcircuit and high temperature conditions. When the fault-inducing condition is removed, the SSM2301 automatically recovers without the need for a hard reset. LAYOUT As output power continues to increase, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Make track widths at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. Poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, PCB traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large-area ground plane be used for minimum impedances. Good PCB layouts also isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Properly designed multilayer printed circuit boards can reduce EMI emission and increase immunity to the RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a doubleside board is often disrupted with signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes or analog and digital power planes. GAIN SELECTION Pulling the GAIN pin of the SSM2301 high sets the gain of the speaker amplifier to 12 dB; pulling it low sets the gain of the speaker amplifier to 6 dB. It is possible to adjust the SSM2301 gain by using external resistors at the input. To set a gain lower than 12 dB, see Figure 26 for differential input configuration and Figure 27 for single-ended configuration. For external gain configuration from a fixed 12 dB gain, use the following formula: External Gain Settings = 20 log[4/(1 + R/150 kΩ)] To set a gain lower than 6 dB, see Figure 28 for differential input configuration and Figure 29 for single-ended configuration. For external gain configuration from a fixed 6 dB gain, use the following formula: External Gain Settings = 20 log[2/(1 + R/150 kΩ)] INPUT CAPACITOR SELECTION The SSM2301 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed (see Figure 24) or if using a single-ended source (see Figure 25). If high-pass filtering is needed at the input, the input capacitor, along with the input resistor of the SSM2301, forms a high-pass filter whose corner frequency is determined by the following equation: fC = 1/(2π × RIN × CIN) The input capacitor can have very important effects on the circuit performance. Not using input capacitors degrades the output offset of the amplifier as well as the PSRR performance. POP-AND-CLICK SUPPRESSION Voltage transients at the output of audio amplifiers may occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients may be generated when the amplifier system changes its operating mode. For example, the following can be sources of audible transients: system power-up/power-down, mute/unmute, input source change, and sample rate change. The SSM2301 has a popand-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. Rev. A | Page 12 of 16 SSM2301 PROPER POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality low ESL and low ESR capacitor, usually around 4.7 μF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 μF capacitor placed as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2301 helps maintain efficient performance. Rev. A | Page 13 of 16 SSM2301 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR 1 8 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 1.50 REF 5 4 1.89 1.74 1.59 0.90 MAX 0.85 NOM 12° MAX 0.70 MAX 0.65 TYP 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF 1.60 1.45 1.30 SEATING PLANE Figure 30. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters 3.20 3.00 2.80 3.20 3.00 2.80 PIN 1 8 5 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8° 0° 0.80 0.60 0.40 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 31. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model SSM2301CPZ-R2 1 SSM2301CPZ-REEL1 SSM2301CPZ-REEL71 SSM2301RMZ-R21 SSM2301RMZ-REEL1 SSM2301RMZ-REEL71 SSM2301-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] Evaluation Board with LFCSP Model Package Option CP-8-2 CP-8-2 CP-8-2 RM-8 RM-8 RM-8 Branding A1C A1C A1C A1C A1C A1C Z = RoHS Compliant Part. Rev. A | Page 14 of 16 SSM2301 NOTES Rev. A | Page 15 of 16 SSM2301 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06163-0-10/07(A) Rev. A | Page 16 of 16