SSM2319

Filterless, High Efficiency, Mono 3 W Class-D Audio Amplifier SSM2319 FEATURES Filterless Class-D amplifier with ultraefficient spreadspectrum Σ-Δ modulation Internal modulator synchronization (SYNC) 3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with 0V OUT+ OUT– VOUT OUTPUT < 0V OUT+ OUT– VOUT +5V 0V +5V 0V +5V 0V POP-AND-CLICK SUPPRESSION Voltage transients at the output of the audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, audible transient sources include system power-up/ power-down, mute/unmute, an input source change, and a sample rate change. The SSM2319 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. +5V 0V +5V 0V 0V –5V 07550-034 Figure 36. 3-Level Σ-Δ Output Modulation With and Without Input Stimulus Rev. 0 | Page 14 of 20 SSM2319 LAYOUT As output power continues to increase, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and to the supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layouts isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more when compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes or analog and digital power planes. POWER SUPPLY DECOUPLING To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality, low ESL, low ESR capacitor, usually of around 4.7 μF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 μF capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2319 helps to maintain efficient performance. SYNCRONIZATION (SYNC) OPERATION SYNC is the feature that allows an external clock signal to control the modulator of the SSM2319. The SSM2319 can act in standalone mode, act as a master device, or act as a slave device. Although the inherent random switching frequency of the Analog Devices patented 3-level PDM modulation virtually eliminates the need for SYNC, this feature can be activated in the event that end users are concerned about clock intermodulation (beating effect) of several amplifiers in close proximity. Another use for the SYNC feature is its ability to adjust modulator frequency to move harmonic interference to a less sensitive frequency band in certain applications with very delicate interference requirements. Although the synchronization frequency operates from 5 MHz to 12 MHz, the optimal operating range is 6 MHz to 9 MHz. Modulator synchronization is initiated after the internal shutdown signal is released. SYNCO buffers the internal oscillator clock with a delay of 127 clock cycles. When synchronizing several SSM2319 amplifiers, configure them in a daisy-chain configuration, as shown in Figure 35. Using this configuration causes a small delay in the SYNCO-toSYNCO transitions of multiple SSM2319s, preventing large surges of instantaneous current and reducing excessive loading of the power supply. When configuring one device to act as a master device, it is mandatory that the connection from SYNCO to SYCNI be less than 1 mm. As in many digital systems, to maintain signal integrity when interfacing several clocking systems, users must insert series dumping resistors close to the SYNCO pin if long trace lengths are used for synchronization connections. A typical value used is 750 Ω. The series dumping resistor should be placed as close to the SYNCO pin as possible. If careful layout practices are followed to minimize signal trace routing from the SYNCO pin of one device to the SYNCI pin of another, a dumping resistor is not necessary. If the SYNC feature is not used, or if the SYNC feature is not interfacing the SYNCO pin to an external device, it is recommended that the SYNCO pin be floated. INPUT CAPACITOR SELECTION The SSM2319 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if using a single-ended source. If highpass filtering is needed at the input, the input capacitor, along with the input resistor of the SSM2319, form a high-pass filter whose corner frequency is determined by fC = 1/{2π × (40 kΩ + REXT) × CIN} The input capacitor can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset of the amplifier and the PSRR performance. Rev. 0 | Page 15 of 20 SSM2319 Operating Modes The SYNC operating modes include the following: • Initial SYNC startup. An internal reference signal, REF, is released after one complete internal clock cycle (MCLK). After REF is released, another internal signal, MOD, waits 127 internal clock cycles. This operates as a training signal to determine the SYNCI/SYNCO connection. During this time, SYNCO is the internal clock signal. SYNCI = GND or VDD. SYNCO stops generating pulses. The modulator is controlled by an internal clock signal, as shown in Figure 37. SD INTERNAL SIGNAL MOD REF • SYNCI = external clock. SYNCO is a buffered clock output sourced from an external clock signal. One clock cycle after the internal modulator detect signal is released, an irregular pulse appears on MCLK before the first buffered output signal begins on SYNCO, as shown in Figure 39. SD INTERNAL REF SIGNAL MOD • SYNCI SYNCO MCLK SYNCI = CLKIN 07550-039 07550-041 CLK LOSS DETECT Figure 39. SYNCI = External Clock • SYNCI SYNCO MCLK SYNCI = GND 07550-037 SYNCI = GND, transitions to clock. When the SYNCI pin is connected to GND first but then transitions to a clock signal, SYNCO generates several internal clock signals before finally being synchronized to the external clock signal, as shown in Figure 40. SD INTERNAL REF SIGNAL MOD SYNCI Figure 37. SYNCI = GND or VDD • SYNCI = SYNCO. SYNCO is the delayed clock signal of SYNCI, as shown in Figure 38. SD INTERNAL REF SIGNAL MOD MCLK SYNCI = GND TO CLKIN Figure 40. SYNCI = GND to Clock Input SYNCI SYNCO MCLK SYNCI = SYNCO 07550-038 • Figure 38. SYNCI = SYNCO SYNCI = CLK, transitions to GND. When SYNCI is connected to a clock signal but then transitions to GND, the SYNCO pin immediately stops generating a clock signal. After a short clock loss detect time, the internal modulator synchronizes to the internal clock signal, as shown in Figure 41. SD INTERNAL REF SIGNAL MOD SYNCI SYNCO MCLK SYNCI = CLKIN TO GND Figure 41. SYNCI = Clock Input to GND Rev. 0 | Page 16 of 20 07550-040 SYNCO SSM2319 OUTLINE DIMENSIONS 1.490 1.460 SQ 1.430 0.655 0.600 0.545 SEATING PLANE 0.350 0.320 0.290 3 2 1 A A1 BALL CORNER B 0.50 BALL PITCH TOP VIEW (BALL SIDE DOWN) C 0.385 0.360 0.335 BOTTOM VIEW 0.270 0.240 0.210 (BALL SIDE UP) Figure 42. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-2) Dimensions shown in millimeters ORDERING GUIDE Model SSM2319CBZ-R2 1 SSM2319CBZ-REEL1 SSM2319CBZ-REEL71 EVAL-SSM2319Z1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board 101507-C Package Option CB-9-2 CB-9-2 CB-9-2 Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 SSM2319 NOTES Rev. 0 | Page 18 of 20 SSM2319 NOTES Rev. 0 | Page 19 of 20 SSM2319 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07550-0-8/08(0) Rev. 0 | Page 20 of 20