High Efficiency, Ground-Referenced
Class-G Headphone Amplifier
SSM2932
Data Sheet
FEATURES
GENERAL DESCRIPTION
Ground-referenced Class-G output stage
Very high efficiency for portable applications
1.7 mA typical quiescent current
50 mW per channel into 16 Ω load (with 3.3 V supply)
98 dB signal-to-noise ratio (SNR), A-weighted
90 dB power supply rejection ratio at 217 Hz
2.5 V to 3.6 V supply range
Selectable gain: 0 dB or 6 dB
High-Z output mode for sharing of output jack
1 μA shutdown current
Short-circuit protection
Pop-and-click reduction circuitry
8 kV ESD protection on output terminals
16-ball, 0.4 mm pitch WLCSP (1.64 mm × 1.64 mm)
−40°C to +85°C operating temperature range
The SSM2932 is a stereo headphone amplifier capable of
delivering 50 mW of continuous output power per channel
into 16 Ω single-ended loads at the 1% THD + N threshold.
The stereo headphone drivers are high efficiency, true groundreferenced Class-G technology.
LE
TE
The SSM2932 incorporates a gain control pin that selects a gain
of 0 dB or 6 dB. The ground-referenced output scheme eliminates
the need for large dc blocking capacitors, reducing system cost
and board area. The Class-G amplifier is fine-tuned to maximize
battery life, a critical task in portable applications. The device
maximizes battery life by modulating the amplifier power supply
rail to match the output demand without consuming excessive
supply current, thus reducing power dissipation during typical
audio playback.
The SSM2932 is specified over the industrial temperature range
of −40°C to +85°C. It has output short-circuit protection as well
as ESD protection to 8 kV (human body model). The SSM2932
is available in a 16-ball, 1.64 mm × 1.64 mm wafer level chip
scale package (WLCSP).
APPLICATIONS
B
SO
Cell phones
Smartphones/multimedia phones
Digital cameras
Portable media players
Phone accessories
PDAs
POR
GAIN
CPVSS
CPVDD
CF2
CF1
GAIN
HI-Z
SD
FUNCTIONAL BLOCK DIAGRAM
POWER
MANAGEMENT
INL+
PGND
OUTR
PGA
SGND
INR+
INR–
OUTL
PGA
SSM2932
POP/
CLICK
CURRENT
LIMIT
10360-001
O
INL–
PVDD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
SSM2932
Data Sheet
TABLE OF CONTENTS
Typical Performance Characteristics ..............................................7
Applications....................................................................................... 1
Theory of Operation ...................................................................... 12
General Description ......................................................................... 1
Amplifier Gain............................................................................ 12
Functional Block Diagram .............................................................. 1
Amplifier Shutdown................................................................... 12
Revision History ............................................................................... 2
High Output Impedance ........................................................... 12
Specifications..................................................................................... 3
Ground Sense.............................................................................. 12
Digital Input Specifications......................................................... 4
Layout .......................................................................................... 12
Absolute Maximum Ratings............................................................ 5
Typical Application Circuit ........................................................... 14
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 15
ESD Caution.................................................................................. 5
Ordering Guide .......................................................................... 15
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
O
B
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LE
2/12—Revision 0: Initial Version
TE
Features .............................................................................................. 1
Rev. 0 | Page 2 of 16
Data Sheet
SSM2932
SPECIFICATIONS
PVDD = 3.0 V, CCF = 1 μF, CCPVDD = CCPVSS = 2.2 μF, RL = 32 Ω, TA = 25°C, unless otherwise noted.
Table 1.
Total Harmonic Distortion Plus Noise
Gain Matching
Frequency Range
Differential Input Impedance
CHARGE PUMP
Oscillator Frequency
Headphone Amplifier Supply
Positive Rail
Negative Rail
AV
Input voltage = 100 mV rms
GAIN pin high
GAIN pin low
f = 1 kHz, THD = 1%
RL = 16 Ω, one channel
RL = 32 Ω, one channel
RL = 16 Ω, stereo
RL = 32 Ω, stereo
PO = 10 mW per channel
PO
THD + N
ΔAV
Ripple within ±0.5 dB
ZIN
fOSC0
fOSC1
VCPVDD
VCPVSS
VTH1
Idle mode, VOUT = 0 V
Active mode
Min
20
12
VTH2
Charge Pump Transition Time
tRELEASE
tATTACK
O
NOISE PERFORMANCE
Output Voltage Noise
Signal-to-Noise Ratio
Pop-and-Click Noise
Channel Separation
OUTPUT CHARACTERISTICS
Output Offset Voltage
Capacitive Output Drive
Slew Rate
STARTUP AND SHUTDOWN
Start-Up Time
Shutdown Time
POWER SUPPLY
Supply Voltage Range
Quiescent Current
Shutdown Current
Power Supply Rejection Ratio
en
SNR
VCP
XTALK
Typ
Max
Unit
6
0
dB
dB
85
50
40
45
0.01
mW
mW
mW
mW
%
%
Hz
kΩ
18
1
20,000
34.5
54
550
kHz
kHz
Efficiency mode: VOUT < 0.2 V rms
High power mode: VOUT > 0.2 V rms
Efficiency mode: VOUT < 0.2 V rms
High power mode: VOUT > 0.2 V rms
Transition from efficiency mode to high
power mode
Transition from high power mode to
efficiency mode
Charge pump transition from high power
mode to efficiency mode
Charge pump transition from efficiency
mode to high power mode
PVDD/2
2.2
−PVDD/2
−2.2
285
V
V
V
V
mV
375
mV
0.8
ms
10
μs
BW = 20 kHz, A-weighted, gain = 0 dB
A-weighted
12
98
−60
86
μV rms
dB
dBV
dB
B
SO
Output Voltage Threshold
Test Conditions/Comments
TE
Output Power
Symbol
LE
Parameter
DEVICE CHARACTERISTICS
Voltage Gain
Single-ended, 1 V rms, PO = 31 mW
|VOS|
CLOAD
SR
150
1.25
0.25
mV
pF
V/μs
20
36
ms
μs
Measured from SD rising edge
tSU
tSD
PVDD
IDD
ISD
PSRR
0°C < TA < 70°C
Guaranteed from PSRR test
RL = 32 Ω + 200 pF; gain = 0 dB, PVDD = 3 V
SD = GND
VRIPPLE = 100 mVPEAK, gain = 0 dB
f = 217 Hz
f = 1 kHz
f = 10 kHz
Rev. 0 | Page 3 of 16
2.5
1.7
1
3.6
V
mA
μA
90
84
62
dB
dB
dB
SSM2932
Data Sheet
DIGITAL INPUT SPECIFICATIONS
Table 2.
Symbol
VIH
VIL
IIN
CIN
Test Conditions/Comments
Min
VIN = 0 V or VDD
Typ
1.2
0.5
Max
±1
5
O
B
SO
LE
TE
Parameter
Input Voltage High
Input Voltage Low
Input Leakage Current
Input Capacitance
Rev. 0 | Page 4 of 16
Unit
V
V
μA
pF
Data Sheet
SSM2932
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
3.75 V
1.8 VPEAK
8 kV
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Table 4. Thermal Resistance
Package Type
16-Ball, 1.64 mm × 1.64 mm WLCSP
ESD CAUTION
O
B
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LE
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TE
Parameter
Analog Supply Voltage (PVDD)
Input Voltage
Output ESD, Human Body Model
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rev. 0 | Page 5 of 16
θJA
66
Unit
°C/W
SSM2932
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
2
1
3
4
SD
PVDD OUTL INL–
PGND
CF1 CPVDD INL+
A
B
CF2 CPVSS SGND INR+
C
HI-Z
GAIN OUTR INR–
10360-002
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
TE
D
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
LE
Description
Shutdown Control
Power Ground
Charge Pump Flying Capacitor, Terminal 2
Output Impedance Select
Power Supply
Charge Pump Flying Capacitor, Terminal 1
Charge Pump Negative Supply
Gain Control
Left Channel Headphone Output
Charge Pump Positive Supply
Headphone Sense Ground
Right Channel Headphone Output
Left Channel Inverting Input
Left Channel Noninverting Input
Right Channel Noninverting Input
Right Channel Inverting Input
B
SO
Mnemonic
SD
PGND
CF2
HI-Z
PVDD
CF1
CPVSS
GAIN
OUTL
CPVDD
SGND
OUTR
INL−
INL+
INR+
INR−
O
Pin No.
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
Rev. 0 | Page 6 of 16
Data Sheet
SSM2932
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
IN PHASE
OUT OF PHASE
10
10
1
1
THD + N (%)
0.1
TE
100
0.001
0.1
10360-003
1
10
OUTPUT POWER PER CHANNEL (mW)
Figure 3. THD + N vs. Output Power, PVDD = 3.6 V, RL = 32 Ω
0.001
0.1
Figure 4. THD + N vs. Output Power, PVDD = 3.0 V, RL = 32 Ω
100
0.1
100
IN PHASE
OUT OF PHASE
O
1
1
THD + N (%)
10
0.1
0.01
0.01
1
10
OUTPUT POWER PER CHANNEL (mW)
100
0.001
0.1
10360-005
THD + N (%)
10
0.001
0.1
100
Figure 7. THD + N vs. Output Power, PVDD = 3.0 V, RL = 16 Ω
IN PHASE
OUT OF PHASE
0.1
1
10
OUTPUT POWER PER CHANNEL (mW)
10360-029
100
1
0.01
10360-030
1
10
OUTPUT POWER PER CHANNEL (mW)
THD + N (%)
1
B
SO
THD + N (%)
IN PHASE
OUT OF PHASE
10
10
0.001
0.1
Figure 6. THD + N vs. Output Power, PVDD = 3.6 V, RL = 16 Ω
LE
IN PHASE
OUT OF PHASE
0.01
100
100
100
0.1
1
10
OUTPUT POWER PER CHANNEL (mW)
10360-004
0.01
0.01
0.001
0.1
0.1
Figure 5. THD + N vs. Output Power, PVDD = 2.5 V, RL = 32 Ω
1
10
OUTPUT POWER PER CHANNEL (mW)
100
Figure 8. THD + N vs. Output Power, PVDD = 2.5 V, RL = 16 Ω
Rev. 0 | Page 7 of 16
10360-006
THD + N (%)
IN PHASE
OUT OF PHASE
SSM2932
Data Sheet
1
1
PO = 5mW
PO = 10mW
PO = 20mW
PO = 5mW
PO = 10mW
PO = 20mW
THD + N (%)
0.1
THD + N (%)
0.1
0.01
1k
FREQUENCY (Hz)
10k
100k
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
TE
100
10360-007
0.001
10
Figure 9. THD + N vs. Frequency, PVDD = 3.6 V, RL = 32 Ω
10360-008
0.01
Figure 12. THD + N vs. Frequency, PVDD = 3.6 V, RL = 16 Ω
1
1
PO = 5mW
PO = 10mW
PO = 20mW
LE
PO = 5mW
PO = 10mW
PO = 20mW
THD + N (%)
0.1
THD + N (%)
0.1
100
1k
FREQUENCY (Hz)
10k
100k
0.001
10
10360-009
0.001
10
Figure 10. THD + N vs. Frequency, PVDD = 2.5 V, RL = 32 Ω
–50
O
100k
LEFT CHANNEL
RIGHT CHANNEL
–60
PSRR (dB)
–80
10k
–50
–70
–80
–90
–100
10
100
1k
FREQUENCY (Hz)
10k
100k
–100
10
Figure 11. PSRR vs. Frequency, PVDD = 3.0 V, RL = 32 Ω
100
1k
FREQUENCY (Hz)
10k
Figure 14. PSRR vs. Frequency, PVDD = 3.0 V, RL = 16 Ω
Rev. 0 | Page 8 of 16
100k
10360-012
–90
10360-011
PSRR (dB)
–70
1k
FREQUENCY (Hz)
Figure 13. THD + N vs. Frequency, PVDD = 2.5 V, RL = 16 Ω
LEFT CHANNEL
RIGHT CHANNEL
–60
100
10360-010
0.01
B
SO
0.01
Data Sheet
SSM2932
210
170
190
TOTAL OUTPUT POWER (mW)
TOTAL OUTPUT POWER (mW)
150
THD + N = 10%
130
110
THD + N = 1%
90
170
THD + N = 10%
150
130
110
THD + N = 1%
90
70
70
2.9
3.1
3.3
SUPPLY VOLTAGE (V)
3.5
30
2.5
Figure 15. Output Power vs. Supply Voltage, RL = 32 Ω
LE
1k
FREQUENCY (Hz)
10k
100k
–95
–100
–105
–110
1M
10M
–60
RIGHT TO LEFT
LEFT TO RIGHT
–65
–70
–75
–80
–85
100
1k
FREQUENCY (Hz)
10k
100k
–95
10
100
1k
FREQUENCY (Hz)
10k
100k
10360-018
–90
10360-017
–115
10
10k
100k
FREQUENCY (Hz)
–55
CHANNEL SEPARATION (dB)
–90
1k
Figure 19. High-Z Mode Output Impedance vs. Frequency
RIGHT TO LEFT
LEFT TO RIGHT
O
CHANNEL SEPARATION (dB)
–85
1k
100
100
Figure 16. Frequency Response, PVDD = 3.0 V
–80
10k
10360-016
IMPEDANCE (Ω)
100
10360-015
B
SO
GAIN (dB)
0
–75
3.5
100k
0.1
–0.2
10
2.9
3.1
3.3
SUPPLY VOLTAGE (V)
Figure 18. Output Power vs. Supply Voltage, RL = 16 Ω
0.2
–0.1
2.7
TE
2.7
10360-013
50
2.5
10360-014
50
Figure 20. Channel Separation vs. Frequency, PVDD = 3.0 V, RL = 16 Ω
Figure 17. Channel Separation vs. Frequency, PVDD = 3.0 V, RL = 32 Ω
Rev. 0 | Page 9 of 16
SSM2932
Data Sheet
250
350
POWER CONSUMPTION (mW)
POWER CONSUMPTION (mW)
300
200
150
100
50
250
200
150
100
20
40
60
TOTAL OUTPUT POWER (mW)
80
100
0
Figure 21. Power Consumption vs. Output Power, PVDD = 3.0 V, RL = 32 Ω
80
100
LE
60
40
0
20
40
60
TOTAL OUTPUT POWER (mW)
80
100
Figure 22. Power Dissipation vs. Output Power, PVDD = 3.0 V, RL = 32 Ω
100
150
100
50
0
10360-021
20
200
0
20
40
60
TOTAL OUTPUT POWER (mW)
80
100
10360-023
80
POWER DISSIPATION (mW)
100
B
SO
Figure 25. Power Dissipation vs. Output Power, PVDD = 3.0 V, RL = 16 Ω
1.72
O
PVDD = 2.5V
PVDD = 3.3V
10
1.70
QUIESCENT CURRENT (mA)
RL = 32Ω
RL = 16Ω
1.68
1.66
1.64
1.62
100
LOAD RESISTANCE (Ω)
1k
1.60
2.5
10360-024
1
10
Figure 23. Maximum Output Power per Channel vs. Load Resistance,
Flying Capacitor = 1 μF, THD + N = 1%
Rev. 0 | Page 10 of 16
2.7
2.9
3.1
3.3
SUPPLY VOLTAGE (V)
Figure 26. Quiescent Current vs. Supply Voltage
3.5
10360-019
POWER DISSIPATION (mW)
40
60
TOTAL OUTPUT POWER (mW)
250
120
OUTPUT POWER PER CHANNEL (mW)
20
Figure 24. Power Consumption vs. Output Power, PVDD = 3.0 V, RL = 16 Ω
140
0
0
TE
0
10360-020
0
10360-022
50
Data Sheet
SSM2932
1 500mV/ 2 1.00V/ 3
4
20.00ms 5.00ms Trig’d?
1 1.00V/ 2 1.00V/ 3
2 1.75V
4
1.520ms 2.000ms Trig’d?
1 1.01V
T
T
1, 2
TE
10360-026
10360-027
1, 2
Figure 27. Start-Up Waveform vs. Time
Figure 29. Shutdown Waveform vs. Time
0
–20
LE
–60
–80
–100
–120
–160
–180
10
100
1k
FREQUENCY (Hz)
10k
100k
10360-028
–140
B
SO
OUTPUT (dBV)
–40
O
Figure 28. Output Spectrum vs. Frequency, PVDD = 3.0 V, RL = 32 Ω
Rev. 0 | Page 11 of 16
SSM2932
Data Sheet
THEORY OF OPERATION
The headphone amplifier uses Class-G architecture and generates
the required power supplies with a built-in charge pump that uses a
flying capacitor connected across CF1 (Ball B2) and CF2 (Ball C1).
The charge pump switching frequency is approximately 54 kHz
in the idle state with no input signal detected and 550 kHz when a
signal is present. The generated supply voltages are available at
CPVDD (Ball B3, positive rail) and CPVSS (Ball C2, negative rail).
Shutdown of the SSM2932 amplifier is controlled by the SD pin.
If a logic low is applied to this pin, the amplifier becomes inactive
and draws only minimal current from the supply.
Table 7. Amplifier Shutdown
Amplifier State
Shutdown
Power-On
SD Pin Logic Level
Low (≤0.5 V)
High (≥1.2 V)
HIGH OUTPUT IMPEDANCE
The SSM2932 has a HI-Z control pin that mutes the amplifier
and sets the output to a high impedance. If both HI-Z and SD
are set high, the amplifier remains in a high impedance state.
This feature allows the headphone output jack to be shared for
other functions such as video output or data transmission.
GROUND SENSE
LE
The supply voltage of the headphone amplifier depends on the
input signal to the amplifier. For lower input signal levels, the
positive and negative rails are lowered, typically to ±PVDD/2.
As the signal level increases, CPVDD and CPVSS are raised to
±2.2 V. This rail switching allows the amplifier to achieve higher
efficiency.
AMPLIFIER SHUTDOWN
TE
The SSM2932 provides a high efficiency Class-G stereo headphone output that is true ground-referenced; therefore, no
external coupling capacitors are required for connection to the
headphones. The headphones can be connected directly to the
headphone output pins, OUTL (Ball A3) and OUTR (Ball D3).
The headphone amplifier uses the supply provided at PVDD
(Ball A2). This supply voltage must be decoupled with a 1 μF
electrolytic capacitor, along with a 100 nF ceramic X7R capacitor.
B
SO
In most typical usage conditions, the amplifier works on
the lower CPVDD and CPVSS voltages (±PVDD/2), thereby
consuming less power. In addition, because the amplifier
generates the positive and negative rails, the output amplifier
is true ground-referenced, thereby eliminating the need for
large coupling capacitors to drive the load.
SGND (Ball C3) is provided for sensing the dc potential at the
headphone jack. It is recommended that SGND be connected
directly to the ground pin of the headphone jack to ensure the
lowest dc offset at the amplifier output and to eliminate pop-andclick noises when the amplifier is turned on or off. In addition,
connecting the SGND ball directly to the ground pin of the headphone jack helps to reduce crosstalk between the left and right
channel outputs. A dc path between the SGND pin and the
system ground must also be provided.
For best audio performance, it is recommended that 2.2 μF,
X7R ceramic decoupling capacitors be used for CPVDD and
CPVSS. These capacitors serve as a reservoir for the headphone
amplifier.
The headphone amplifier has built-in short-circuit protection
and, therefore, shuts down in the event of a short circuit on
the headphone outputs.
O
The amplifier is designed to drive headphones with a minimum impedance of 16 Ω. Capacitive loads of up to 150 pF
are supported.
AMPLIFIER GAIN
The SSM2932 amplifier gain can be set to either 0 dB or 6 dB
by applying the appropriate logic level to the GAIN pin (see
Table 6).
Table 6. Amplifier Gain and GAIN Pin Logic Levels
Amplifier Gain
0 dB
6 dB
GAIN Pin Logic Level
Low (≤0.5 V)
High (≥1.2 V)
LAYOUT
Care must be taken to lay out PCB traces and wires properly
between the amplifier, load, and power supply. A good practice
is to use short, wide PCB tracks to decrease voltage drops and
minimize inductance. Ensure that track widths are at least 200 mil
per inch of track length for lowest DCR, and use at least 1 oz
or 2 oz copper thickness to minimize resistance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs
to minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent
switching noise from coupling into the audio signal. The PCB
traces that connect the output pins to the load, as well as the
PCB traces to the supply pins, should be as wide as possible to
maintain the minimum trace resistances. It is also recommended
that a large ground plane be used for minimum impedances.
The SGND pin should be connected directly to the ground pin
of the headphone jack.
Rev. 0 | Page 12 of 16
Data Sheet
SSM2932
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
O
B
SO
LE
TE
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be directly beneath the
analog power plane, and, similarly, the digital ground plane should
be directly beneath the digital power plane. There should be no
overlap between analog and digital ground planes or between
analog and digital power planes.
Rev. 0 | Page 13 of 16
SSM2932
Data Sheet
TYPICAL APPLICATION CIRCUIT
2.2µF
2.2µF
POR
GAIN
CPVSS
CPVDD
HI-Z GAIN
CF2
SD
CF1
1µF
POWER
MANAGEMENT
100nF
PVDD
1µF
PGND
0.1µF
INL+
INL–
SGND
0.1µF
INR+
0.1µF
TE
OUTR
PGA
PHONE
JACK
OUTL
PGA
INR–
SSM2932
CURRENT
LIMIT
LE
POP/
CLICK
O
B
SO
Figure 30. Application Circuit (Differential Input Configuration)
Rev. 0 | Page 14 of 16
10360-031
0.1µF
Data Sheet
SSM2932
OUTLINE DIMENSIONS
1.680
1.640 SQ
1.600
4
3
2
1
A
BALL A1
IDENTIFIER
B
1.20
REF
C
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
SIDE VIEW
COPLANARITY
0.05
0.300
0.260
0.220
0.230
0.200
0.170
LE
SEATING
PLANE
02-03-2012-A
0.560
0.500
0.440
D
TE
TOP VIEW
0.40
REF
Figure 31. 16-Ball Wafer Level Chip Scale Package [WLCSP]
1.6 mm × 1.6 mm Body
(CB-16-11)
Dimensions shown in millimeters
B
SO
ORDERING GUIDE
Model 1
SSM2932ACBZ-RL
SSM2932ACBZ-R7
EVAL-SSM2932Z
Package Description
16-Ball Wafer Level Chip Scale Package [WLCSP]
16-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
Z = RoHS Compliant Part.
O
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Rev. 0 | Page 15 of 16
Package Option
CB-16-11
CB-16-11
SSM2932
Data Sheet
O
B
SO
LE
TE
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10360-0-2/12(0)
Rev. 0 | Page 16 of 16
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