SSM3302ACPZ-R7

2 ×10 W Filterless Class-D Stereo Audio Amplifier SSM3302 Data Sheet FEATURES Filterless stereo Class-D amplifier with Σ-Δ modulation 2 × 10 W into 4 Ω load and 2 × 8 W into 8 Ω load at 12 V supply with 0V OUTR+/ OUTL+ and minimum inductance, ensure that track widths are at least 200 mil for every inch of length and use 1 oz. or 2 oz. copper. Use large traces for the power supply inputs and amplifier outputs. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. 0V +5V OUTR–/ OUTL– fC = 1/(2π × RIN × CIN) 0V VOUT –5V 10198-036 0V Figure 39. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus The input capacitor can significantly affect the performance of the circuit. Failure to use input capacitors degrades the output offset of the amplifier. BOOTSTRAP CAPACITORS LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. For lowest DCR The output stage of the SSM3302 uses a high-side NMOS driver, rather than PMOS driver. To generate the gate drive voltage for the high-side NMOS driver, a bootstrap capacitor for each output terminal acts as a floating power supply for the switching cycle. Using 0.22 μF ceramic capacitors with a voltage rating of 35 V or greater is recommended. Rev. A | Page 17 of 20 SSM3302 Data Sheet POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion, and high power supply rejection ratio, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. Decouple the power supply input with a good quality, low ESL, low ESR bulk capacitor larger than 220 µF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, place two separate 1 µF capacitors as close as possible to the PVDD pins of the device. Connect one of the 1 µF capacitors between the left-side PVDD terminals and PGND terminals, and connect the other 1 µF capacitor between the right-side PVDD terminals and PGND terminals. Placing the decoupling capacitor as close as possible to the SSM3302 helps to achieve the best performance. Rev. A | Page 18 of 20 Data Sheet SSM3302 OUTLINE DIMENSIONS 0.30 0.23 0.18 31 40 30 0.50 BSC 1 0.80 0.75 0.70 0.45 0.40 0.35 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.45 4.30 SQ 4.25 EXPOSED PAD 21 TOP VIEW PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 40. 40-Lead Lead Free Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-10) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM3302ACPZ SSM3302ACPZ-RL SSM3302ACPZ-R7 EVAL-SSM3302Z 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 40-Lead Lead Free Chip Scale Package [LFCSP_WQ] 40-Lead Lead Free Chip Scale Package [LFCSP_WQ] 40-Lead Lead Free Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 19 of 20 Package Option CP-40-10 CP-40-10 CP-40-10 SSM3302 Data Sheet NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10198-0-5/13(A) Rev. A | Page 20 of 20