SSM3582BCPZR7

2×, 31.76 W, Digital Input, Filterless Stereo Class-D Audio Amplifier SSM3582 Data Sheet FEATURES Supported sample rates from 8 kHz to 192 kHz; 24-bit resolution Multiple PCM audio serial data formats TDM slave with support for up to 16 devices on a single bus I2S or left justified slave Adjustable full-scale output tailored for many PVDD sources 2- and 3-cell Li-Ion batteries Digital volume control with selectable smooth ramp Automatic power-down function Supply monitoring automatic gain control (AGC) function reduces system brownout Standalone operational mode without I2C Temperature sensor with 1°C step readout via I2C Short-circuit, undervoltage, and thermal protection Thermal early warning Power-on reset PVDD sensing ADC 40-lead, 6 mm × 6 mm LFCSP with thermal pad Digital input stereo, high efficiency Class-D amplifier Operates from a single 4.5 V to 16 V supply State-of-the-art, proprietary, filterless Σ-Δ modulation 106.5 dB signal-to-noise ratio 0.004% total harmonic distortion plus noise (THD + N) at 5 W into 8 Ω 38.5 µV rms A weighted output noise Pop/clickless on/off sequence 2× 14.67 W output at 12 V supply to 4 Ω loads at 145°C Die temperature > 117°C Battery voltage PVDD > VBAT_INF_L Battery voltage PVDD > VBAT_INF_R FAULTS AND LIMITER STATUS REPORTING The SSM3582 offers comprehensive protections against the faults at the outputs and reporting to help with system design. The faults listed in Table 20 are reported using the status registers. The faults listed in Table 20 are reported in Register 0x18 and Register 0x19 and can be read via I2C by the microcontroller in the system. In the event of a fault occurrence, use Register 0x0B to control how the device reacts to the faults. Table 21. Register 0x16, Register 0x17, Fault Recovery Fault Type OTW Manual Recovery Autorecovery Attempts UV Die OT OC Flag Set Condition The amount of gain reduction applied if there is an OTW for left channel The amount of gain reduction applied if there is an OTW for the right channel Use to attempt manual recovery in case of a fault event When autorecovery from faults is used, set the number of attempts using this bit Recovery can be automatic or manual Recovery can be automatic or manual Recovery can be automatic or manual Status Reported Register Register 0x16, Bits[1:0], OTW_ GAIN_L Register 0x16, Bits[5:4], OTW_ GAIN_R Register 0x17, Bit 7, MRCV Register 0x17, Bits[5:4], MAX_AR Register 0x17, Bit 2, ARCV_UV Register 0x17, Bit 1, ARCV_OT Register 0x17, Bit 0, ARCV_OC When the automatic recovery mode is set, the device attempts to recover itself after the fault event and, in case the fault persists, then the device sets the fault again. This process repeats until the fault is resolved. Status Reported Register Register 0x18, Bit 7, UVLO_PVDD Register 0x18, Bit 6, UVLO_VREG Register 0x19, Bit 3, LIM_EG_L Register 0x19, Bit 7, LIM_EG_R Register 0x19, Bit 2, CLIP_L Register 0x19, Bit 6, CLIP_R Register 0x19, Bit 1, AMP_OC_L Register 0x19, Bit 5, AMP_OC_R Register 0x18, Bit 1, OTF Register 0x18, Bit 0, OTW Register 0x19, Bit 0, BAT_WARN_L Register 0x19, Bit 4, BAT_WARN_R When the manual recovery mode is used, the device shuts down and the recovery must be attempted using the system microcontroller. VBAT (PVDD) SENSING The SSM3582 contains an 8-bit ADC that measures the voltage of the battery voltage (VBAT/PVDD) supply. The battery voltage information is stored in Register 0x1A as an 8-bit unsigned format. The ADC input range is fixed internally at 3.8 V to 16.2 V. To convert the hexadecimal value to the voltage value, use the following steps: Convert the hexadecimal value to decimal. For example, if the hexadecimal value is 0xA9, the decimal value is 169. Calculate the voltage using the following equation: Voltage = 3.8 V + 12.4 V × Decimal Value/255 With a decimal value of 169, Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V LIMITER AND BATTERY TRACKING THRESHOLD CONTROL The SSM3582 contains an output limiter that can be used to limit the peak output voltage of the amplifier. The limiter works on the rms and peak value of the signal. The limiter threshold, slope, attack rate, and release rate are programmable using Register 0x0E, Register 0x0F, and Register 0x10 for the left channel and Register 0x11, Register 0x12, Register 0x13 for the right channel. The limiter can be enabled or disabled using LIM_EN_L, Bits[1:0] in Register 0x0E, Bits[1:0] for the left channel and the LIM_EN_R bits, Bits[1:0] in Register 0x11, for the right channel. The threshold at which the output is limited is determined by the LIM_THRES_L bits setting, Bits[7:3] in Register 0x0F for the left channel, and the LIM_THRES_R bits setting, Bits[7:3] in Register 0x12 for the right channel. When the ouput signal level exceeds the set threshold level, the limiter activates and limits the signal level to the set limit. Below the set threshold, the output level is not affected. Rev. A| Page 32 of 59 Data Sheet SSM3582 When set to a variable threshold, the SSM3582 monitors the VBAT supply and automatically adjusts the limiter threshold based on the VBAT supply voltage. The VBAT supply voltage at which the limiter begins to decrease the output level is determined by the VBAT inflection point (the VBAT_INF _L bits (Register 0x10, Bits[7:0]) for the left channel and VBAT_INF_R bits (Register 0x13, Bits[7:0]) for the right channel). When LIM_EN_x = 01, the limiter is enabled. When LIM_EN_x = 10, the limiter mutes the output if VBAT falls below VBAT_INF_x. When LIM_EN_x = 11, the limiter engages only when the battery voltage is lower than VBAT_INF_x. When VBAT is greater than VBAT_INF_x, no limiting occurs. Note that there is hysteresis on VBAT_INF_x for the limiter disengaging. The limiter, when active, reduces the gain of the amplifier. The rate of gain reduction or attack rate is determined by the LIM_ATR_ x bits (Register 0x0E and Register 0x11, Bits[5:4]). Similarly, when the signal level drops below the limiter threshold, the gain is restored. The gain release rate is determined by the LIM_RRT bits (Register 0x0E and Register 0x11, Bits[7:6]). LIM_EN_x = 00 VBAT_TRACK_x = 0 AMPLIFIER CLIPPING LEVEL The VBAT_INF_x point is defined as the battery voltage at which the limiter either activates or deactivates depending on the LIM_EN_x mode (see Table 22). When the battery voltage is greater than VBAT_INF_x, the limiter is not active. When the battery voltage is less than VBAT_INF_X, the limiter is activated. The VBAT_INF_x bits can be set from 3.8 V to 16.2 V. The 8-bit value for the voltage can be calculated using the following equation: INPUT LEVEL Voltage = 3.8 + 12.4 × Decimal Value/255 13399-076 The limiter threshold can be set as fixed or to vary with the battery voltage via the VBAT_TRACK_L bit (Register 0x0E, Bit 2) for the left channel and VBAT_TRACK_R bit (Register 0x11, Bit 2) for right channel. When set to fixed, the limiter threshold is fixed and does not vary with battery voltage. The threshold can be set from 2 V peak to 16 V peak using the LIM_THRES_x bit (see Figure 77). The limiter offers various active modes that can be set using the LIM_EN_x bits (Register 0x0E and Register 0x11, Bits[1:0]) and the VBAT_TRACK_x bit, as shown in Table 22. PEAK OUTPUT LEVEL The limiter threshold can be set above the maximum output voltage of the amplifier. In this case, the limiter allows maximum peak output; in other words, the output may clip depending on the power supply voltage and not the limiter. Figure 76. Limiter Example (LIM_EN_x = 0b0, VBAT_TRACK_x = 0bX) Convert the decimal value to an 8-bit hexadecimal value and use it to set the VBAT_INF_x bits. The slope bits (Register 0x0F and Register 0x12, Bits[1:0]) determine the rate at which the limiter threshold is lowered relative to the amount of change in VBAT below the VBAT_INF_x point. LIMITER THRESHOLD FIXED AT SET VALUE AND DOES NOT TRACK VBAT LIMITER THRESHOLD LIM_THRES_x The slope is the ratio of the limiter threshold reduction to the VBAT voltage reduction. The slope ratio can be set from 1:1 to 4:1. This function is useful to prevent early shutdown under low battery conditions. As the VBAT voltage falls, the limiter threshold is lowered. This lower threshold results in the lower output level and therefore helps to reduce the current drawn from the battery and in turn helps prevent early shutdown due to low VBAT. VBAT Figure 77. Limiter Fixed (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b0) Table 22. Limiter Modes LIM_EN_x 00 01 01 10 11 11 VBAT_TRACK_x 0 or 1 0 1 0 or 1 0 1 Limiter No Fixed Variable Fixed Fixed Variable VBAT < VBAT_INF_x Not applicable Use the set threshold Lowers the threshold Mutes the output Use the set threshold Lowers the threshold VBAT > VBAT_INF_x Not applicable Use the set threshold Use the set threshold Use the set threshold No limiting No limiting Rev. A| Page 33 of 59 Comments See Figure 76 See Figure 77 See Figure 78 and Figure 79 Not shown See Figure 80 and Figure 81 See Figure 82 and Figure 83 13399-077 Slope = ΔLimiter Threshold/ΔVBAT SSM3582 Data Sheet LIM_EN_x = 01 VBAT_TRACK_x = 1 LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF_x 13399-078 CHANGE IN LIM THRESHOLD = N × (VBAT_INF_x – VBAT) WHERE N = 1 TO 4, SET USING SLOPE BITS IN REG 0x0F, REG 0x12 INPUT LEVEL VBAT Figure 81. Limiter Fixed (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b0) Figure 78. Limiter Fixed (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b1) LIM_EN_x = 11 VBAT_TRACK_x = 1 LIMITER THRESHOLD STAYS AT THE SET VALUE FOR VBAT > VBAT_INF_x VBAT > VBAT_INF_x LIMITER IS NOT ACTIVE AMPLIFIER CLIPPING LEVEL VBAT_INF_x PEAK OUTPUT LEVEL LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF CHANGE IN LIM THRESHOLD = N × (VBAT_INF_x – VBAT) WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x0F, REG 0x12 VBAT Figure 79. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b1) INPUT LEVEL Figure 82. Limiter Example (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b1) LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF_x SET LIM_THRES_x LIMITER THRESHOLD AMPLIFIER CLIPPING LEVEL LIMITER THRESHOLD SETTING NO CHANGE IN LIM THRESHOLD PER VBAT VBAT_INF_x SLOPE LIMITER THRESHOLD LOWERS FOR VBAT < VBAT_INF_x INPUT LEVEL 13399-080 VBAT 13399-083 LIM_EN_x = 11 VBAT_TRACK_x = 0 PEAK OUTPUT LEVEL 13399-082 LIMITER THRESHOLD LOWERS FOR VBAT < VBAT_INF_x LIMITER THRESHOLD SETTING 13399-079 LIMITER THRESHOLD LIM_THRES_x SLOPE 13399-081 LIMITER THRESHOLD VBAT > VBAT_INF_x LIMITER LIMITER THRESHOLD SETTING PEAK OUTPUT LEVEL LIMITER THRESHOLD FIXED AT SET VALUE AND DOES NOT TRACK VBAT LIM_THRES_x Figure 83. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b1) Figure 80. Limiter Example (LIM_EN_x = 0b11, VBAT_TRACK_x = 0) Rev. A| Page 34 of 59 Data Sheet SSM3582 HIGH FREQUENCY CLIPPER OUTPUT MODULATION DESCRIPTION The high frequency clipper can be controlled via the DAC_CLIP_L bits (Register 0x14, Bits[7:0]) and the DACL_CLIP_R bits (Register 0x15, Bits[7:0]). The SSM3582 uses three level, Σ-Δ output modulation. Each output can swing from ground to PVDD, and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. These bits determine the clipper threshold, relative to full scale. When enabled, the clipper digitally clips the signal after the DAC interpolation. EMI NOISE The SSM3582 uses a proprietary modulation and spread spectrum technology to minimize EMI emissions from the device. The SSM3582 passes FCC Class-B emissions testing with an unshielded 20 inch cable using ferrite bead-based filtering. For applications that have difficulty passing FCC Class-B emission tests, the SSM3582 includes an ultralow EMI emissions mode that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. Note that reducing the supply voltage greatly reduces radiated emissions. Due to this constant presence of noise, a differential pulse is occasionally generated in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. However, typically, the output differential voltage is 0 V. This feature ensures that the current flowing through the inductive load is small. When the user sends an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 84 depicts three-level, Σ-Δ output modulation with and without input stimulus. OUTPUT = 0V +5V OUTx+ 0V +5V OUTx– 0V +5V VOUT 0V –5V OUTPUT > 0V +5V OUTx+ 0V +5V OUTx– 0V +5V VOUT 0V OUTPUT < 0V +5V OUTx+ 0V +5V OUTx– 0V VOUT –5V 13399-074 0V Figure 84. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus Rev. A| Page 35 of 59 SSM3582 Data Sheet BOOTSTRAP CAPACITORS OUTPUT EMI FILTERING The output stage of the SSM3582 uses a high-side NMOS driver, rather than a PMOS driver. To generate the gate drive voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating power supply for the switching cycle. Use 0.22 μF capacitors to connect the appropriate output pin (OUTx±) to the bootstrap pin (BSTx±). For example, connect a 0.22 μF capacitor between OUTL+ (a left channel, noninverting output) and BSTL+ for bootstrapping the left channel. Similarly, connect another 0.22 μF capacitor between the OUTL− and BSTL− pins for the left channel inverting output. Additional EMI filtering may be required when the speaker traces and cables are long and present a significant capacitive load that can create additional draw from the amplifier. Typical power ferrites present a significant magnetic hysteresis cycle that affects THD performance and are not recommended for high performance designs. The NFZ filter series from Murata, designed in close collaboration with Analog Devices, Inc., provides a closed hysteresis loop similar to an air coil with minimum impact on performance. Products are available at upwards of 4 A rms, well suited to this application. A small capacitor can be added between the output of the filter and ground to further attenuate very high frequencies. Take care to ensure the capacitor is properly sized so as not to affect idle power consumption or efficiency. POWER SUPPLY DECOUPLING To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR bulk capacitor larger than 220 µF. This capacitor bypasses low frequency noise to the ground plane. For high frequency decoupling, place 1 µF capacitors as close as possible to the PVDD pins of the device. BSTL+ 0.22µF CAPACITOR PCB PLACEMENT Component selection and placement have great influence on system performance, both measured and subjective. Proper PVDD layout and decoupling is necessary to reach the specified level of performance, particularly at the highest power levels. The placement shown in Figure 85 ensures proper output stage decoupling for each channel, for minimum supply noise and maximum separation between channels. Additional bulk decoupling is necessary to reduce current ripple at low frequencies, and can be shared between several amplifiers in a multichannel solution. PVDD DECOUPLING 0.1µF CAPACITOR BSTL– 0.22µF CAPACITOR DVDD DECOUPLING 0.1µF CAPACITOR BSTR+ 0.22µF CAPACITOR BSTR– 0.22µF CAPACITOR PVDD DECOUPLING 0.1µF CAPACITOR Figure 85. Recommended Component Placement Rev. A| Page 36 of 59 13399-075 AVDD DECOUPLING 0.1µF CAPACITOR Data Sheet SSM3582 LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. For the lowest dc resistance (DCR) and minimum inductance, ensure that track widths for the outputs are at least 200 mil for every inch of length and use 1 oz. or 2 oz. copper. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins must be as wide as possible; this also maintains the minimum trace resistances. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emission and increase immunity to the RF field by a factor of 10 or more, compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane must be directly beneath the analog power plane, and, similarly, the digital ground plane must be directly beneath the digital power plane. There must be no overlap between the analog and digital ground planes or between the analog and digital power planes. PVDD and PGND carry most of the device current, and must be properly decoupled with multiple capacitors at the device pins. To minimize ground bounce, use independent large traces to carry PVDD and PGND to the power supply, thus reducing the amount of noise the amplifier bridges inject in the circuit, particularly if common ground impedance is significant. Proper grounding guidelines help improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. Rev. A| Page 37 of 59 SSM3582 Data Sheet REGISTER SUMMARY Table 23. Register Summary Reg 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C Name VENDOR_ID DEVICE_ID1 DEVICE_ID2 REVISION POWER_CTRL AMP_DAC_CTRL DAC_CTRL VOL_LEFT_CTRL VOL_RIGHT_CTRL SAI_CTRL1 SAI_CTRL2 SLOT_LEFT_CTRL SLOT_RIGHT_CTRL LIM_LEFT_CTRL1 LIM_LEFT_CTRL2 LIM_LEFT_CTRL3 LIM_RIGHT_CTRL1 LIM_RIGHT_CTRL2 LIM_RIGHT_CTRL3 CLIP_LEFT_CTRL CLIP_RIGHT_CTRL FAULT_CTRL1 FAULT_CTRL2 STATUS1 STATUS2 VBAT TEMP SOFT_RESET Bits [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 APWDN_EN DAC_LPM DAC_HV RESERVED RESERVED DAC_MUTE_R TEMP_PWDN DAC_POL_R DAC_MUTE_L RESERVED SDATA_EDGE Bit 3 VENDOR DEVICE1 DEVICE2 REV MONO R_PWDN DAC_POL_L EDGE DAC_HPF RESERVED VOL_L VOL_R TDM_BCLKS DATA_WIDTH VOL_ZC_ONLY BCLK_POL RESERVED RESERVED RESERVED LIM_RRT_L LIM_ATR_L LIM_THRES_L LIM_RRT_R LIM_ATR_R LIM_THRES_R RESERVED VBAT_INF_L LIM_LINK Bit 2 Bit 1 L_PWDN RESERVED RESERVED SPWDN ANA_GAIN DAC_FS FSYNC_MODE CLIP_LINK TDM_SLOT_L TDM_SLOT_R VBAT_TRACK_L RESERVED SDATA_FMT VOL_LINK VBAT_TRACK_R RESERVED Bit 0 SAI_MODE AUTO_SLOT LIM_EN_L SLOPE_L LIM_EN_R SLOPE_R VBAT_INF_R DAC_CLIP_L DAC_CLIP_R RESERVED MRCV RESERVED UVLO_PVDD UVLO_VREG LIM_EG_R CLIP_R OTW_GAIN_R MAX_AR AMP_OC_R RESERVED RESERVED BAT_WARN_R LIM_EG_L VBAT TEMP RESERVED Rev. A| Page 38 of 59 RESERVED ARCV_UV CLIP_L OTW_GAIN_L ARCV_OT ARCV_OC OTF OTW AMP_OC_L BAT_WARN_L S_RST Reset 0x41 0x35 0x82 0x01 0xA1 0x8A 0x02 0x40 0x40 0x11 0x07 0x00 0x01 0xA0 0x51 0x22 0xA8 0x51 0x22 0xFF 0xFF 0x00 0x30 0x00 0x00 0x00 0x00 0x00 RW R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W Data Sheet SSM3582 REGISTER DETAILS Address: 0x00, Reset: 0x41, Name: VENDOR_ID 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 [7:0] VENDOR (R) Vendor ID Table 24. Bit Descriptions for VENDOR_ID Bits Bit Name [7:0] VENDOR Settings Description Reset Access Vendor ID 0x41 R Description Reset Access Device ID 1 0x35 R Description Reset Access Device ID 2 0x82 R Description Reset Access Revision Code 0x1 R Address: 0x01, Reset: 0x35, Name: DEVICE_ID1 7 6 5 4 3 2 1 0 0 0 1 1 0 1 0 1 [7:0] DEVICE1 (R) Device ID 1 Table 25. Bit Descriptions for DEVICE_ID1 Bits Bit Name [7:0] DEVICE1 Settings Address: 0x02, Reset: 0x82, Name: DEVICE_ID2 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 0 [7:0] DEVICE2 (R) Device ID 2 Table 26. Bit Descriptions for DEVICE_ID2 Bits Bit Name [7:0] DEVICE2 Settings Address: 0x03, Reset: 0x01, Name: REVISION 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:0] REV (R) Revision Code Table 27. Bit Descriptions for REVISION Bits Bit Name [7:0] REV Settings Rev. A| Page 39 of 59 SSM3582 Data Sheet Address: 0x04, Reset: 0xA1, Name: POWER_CTRL 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 1 [7] APWDN_EN (R/W) Auto Power-Down Enable 0: Auto Power-Down Feature Disabled. 1: Auto Power-Down Feature Enabled. [0] SPWDN (R/W) Software Master Power-Down 0: Norm al Operation. 1: Software Master Power-Down. [6] RESERVED [1] RESERVED [5] TEMP_PWDN (R/W) Tem perature Sensor Power-down 0: Tem perature Sensor On. 1: Tem perature Sensor Powered Down. [2] L_PWDN (R/W) Left Channel Power-Down 0: Left Channel Powered on. 1: Left Channel Powered Down. [4] MONO (R/W) Mono Mode Selection 0: Stereo Mode Enabled. 1: Mono Mode Enabled. [3] R_PWDN (R/W) Right Channel Power-Down 0: Right Channel Powered On. 1: Right Channel Powered Down. Table 28. Bit Descriptions for POWER_CTRL Bits 7 Bit Name APWDN_EN Settings 0 1 6 5 RESERVED TEMP_PWDN 0 1 4 MONO 0 1 3 R_PWDN 0 1 2 L_PWDN 0 1 1 0 RESERVED SPWDN 0 1 Description Automatic Power-Down Enable. Automatic power-down feature disabled. Automatic power-down feature enabled. Reserved. Temperature Sensor Power-Down. Temperature sensor on. Temperature sensor powered down. Mono Mode Selection. Stereo mode enabled. Mono mode enabled. Left Channel Power-Down. Right channel powered on. Right channel powered down. Left Channel Power-Down. Left channel powered on. Left channel powered down. Reserved. Software Master Power-Down Normal operation. Software master power-down. Rev. A| Page 40 of 59 Reset 0x1 Access R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x1 R R/W Data Sheet SSM3582 Address: 0x05, Reset: 0x8A, Name: AMP_DAC_CTRL 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 0 [7] DAC_LPM (R/W) DAC low power m ode 0: DAC Low Power Mode Disabled. 1: DAC Low Power Mode Enabled. [6] RESERVED [5] DAC_POL_R (R/W) Right Channel DAC output polarity control 0: Norm al behavior. 1: Invert the DAC output. [1:0] ANA_GAIN (R/W) Am plifier analog gain select 0: +13dB (6.3 V peak) 1: +16 dB (8.9 V peak) 10: +19 dB (12.6 V peak) 11: +21 dB (16 V peak) [2] RESERVED [3] EDGE (R/W) Edge rate control 0: Norm al operation. 1: Low EMI m ode operation. [4] DAC_POL_L (R/W) Left Channel DAC output polarity control 0: Norm al behavior. 1: Invert the DAC output. Table 29. Bit Descriptions for AMP_DAC_CTRL Bits Bit Name 7 DAC_LPM Settings Description Reset Access DAC Low Power Mode. 0x1 R/W 0 DAC low power mode disabled. 1 DAC low power mode enabled. 6 RESERVED Reserved. 0x0 R 5 DAC_POL_R Right Channel DAC Output Polarity Control. 0x0 R/W 0x0 R/W 0x1 R/W 4 3 0 Normal behavior. 1 Invert the DAC output. DAC_POL_L Left Channel DAC Output Polarity Control. 0 Normal behavior. 1 Invert the DAC output. EDGE Edge Rate Control. 0 Normal operation. 1 Low EMI mode operation. 2 RESERVED Reserved. 0x0 R [1:0] ANA_GAIN Amplifier Analog Gain Select. 0x2 R/W 0 +13 dB (6.3 V peak). 1 +16 dB (8.9 V peak). 10 +19 dB (12.6 V peak). 11 +21 dB (16 V peak). Rev. A| Page 41 of 59 SSM3582 Data Sheet Address: 0x06, Reset: 0x02, Name: DAC_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [7] DAC_HV (R/W) Hard volum e control 0: Soft volum e ram ping. 1: No volum e ram ping. [2:0] DAC_FS (R/W) DAC sam ple rate select 0: 8kHz to 12 kHz. 1: 16kHz to 24 kHz. 10: 32kHz to 48 kHz. 11: 64kHz to 96 kHz. 100: 128kHz to 192 kHz. 101: 48kHz to 72 kHz. [6] DAC_MUTE_R (R/W) DAC right channel m ute 0: Right channel unm uted. 1: Right channel m uted. [3] RESERVED [5] DAC_MUTE_L (R/W) DAC left channel m ute 0: Left channel unm uted. 1: Left channel m uted. [4] DAC_HPF (R/W) DAC high pass filter 0: DAC high pass filter disabled. 1: DAC high pass filter enabled. Table 30. Bit Descriptions for DAC_CTRL Bits Bit Name 7 DAC_HV 6 5 4 Settings Description Reset Access Hard Volume Control. 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0 Soft Volume Ramping. 1 No Volume Ramping. DAC_MUTE_R DAC Right Channel Mute. 0 Right Channel Unmuted. 1 Right Channel Muted. DAC_MUTE_L DAC Left Channel Mute. 0 Left Channel Unmuted. 1 Left Channel Muted. DAC_HPF DAC High-Pass Filter. 0 DAC High-Pass Filter Disabled. 1 DAC High-Pass Filter Enabled. 3 RESERVED Reserved. 0x0 R [2:0] DAC_FS DAC Sample Rate Select. 0x2 R/W 0 8 kHz to 12 kHz. 1 16 kHz to 24 kHz. 10 32 kHz to 48 kHz. 11 64 kHz to 96 kHz. 100 128 kHz to 192 kHz. 101 48 kHz to 72 kHz. Rev. A| Page 42 of 59 Data Sheet SSM3582 Address: 0x07, Reset: 0x40, Name: VOL_LEFT_CTRL 7 6 5 4 3 2 0 1 0 1 0 0 0 0 0 0 [7:0] VOL_L (R/W) Left channel volum e 0x00: +24 dB. 0x01: +23.625 dB. 0x02: ... ... 0xFD: -70.875 dB. 0xFE: -71.25 dB. 0xFF: Mute. Table 31. Bit Descriptions for VOL_LEFT_CTRL Bits Bit Name [7:0] VOL_L Settings Description Reset Access Left Channel Volume 0x40 R/W Description Reset Access Right Channel Volume 0x40 R/W 0x00 +24 dB 0x01 +23.625 dB 0x02 … 0x3F +0.375 dB 0x40 0 dB 0x41 −0.375 dB 0x42 … 0xFD −70.875 dB 0xFE −71.25 dB 0xFF Mute Address: 0x08, Reset: 0x40, Name: VOL_RIGHT_CTRL 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 [7:0] VOL_R (R/W) Right channel volum e 0x00: +24 dB. 0x01: +23.625 dB. 0x02: ... ... 0xFD: -70.875 dB. 0xFE: -71.25 dB. 0xFF: Mute. Table 32. Bit Descriptions for VOL_RIGHT_CTRL Bits Bit Name [7:0] VOL_R Settings 0x00 +24 dB 0x01 +23.625 dB 0x02 … 0x3F +0.375 dB 0x40 0 dB 0x41 −0.375 dB 0x42 … 0xFD −70.875 dB 0xFE −71.25 dB 0xFF Mute Rev. A| Page 43 of 59 SSM3582 Data Sheet Address: 0x09, Reset: 0x11, Name: SAI_CTRL1 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 [7] RESERVED [0] SAI_MODE (R/W) Serial interface m ode select 0: Stereo m odes. 1: TDM m odes. [6] BCLK_POL (R/W) BCLK polarity control 0: Use rising edge to capture SDATA. 1: Use falling edge to capture SDATA. [1] SDATA_FMT (R/W) Serial data form at 0: I2S (delay by 1) Form at. 1: Left Justified Form at. [5:3] TDM_BCLKS (R/W) TDM slot width select 0: 16 bits. 1: 24 bits. 10: 32 bits. 11: 48 bits. 100: 64 bits. [2] FSYNC_MODE (R/W) FSYNC m ode 0: Stereo: low FSYNC is left channel; TDM: Fram e start on falling edge. 1: Stereo: high FSYNC is left channel; TDM: Fram e start on rising edge. Table 33. Bit Descriptions for SAI_CTRL1 Bits Bit Name 7 6 [5:3] 2 1 0 Settings Description Reset Access RESERVED Reserved. 0x0 R BCLK_POL BCLK Polarity Control 0x0 R/W 0x2 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0 Use Rising Edge to Capture SDATA 1 Use Falling Edge to Capture SDATA TDM_BCLKS TDM Slot Width Select 0 16 Bits 1 24 Bits 10 32 Bits 11 48 Bits 100 64 Bits FSYNC_MODE FSYNC Mode 0 Stereo: Low FSYNC is Left Channel; TDM: Frame Start on Falling Edge 1 Stereo: High FSYNC is Left Channel; TDM: Frame Start on Rising Edge SDATA_FMT Serial Data Format 0 I2S (Delay by 1) Format 1 Left Justified Format SAI_MODE Serial Interface Mode Select 0 Stereo Modes 1 TDM Modes Rev. A| Page 44 of 59 Data Sheet SSM3582 Address: 0x0A, Reset: 0x07, Name: SAI_CTRL2 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 [7] SDATA_EDGE (R/W) SDATA edge delay m ode 0: Norm al operation. 1: Half cycle delay of SDATA. [0] AUTO_SLOT (R/W) Autom atic TDM slot selection 0: Set TDM slots using TDM_SLOTx Bits. 1: Set TDM slots autom atically using ADDRx pin settings. [6:5] RESERVED [4] DATA_WIDTH (R/W) Audio input data width 0: 24 bits. 1: 16 bits. [3] VOL_ZC_ONLY (R/W) Volum e control zero-crossing detection 0: Allow volum e to change at all tim es. 1: Only change volum e when zero-crossing is detected (m ay be different per-channel) [1] VOL_LINK (R/W) Channel volum e link 0: Use independent VOL_L and VOL_R controls. 1: Link both channels to VOL_L control. [2] CLIP_LINK (R/W) High frequency clipper link 0: Use Independent Left and Right DAC_CLIP_x Bits. 1: Link Both Channels to DAC_CLIP_L Bits. Table 34. Bit Descriptions for SAI_CTRL2 Bits Bit Name 7 SDATA_EDGE Settings Description Reset Access SDATA Edge Delay Mode 0x0 R/W 0 Normal Operation 1 Half Cycle Delay of SDATA [6:5] RESERVED Reserved 0x0 R 4 DATA_WIDTH Audio Input Data Width 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x1 R/W 3 2 1 0 0 24 Bits 1 16 Bits VOL_ZC_ONLY Volume Control Zero-Crossing Detection 0 Allow Volume to Change at All Times 1 Only Change Volume When Zero-Crossing is Detected (May Be Different Per Channel) CLIP_LINK High Frequency Clipper Link 0 Use Independent Left and Right DAC_CLIP_x Bits 1 Link Both Channels to DAC_CLIP_L Bits VOL_LINK Channel Volume Link 0 Use Independent VOL_L and VOL_R Controls 1 Link Both Channels to VOL_L Control AUTO_SLOT Automatic TDM Slot Selection 0 Set TDM Slots Using TDM_SLOT_x Bits 1 Set TDM Slots Automatically Using the ADDRx Pin Settings Rev. A| Page 45 of 59 SSM3582 Data Sheet Address: 0x0B, Reset: 0x00, Name: SLOT_LEFT_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:5] RESERVED [4:0] TDM_SLOT_L (R/W) Left channel s lot s election Table 35. Bit Descriptions for SLOT_LEFT_CTRL Bits Bit Name [7:5] [4:0] Settings Description Reset Access RESERVED Reserved 0x0 R TDM_SLOT_L Left Channel Slot Selection 0x0 R/W Description Reset Access Address: 0x0C, Reset: 0x01, Name: SLOT_RIGHT_CTRL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7:5] RESERVED [4:0] TDM_SLOT_R (R/W) Right channel s lot s election Table 36. Bit Descriptions for SLOT_RIGHT_CTRL Bits Bit Name Settings [7:5] RESERVED Reserved 0x0 R [4:0] TDM_SLOT_R Right Channel Slot Selection 0x1 R/W Address: 0x0E, Reset: 0xA0, Name: LIM_LEFT_CTRL1 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 [7:6] LIM_RRT_L (R/W) Left lim iter release rate 0: 3200 m s/dB. 1: 1600 m s/dB. 10: 1200 m s/dB. 11: 800 m s/dB. [1:0] LIM_EN_L (R/W) Left lim iter m ode 0: Lim iter off. 1: Lim iter on. 10: Mute output if VBAT