USB-EA-CONVZ

MicroConverter® Multichannel 12-Bit ADC with Embedded 62 kB Flash and Single-Cycle MCU ADuC841/ADuC842/ADuC843 Anomaly Sheet for Silicon Rev. E This anomaly list represents the known bugs, anomalies, and workarounds for the ADuC841, ADuC842, and ADuC843 MicroConverter products. The anomalies listed apply to all ADuC841/ADuC842/ADuC843 packaged material branded as follows: First(CSP) /Second (PQFP) Line Third (CSP) / Fourth Line (PQFP) ADuC841 or ADuC842 or ADuC843 E20 Analog Devices, Inc. is committed, through future silicon revisions, to continuously improving silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems implementing the recommended workarounds outlined here. ADuC841/ADuC842/ADuC843 SILICON REVISION HISTORY Silicon Revision Identifier E Kernel Revision Identifier 0 E 0 Chip Marking All silicon branded ADUC841BS or ADuC841BCP ADuC842BS or ADuC842BCP ADuC843BS or ADuC843BCP Third/Fourth Line: E20 All silicon branded ADUC841BS or ADuC841BCP ADuC842BS or ADuC842BCP ADuC843BS or ADuC843BCP Third/Fourth Line: E20 Silicon Status Release Anomaly Sheet Rev. 0 No. of Reported Anomalies 8 Release Rev. A 11 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADuC841/ADuC842/ADuC843 ANOMALIES 1. Mode 0 UART Operation [er001] Background: Issue: Workaround: Related Issues: UART Mode 0 allows the UART to function in an 8-bit shift register mode. UART Mode 0 is nonfunctional on the ADuC841/ADuC842/ADuC843. None. None. 2. Use of the Extended Stack Pointer [er002] Background: Issue: Workaround: Related Issues: The extended stack pointer allows the stack to overflow into internal XRAM. A PUSH onto the extended stack when it is the first instruction within a subroutine results in the return address being overwritten. For Assembly code, insert a NOP as the first instruction in any subroutine. For C code, there is currently no workaround. None. 3. Use of I2C in Slave Mode with Stop Interrupt Enabled [er003] Background: Issue A: Workaround A: Issue B: Workaround B: Related Issues: In slave mode, the I2C interface can be configured to generate an interrupt due to a start, repeated start, data, or stop condition. The I2C interrupt decode bits (I2CID0 and I2CID1) in I2CCON indicate the source of the interrupt. If the stop interrupt is enabled via the I2CSI bit, an interrupt is generated when the slave receives a stop condition. In the I2C interrupt service routine, if the I2CI bit or I2CDAT register is accessed during a stop interrupt, the I2C bus will fail to respond to further I2C communication. When a stop interrupt is detected, the user should reset the I2C bus by using the I2CRS bit. When the stop interrupt is enabled, on occasion the I2C interrupt decode bits indicate that a start, repeated start, or DATA interrupt occurred when the source was in fact a stop interrupt. If this happens the user may try to clear I2CI or read I2CDAT, resulting in the bus failing to respond to further I2C communication. Tie the SCLOCK pin to an I/O pin; This allows the state of SCLOCK to be read. SCLOCK is high only during an interrupt if the source is a stop interrupt. er004: Use of I2C in slave mode with stop interrupt disabled. 4. Use Of I2C in Slave Mode with Stop Interrupt Disabled [er004] Background: Issue: Workaround: Related Issues: In slave mode, the I2C interface can be configured to generate an interrupt due to a start, repeated start, data, or stop condition. The I2C interrupt decode bits (I2CID0 and I2CID1) in I2CCON indicate the source of the interrupt. Once one repeated start is detected by the I2C interface, all subsequent start conditions are detected as a repeated start even if a stop bit has been received between data transfers. None. None. 5. I2C Data Transfer [er005] Background: Issue A: Workaround A: Issue B: Workaround B: Issue C: Workaround C: Related Issues: The I2CDAT register is used to read or write data to the I2C bus. The I2CDAT register has an SFR address of 0x9A. During an I2C transfer if a user accesses the RAM address 0x9A the contents of the I2CDAT SFR can be modified. For Assembly code: Do not use memory location 0x9A For C code: Assign a dummy variable to location 0x9A using the following code: idata unsigned int ui32Dummy[2] _at_ 0x9A; During an I2C transfer, if a user executes either of the following instructions, the contents of the I2CDAT SFR can be modified. MOV dest,#9AH SUBB A,R2 To prevent code from changing the contents of the I2CDAT SFR make sure that neither of these instructions are executed during an I2C transfer. A small percentage (