FEATURES
FUNCTIONAL BLOCK DIAGRAMS
4.7 Ω maximum on resistance at 25°C
0.5 Ω on-resistance flatness
Up to 190 mA continuous current
Fully specified at ±15 V/+12 V/±5 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP and 4 mm × 4 mm LFCSP
ADG1408
S1A
DA
S4A
D
S1B
DB
S8
APPLICATIONS
S4B
1-OF-8
DECODER
Relay replacement
Audio and video routing
Automatic test equipment
Data acquisition systems
Temperature measurement systems
Avionics
Battery-powered systems
Communication systems
Medical equipment
1-OF-4
DECODER
A0 A1 A2 EN
A0
A1
EN
Figure 1.
GENERAL DESCRIPTION
The ADG1408/ADG1409 are monolithic iCMOS® analog multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1408 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2. The ADG1409 switches one of
four differential inputs to a common differential output, as
determined by the 2-bit binary address lines, A0 and A1. An EN
input on both devices is used to enable or disable the device.
When disabled, all channels are switched off.
The industrial CMOS (iCMOS) modular manufacturing process
combines high voltage complementary metal-oxide semiconductor
(CMOS) and bipolar technologies. It enables the development
of a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no other generation of high voltage
devices has been able to achieve. Unlike analog ICs using
conventional CMOS processes, iCMOS components can tolerate
high supply voltages while providing increased performance,
dramatically lower power consumption, and reduced package size.
Rev. D
ADG1409
S1
04861-001
Data Sheet
4 Ω RON, 4-/8-Channel,
±15 V/+12 V/±5 V iCMOS Multiplexers
ADG1408/ADG1409
The ultralow on resistance and on resistance flatness of these
switches make them ideal solutions for data acquisition and
gain switching applications where low distortion is critical.
iCMOS construction ensures ultralow power dissipation,
making the devices ideally suited for portable and batterypowered instruments.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
4 Ω on resistance.
0.5 Ω on-resistance flatness.
3 V logic compatible digital input, VIH = 2.0 V, VIL = 0.8 V.
16-lead TSSOP and 4 mm × 4 mm LFCSP.
Table 1. Related Devices
Device No.
ADG1208/ADG1209
Description
Low capacitance, low charge injection,
and low leakage 4-/8-channel ±15 V
multiplexers
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ADG1408/ADG1409
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Continuous Current per channel, S or D ...................................8
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................9
Functional Block Diagrams ............................................................. 1
Thermal Resistance .......................................................................9
General Description ......................................................................... 1
ESD Caution...................................................................................9
Product Highlights ........................................................................... 1
Pin Configurations and Function Descriptions ......................... 10
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 12
Specifications..................................................................................... 3
Terminology .................................................................................... 16
15 V Dual Supply .......................................................................... 3
Test Circuits ..................................................................................... 17
12 V Single Supply ........................................................................ 5
Outline Dimensions ....................................................................... 19
5 V Dual Supply ............................................................................ 7
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/2016—Rev. C to Rev. D
Changes to Analog Inputs Parameter, Table 6 .............................. 9
Added Digital Inputs Parameter, Table 6 ...................................... 9
5/2016—Rev. B to Rev. C
Changed CP-16-13 to CP-16-26 .................................. Throughout
Changes to Figure 3 ........................................................................ 10
Changes to Figure 5 ........................................................................ 11
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
3/2009—Rev. A to Rev. B
Change to IDD Parameter, Table 2 ................................................... 4
Change to IDD Parameter, Table 3 ................................................... 6
8/2008—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Added Table 5; Renumbered Sequentially .................................... 8
Changes to Table 6 ............................................................................ 9
Added Exposed Pad Notation to Figure 3 ................................... 10
Added Exposed Pad Notation to Figure 5 ................................... 11
Added Exposed Pad Notation to Outline Dimensions ............. 19
8/2006—Revision 0: Initial Version
Rev. D | Page 2 of 19
Data Sheet
ADG1408/ADG1409
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
+25°C
−40°C to
+85°C
−40°C to
+125°C1
VSS to VDD
4
4.7
0.2
0.78
0.5
0.72
±0.04
±0.2
±0.04
±0.45
±0.1
±1.5
5.7
6.7
0.85
1.1
0.77
0.92
±0.6
±5
±2
±30
±3
±30
2.0
0.8
±0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Break-Before-Make Time Delay, tBBM
4
140
170
50
210
240
30
tON (EN)
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus
Noise (THD + N)
−3 dB Bandwidth
ADG1408
ADG1409
Insertion Loss
CS (Off )
CD (Off )
ADG1408
ADG1409
100
120
100
120
−50
−70
−70
0.025
150
165
150
170
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −10 mA; see Figure 26
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
60
115
0.24
14
MHz typ
MHz typ
dB typ
pF typ
80
40
pF typ
pF typ
Rev. D | Page 3 of 19
VS = ±10 V, IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = ∓10 V; see Figure 27
VS = ±10 V, VD = ∓10 V; see Figure 27
VS = VD = ±10 V; see Figure 28
VIN = VGND or VDD
RL = 100 Ω, CL = 35 pF
VS = 10 V, see Figure 29
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 10 V; see Figure 31
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
f = 1 MHz
f = 1 MHz
ADG1408/ADG1409
Parameter
CD, CS (On)
ADG1408
ADG1409
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C1
135
90
pF typ
pF typ
0.002
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
1
220
380
ISS
0.002
VDD/VSS
1
2
Unit
1
±4.5/±16.5
Temperature range: Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. D | Page 4 of 19
Test Conditions/Comments
f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V or VDD
Data Sheet
ADG1408/ADG1409
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
+25°C
−40°C to
+85°C
−40°C to
+125°C1
0 to VDD
6
8
0.2
0.82
1.5
2.5
±0.04
±0.2
±0.04
±0.45
±0.06
±0.44
9.5
11.2
0.85
1.1
2.5
2.8
±0.6
±5
±1
±37
±1.3
±32
2.0
0.8
±0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Break-Before-Make Time Delay, tBBM
5
200
260
90
330
380
40
tON (EN)
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG1408
ADG1409
Insertion Loss
CS (Off )
CD (Off )
ADG1408
ADG1409
CD, CS (On)
ADG1408
ADG1409
160
210
115
145
−12
−70
−70
250
285
180
200
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −10 mA; see Figure 26
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
36
72
0.5
25
MHz typ
MHz typ
dB typ
pF typ
165
80
pF typ
pF typ
200
120
pF typ
pF typ
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27
VS = VD = 1 V or 10 V; see Figure 28
VIN = VGND or VDD
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
RL = 50 Ω, CL = 5 pF; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
f = 1 MHz
f = 1 MHz
f = 1 MHz
Rev. D | Page 5 of 19
ADG1408/ADG1409
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C1
0.002
1
220
VDD
1
2
380
5/16.5
Unit
μA typ
μA max
μA typ
μA max
V min/max
Temperature range for Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. D | Page 6 of 19
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
Data Sheet
ADG1408/ADG1409
5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between
Channels (ΔRON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
+25°C
−40°C to
+85°C
−40°C to
+125°C1
VSS to VDD
7
9
0.3
0.78
1.5
2.5
±0.02
±0.2
±0.02
±0.45
±0.04
±0.3
10.5
12
0.91
1.1
2.5
3
±0.6
±5
±0.8
±20
±1.1
±22
2.0
0.8
±0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
Break-Before-Make Time Delay, tBBM
5
330
440
100
530
550
50
tON (EN)
tOFF (EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus
Noise (THD + N)
−3 dB Bandwidth
ADG1408
ADG1409
Insertion Loss
CS (Off )
CD (Off )
ADG1408
ADG1409
CD, CS (On)
ADG1408
ADG1409
245
330
215
285
–10
–70
–70
0.06
400
440
335
370
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = ±4.5 V, IS = −10 mA; see Figure 26
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = −10 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
40
80
0.5
20
MHz typ
MHz typ
dB typ
pF typ
130
65
pF typ
pF typ
180
120
pF typ
pF typ
VS = ±4.5 V; IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = ∓4.5 V; see Figure 27
VS = ±4.5 V, VD = ∓4.5 V; see Figure 27
VS = VD = ±4.5 V; see Figure 28
VIN = VGND or VDD
RL = 100 Ω, CL = 35 pF
VS = 5 V; see Figure 29
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 5 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 5 V; see Figure 31
RL = 100 Ω, CL = 35 pF
VS = 5 V; see Figure 31
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
f = 1 MHz
f = 1 MHz
f = 1 MHz
Rev. D | Page 7 of 19
ADG1408/ADG1409
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C1
0.001
Digital inputs = 0 V, 5 V or VDD
1
±4.5/±16.5
Test Conditions/Comments
0.001
VDD/VSS
1
2
Test Conditions/Comments
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VDD
μA typ
μA max
μA typ
μA max
V min/max
1
ISS
Unit
Temperature range for Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter
CONTINUOUS CURRENT, S or D1
15 V Dual Supply
ADG1408
ADG1409
12 V Single Supply
ADG1408
ADG1409
5 V Dual Supply
ADG1408
ADG1409
1
25°C
85°C
125°C
Unit
190
140
105
85
50
45
mA max
mA max
160
120
95
75
50
40
mA max
mA max
155
115
90
70
45
40
mA max
mA max
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Guaranteed by design, not subject to production test.
Rev. D | Page 8 of 19
Data Sheet
ADG1408/ADG1409
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
Operating Temperature Range
Industrial (Y Version)
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature
(RoHS Compliant)
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
GND − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
Table 5 data + 10%
350 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
16-Lead TSSOP
16-Lead LFCSP
−40°C to +125°C
−65°C to +150°C
150°C
260(+0/−5)°C
ESD CAUTION
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Rev. D | Page 9 of 19
θJA
150.4
30.4
θJC
50
Unit
°C/W
°C/W
ADG1408/ADG1409
Data Sheet
A2
ADG1408
14
GND
TOP VIEW
(Not to Scale)
13
VDD
S1 2
S2 5
VSS 1
S5
S2 3
11
S6
S3 4
S4 7
10
S7
D 8
9
S8
TOP VIEW
(Not to Scale)
11 VDD
10 S5
9
S4 5
04861-002
12
S3 6
12 GND
ADG1408
S6
S7 8
S1 4
S8 7
3
D 6
VSS
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.
04861-003
A1
13 A2
16
15
14 A1
16 EN
A0 1
EN 2
15 A0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. ADG1408 Pin Configuration (LFCSP)
Figure 2. ADG1408 Pin Configuration (TSSOP)
Table 8. ADG1408 Pin Function Descriptions
Pin No.
TSSOP
1
2
LFCSP
15
16
Mnemonic
A0
EN
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Not
applicable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
VSS
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
EPAD
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
Most Negative Power Supply Potential. In single supply applications, it can be connected to ground.
Source Terminal 1. Can be an input or an output.
Source Terminal 2. Can be an input or an output.
Source Terminal 3. Can be an input or an output.
Source Terminal 4. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Source Terminal 8. Can be an input or an output.
Source Terminal 7. Can be an input or an output.
Source Terminal 6. Can be an input or an output.
Source Terminal 5. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG1408 Truth Table
A2
X
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
Rev. D | Page 10 of 19
On Switch
None
1
2
3
4
5
6
7
8
TOP VIEW
(Not to Scale)
13
12
S2B
11
S3B
S2A
5
S3A
6
S4A
7
10
DA 8
9
12 VDD
11 S1B
S2A 3
ADG1409
TOP VIEW
(Not to Scale)
S3A 4
S4B
DB
VSS 1
S1A 2
10 S2B
9
S4A 5
4
04861-004
S1A
S3B
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, VSS.
04861-005
S1B
ADG1409
14
13 GND
VDD
3
14 A1
GND
VSS
DB 7
A1
S4B 8
16
15
DA 6
A0 1
EN 2
16 EN
ADG1408/ADG1409
15 A0
Data Sheet
Figure 5. ADG1409 Pin Configuration (LFCSP)
Figure 4. ADG1409 Pin Configuration (TSSOP)
Table 10. ADG1409 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
15
2
16
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Not
applicable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
Mnemonic
A0
EN
VSS
S1A
S2A
S3A
S4A
DA
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
EPAD
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
Most Negative Power Supply Potential. In single supply applications, it can be connected to ground.
Source Terminal 1A. Can be an input or an output.
Source Terminal 2A. Can be an input or an output.
Source Terminal 3A. Can be an input or an output.
Source Terminal 4A. Can be an input or an output.
Drain Terminal A. Can be an input or an output.
Drain Terminal B. Can be an input or an output.
Source Terminal 4B. Can be an input or an output.
Source Terminal 3B. Can be an input or an output.
Source Terminal 2B. Can be an input or an output.
Source Terminal 1B. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG1409 Truth Table
A1
X
0
0
1
1
A0
X
0
1
0
1
EN
0
1
1
1
1
On Switch Pair
None
1
2
3
4
Rev. D | Page 11 of 19
ADG1408/ADG1409
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
7
VDD = +15V
VSS = –15V
TA = 25°C
6
ON RESISTANCE (Ω)
4
3
2
1
0
–16.5
VDD
VDD
VDD
VDD
VDD
= +15V, VSS = –15V
= +13.5V, VSS = –13.5V
= +12V, VSS = –12V
= +10V, VSS = –10V
= +16.5V, VSS = –16.5V
–12.5
–8.5
–4.5
5
4
3
2
1
–0.5
3.5
7.5
15.5
11.5
SOURCE OR DRAIN VOLTAGE (V)
0
–15
04861-006
ON RESISTANCE (Ω)
5
TA = +25°C
TA = +85°C
TA = –40°C
TA = +125°C
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
04861-008
6
Figure 9. On Resistance vs. VD, VS for Different Temperatures;
15 V Dual Supply
Figure 6. On Resistance vs. VD, VS; Dual Supply
12
9
VDD = +5V
VSS = –5V
TA = 25°C
8
10
5
4
3
2
1
0
–7
VDD
VDD
VDD
VDD
–6
= +7V, VSS = –7V
= +5.5V, VSS = –5.5V
= +5V, VSS = –5V
= +4.5V, VSS = –4.5V
–5
–4
–3
–2
–1
0
1
2
3
4
5
7
6
4
0
–5
TA = +25°C
TA = +85°C
TA = –40°C
TA = +125°C
–4
–3
–2
–1
0
1
2
3
4
5
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance vs. VD, VS for Different Temperatures;
5 V Dual Supply
Figure 7. On Resistance vs. VD, VS; Dual Supply
10
13
TA = 25°C
VSS = 0V
12
VDD = 12V
VSS = 0V
9
11
8
9
8
7
6
5
4
2
1
0
VDD
VDD
VDD
VDD
VDD
= 12V
= 13.2V
= 10.8V
= 8V
= 5V
1
2
3
6
5
4
3
2
TA = +25°C
TA = +85°C
TA = –40°C
TA = +125°C
1
4
5
6
7
8
9
10
11
12
SOURCE OR DRAIN VOLTAGE (V)
13
04861-007
3
7
0
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
Figure 11. On Resistance vs. VD, VS for Different Temperatures;
12 V Single Supply
Figure 8. On Resistance vs. VD, VS; Single Supply
Rev. D | Page 12 of 19
04861-010
ON RESISTANCE (Ω)
10
ON RESISTANCE (Ω)
6
2
SOURCE OR DRAIN VOLTAGE (V)
0
8
04861-009
ON RESISTANCE (Ω)
6
04861-036
ON RESISTANCE (Ω)
7
Data Sheet
1.0
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) ––
0.6
0.4
18
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) ––
16
14
LEAKAGE CURRENT (nA)
0.8
0.2
0
–0.2
–0.4
–0.6
12
10
8
6
4
0
–1.0
–2
0
10
20
30
40
50
60
70
80
04861-011
–0.8
0
20
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) ––
10
80
100
120
Figure 15. Leakage Current vs. Temperature;
12 V Single Supply
70
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
IDD PER CHANNEL
TA = 25°C
60
50
8
IDD (µA)
6
4
40
VDD = +15V
VSS = –15V
VDD = +12V
VSS = 0V
30
2
20
0
10
–2
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
04861-012
–4
VDD = +5V
VSS = –5V
2
0
7
VDD = +5V
VSS = –5V
VBIAS = +4.5V/–4.5V
12
14
TA = 25°C
150
6
5
4
3
2
100
50
VDD = +5V
VSS = –5V
0
VDD = +12V
VSS = 0V
–50
–100
1
VDD = +15V
VSS = –15V
–150
0
20
40
60
80
100
TEMPERATURE (°C)
120
04861-015
0
–1
10
Figure 16. Positive Supply Current vs. Logic Level
CHARGE INJECTION (pC)
8
8
200
IS (OFF) +–
ID (OFF) +–
IS (OFF) –+
ID (OFF) –+
ID, IS (ON) ++
ID, IS (ON) ––
9
6
LOGIC, AX (V)
Figure 13. Leakage Current vs. Temperature;
15 V Dual Supply
10
4
04861-034
LEAKAGE CURRENT (nA)
12
60
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature;
15 V Dual Supply
14
40
04861-013
2
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
Figure 14. Leakage Current vs. Temperature;
5 V Dual Supply
–200
–15
–10
–5
0
5
10
VS (V)
Figure 17. Charge Injection vs. Source Voltage
Rev. D | Page 13 of 19
15
04861-014
LEAKAGE CURRENT (nA)
ADG1408/ADG1409
ADG1408/ADG1409
Data Sheet
450
0
400
–20
VDD = +5V
VSS = –5V
350
–30
CROSSTALK (dB)
VDD = 12V
VSS = 0V
300
250
200
150
VDD = +15V
VSS = –15V
–40
ADJACENT
CHANNEL
–50
–60
–70
NONADJACENT
CHANNEL
–80
100
–90
50
–100
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
–110
1k
04861-033
0
–40
10k
100M
1G
0
VDD = +15V
VSS = –15V
TA = 25°C
–0.5
–1.0
–30
BANDWIDTH (dB)
OFF ISOLATION (dB)
10M
Figure 21. ADG1409 Crosstalk vs. Frequency
0
–20
1M
FREQUENCY (Hz)
Figure 18. Transition Time vs. Temperature
–10
100k
04861-018
TIME (ns)
VDD = +15V
VSS = –15V
TA = 25°C
–10
–40
–50
–60
–70
–80
–1.5
–2.0
–2.5
–3.0
–90
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–4.0
100
04861-016
–110
1k
VDD = +15V
VSS = –15V
TA = 25°C
1k
10M
100M
0
VDD = +15V
VSS = –15V
TA = 25°C
–0.5
–1.0
BANDWIDTH (dB)
–30
–40
–50
–60
–70
–80
–1.5
–2.0
–2.5
–3.0
–90
–110
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
Figure 20. ADG1408 Crosstalk vs. Frequency
VDD = +15V
VSS = –15V
TA = 25°C
–4.0
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 23. ADG1409 On Response vs. Frequency
Rev. D | Page 14 of 19
1G
04861-031
–3.5
–100
04861-017
CROSSTALK (dB)
1M
Figure 22. ADG1408 On Response vs. Frequency
0
–20
100k
FREQUENCY (Hz)
Figure 19. Off Isolation vs. Frequency
–10
10k
04861-019
–3.5
–100
Data Sheet
0.09
0
LOAD = 110Ω
TA = 25°C
–10
–20
0.08
–30
ACPSRR (dB)
VDD = +5V, VSS = –5V, VS = +5V p-p
0.06
0.05
0.04
0.03
VDD = +15V, VSS = –15V, VS = +15V p-p
NO DECOUPLING
CAPACITORS
–50
–60
–70
DECOUPLING
CAPACITORS
ON SUPPLIES
–90
0.01
0
10
–40
–80
0.02
–100
100
1k
10k
100k
FREQUENCY (Hz)
04861-032
THD + N (%)
0.07
VDD = +15V
VSS = –15V
TA = 25°C
V p-p = 0.63V
Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency
–110
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 25. AC Power Supply Rejection Ratio vs. Frequency
Rev. D | Page 15 of 19
10M
04861-035
0.10
ADG1408/ADG1409
ADG1408/ADG1409
Data Sheet
TERMINOLOGY
tBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
RON
Ohmic resistance between D and S.
ΔRON
Difference between the RON of any two channels.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IS (Off)
Source leakage current when the switch is off.
IINL, IINH
Input current of the digital input.
ID (Off)
Drain leakage current when the switch is off.
IDD
Positive supply current.
ID, IS (On)
Channel leakage current when the switch is on.
ISS
Negative supply current.
VD (VS)
Analog voltage on Terminal D and Terminal S.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (Off)
Channel input capacitance for off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for off condition.
Bandwidth
Frequency at which the output is attenuated by 3 dB.
CD, CS (On)
On switch capacitance.
On Response
Frequency response of the on switch.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
Total Harmonic Distortion Plus Noise (THD + N)
Ratio of the harmonic amplitude plus noise of the signal to the
fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
A measure of the ability of a device to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is
the ACPSRR.
Rev. D | Page 16 of 19
Data Sheet
ADG1408/ADG1409
TEST CIRCUITS
V
A
IDS
ID (ON)
ID (OFF)
A
NC
VD
Figure 26. On Resistance
50%
50%
S
D
A
VD
NC = NO CONNECT
Figure 27. Off Leakage
3V
ADDRESS
DRIVE (VIN)
D
VS
04861-020
VS
S
Figure 28. On Leakage
tr < 20ns
tf < 20ns
VDD
VSS
VDD
VSS
A0
0V
VIN
S1
A1
50Ω
A2
tTRANSITION
VS1
S2 TO S7
tTRANSITION
VS8
S8
ADG14081
90%
2.4V
OUTPUT
OUTPUT
D
EN
100Ω
GND
35pF
04861-023
90%
1SIMILAR CONNECTION FOR ADG1409.
Figure 29. Address to Output Switching Times, tTRANSITION
3V
ADDRESS
DRIVE (VIN)
VDD
VSS
VDD
VSS
A0
VIN
0V
S1
A1
50Ω
VS
S2 TO S7
A2
S8
80%
ADG14081
80%
OUTPUT
2.4V
OUTPUT
D
EN
100Ω
GND
35pF
04861-024
tBBM
1SIMILAR CONNECTION FOR ADG1409.
Figure 30. Break-Before-Make Delay, tBBM
3V
50%
VDD
VSS
A0
50%
S1
A1
0V
A2
tON (EN)
0.9VO
50Ω
OUTPUT
D
EN
VIN
VS
S2 TO S8
ADG14081
tOFF (EN)
0.9VO
OUTPUT
VSS
GND
100Ω
1SIMILAR CONNECTION FOR ADG1409.
Figure 31. Enable Delay, tON (EN), tOFF (EN)
Rev. D | Page 17 of 19
35pF
04861-025
ENABLE
DRIVE (VIN)
VDD
04861-022
IS (OFF)
D
04861-021
S
ADG1408/ADG1409
Data Sheet
3V
VDD
VSS
VDD
VSS
A0
A1
VIN
A2
ADG14081
VOUT
RS
ΔVOUT
D
S
VOUT
EN
QINJ = CL × ΔVOUT
VS
CL
1nF
GND
1SIMILAR
04861-026
VIN
CONNECTION FOR ADG1409.
Figure 32. Charge Injection
VSS
VDD
0.1µF
VDD
NETWORK
ANALYZER
VSS
S
VSS
0.1µF
0.1µF
VDD
50Ω
50Ω
50Ω
S
VS
VS
D
RL
50Ω
GND
D
VOUT
RL
50Ω
VOUT
VS
04861-027
GND
OFF ISOLATION = 20 log
INSERTION LOSS = 20 log
VDD
RL
50Ω
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
VSS
0.1µF
0.1µF
VOUT
VOUT
Figure 35. Insertion Loss
Figure 33. Off Isolation
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
04861-029
VDD
0.1µF
VDD
VDD
VSS
VSS
0.1µF
0.1µF
S1
AUDIO PRECISION
D
S2
VDD
R
50Ω
VSS
RS
S
IN
VS
GND
GND
Figure 34. Channel-to-Channel Crosstalk
RL
10kΩ
Figure 36. THD + N
Rev. D | Page 18 of 19
VOUT
04861-030
VOUT
VS
04861-028
VIN
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VS
V p-p
D
Data Sheet
ADG1408/ADG1409
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
8
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
2.60
2.50 SQ
2.40
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
042709-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG1408YRUZ
ADG1408YRUZ-REEL
ADG1408YRUZ-REEL7
ADG1408YCPZ-REEL7
ADG1409YRUZ
ADG1409YRUZ-REEL
ADG1409YRUZ-REEL7
ADG1409YCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04861-0-6/16(D)
Rev. D | Page 19 of 19
Package Option
RU-16
RU-16
RU-16
CP-16-26
RU-16
RU-16
RU-16
CP-16-26
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