P87C51

Datasheet 87C51, 80C51BH, 80C31BH CHMOS Single-Chip 8-Bit Microcontroller The 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on reliable CHMOS III-E technology. Being a member of the MCS® 51 controller family, the 87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller family of products. Rochester Electronics Manufactured Components Rochester branded components are manufactured using either die/wafers purchased from the original suppliers or Rochester wafers recreated from the original IP. All re-creations are done with the approval of the Original Component Manufacturer (OCM). Parts are tested using original factory test programs or Rochester developed test solutions to guarantee product meets or exceeds the OCM data sheet. Quality Overview • ISO-9001 • AS9120 certification • Qualified Manufacturers List (QML) MIL-PRF-35835 • Class Q Military • Class V Space Level • Qualified Suppliers List of Distributors (QSLD) • Rochester is a critical supplier to DLA and meets all industry and DLA standards. Rochester Electronics, LLC is committed to supplying products that satisfy customer expectations for quality and are equal to those originally supplied by industry manufacturers. The original manufacturer’s datasheet accompanying this document reflects the performance and specifications of the Rochester manufactured version of this device. Rochester Electronics guarantees the performance of its semiconductor products to the original OCM specifications. ‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. FOR REFERENCE ONLY © 2018 Rochester Electronics, LLC. All Rights Reserved 10082018 To learn more, please visit www.rocelec.com 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER 87C51/80C51BH/80C51BHP/80C31BH *See Table 1 for Proliferation Options High Performance CHMOS EPROM 5 Interrupt Sources 24 MHz Operation Programmable Serial Port Improved Quick-Pulse Programming Algorithm TTL- and CMOS-Compatible Logic Levels 3-Level Program Memory Lock 64K External Program Memory Space Boolean Processor 64K External Data Memory Space 128-Byte Data RAM ONCE Mode Facilitates System Testing 32 Programmable I/O Lines Power Control Modes Idle Power Down Two 16-Bit Timer/Counters Extended Temperature Range (- 40°C to + 85 °C) MEMORY ORGANIZATION July 2004 Order Number: 272335-004 87C51/80C51BH/80C31BH Table 1. Proliferation Options Standard -1 -2 -24 80C31BH X X X X 80C51BH X X X X 80C51BHP X X X X 87C51 X X X X NOTES: 3.5 MHz -1 3.5 MHz -2 0.5 MHz -24 3.5 MHz to to to to 12 16 12 24 MHz; VCC MHz; VCC MHz; VCC MHz; VCC 5V 5V 5V 5V 20% 20% 20% 20% 272335 ±1 Figure 1. 87C51/BH Block Diagram 2 87C51/80C51BH/80C31BH PROCESS INFORMATION PACKAGES Part Package Type PLCC DIP QFP Figure 2. Pin Connections 87C51/80C51BH/80C31BH PIN DESCRIPTION VCC: Supply voltage during normal, Idle and Power Down operations. VSS: Circuit ground. Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pullups when emitting 1's. Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address bytes during EPROM programming and program verification. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX DPTR). In this application it uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit addresses (MOVX Ri), Port 2 emits the contents of the P2 Special Function Register. 4 Port 2 also receives some control signals and the high-order address bits during EPROM programming and program verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Pin Name P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe Port 3 also receives some control signals for EPROM programming and program verification. RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not. An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC. ALE/PROG : Address Latch Enable output signal for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during EPROM programming for the 87C51. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. However, the ALE disable feature will be suspended during a MOVX or MOVC instruction, idle mode, power down mode and ICE mode. The ALE disable feature will be terminated by reset. When the ALE disable feature is suspended or terminated, the ALE pin will no longer be pulled up weakly. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. 87C51/80C51BH/80C31BH In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. PSEN: Program Store Enable is the Read strobe to External Program Memory. When the 87C51/BH is executing from Internal Program Memory, PSEN is inactive (high). When the device is executing code from External Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to External Data Memory. EA/V PP: External Access enable. EA must be strapped to VSS in order to enable the 87C51/BH to fetch code from External Program Memory locations starting at 0000H up to FFFFH. Note, however, that if either of the Lock Bits is programmed, the logic level at EA is internally latched during reset. EA must be strapped to VCC for internal program execution. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 3. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF. This pin also receives the programming supply voltage (VPP) during EPROM programming. XTAL1 : Input to the inverting oscillator amplifier. XTAL2 : Output from the inverting oscillator amplifier. 272335 ±6 Figure 4. External Clock Drive 272335 ±5 Figure 3. Using the On-Chip Oscillator 5 87C51/80C51BH/80C31BH IDLE MODE the on-chip RAM. An external interrupt allows both the SFRs and on-chip RAM to retain their values. In Idle Mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the Special Functions Registers remain unchanged during this mode. The Idle Mode can be terminated by any enabled interrupt or by a hardware reset. To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level, and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). It should be noted that when Idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. POWER DOWN MODE To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is transmitted. On the 87C51/BH either a hardware reset or an external interrupt can cause an exit from Power Down. Reset redefines all the SFR's but does not change With an external interrupt INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RET1 will be the one following the instruction that put the device into Power Down. DESIGN CONSIDERATIONS Exposure to light when the device is in operation may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window when the die is exposed to ambient light. The 87C51/BH now have some additional features. The features are: asynchronous port reset, 4 interrupt priority levels, power off flag, ALE disable, serial port automatic address recognition, serial port framing error detection, 64-byte encryption array, and 3 program lock bits. These features cannot be used with the older versions of 80C51BH/80C31BH. The newer version of 80C51BH/80C31BH will have change identifier "A'' appended to the lot number. Table 2. Status of the External Pins during Idle and Power Down Program Memory ALE PSEN Idle Internal 1 Idle External 1 Mode 6 PORT0 PORT1 PORT2 PORT3 1 Data 1 Float Data Data Data Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data 87C51/80C51BH/80C31BH ONCE MODE 87C51/BH EXPRESS ° ° -4 ° + ° ° = ± 87C51/80C51BH/80C31BH ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS Symbol Description Min Max Unit DC CHARACTERISTICS Symbol Parameter Min Typ(1) Max Unit Test Conditions 87C51/80C51BH/80C31BH DC CHARACTERISTICS (Over Operating Conditions) (Continued) Symbol Parameter VOL1 Output Low Voltage (6) (Port 0, ALE, PSEN) Min Typ(1) Max VOH1 IIL Output High Voltage (Ports 1, 2, 3, ALE, PSEN) Output High Voltage (Port 0 in External Bus Mode) IOL 200 A(2) 0.45 V IOL 3.2 mA (2) 7.0 mA(2) V IOL VCC 0.3 V IOH 10 A(3) VCC 0.7 V IOH 30 A(3) VCC 1.5 V IOH 60 A(3) VCC 0.3 V IOH 200 A(3) VCC 0.7 V IOH 3.2 mA(3) VCC 1.5 V IOH 7.0 mA(3) Logical 0 Input Current (Ports 1, 2, 3) Commercial Express ILI Input Leakage Current (Port 0) ITL Logical 1-to-0 Transition Current (Ports 1, 2, 3) Commercial Express RRST RST Pulldown Resistor CIO Pin Capacitance ICC Power Supply Current Active Mode 12 MHz (Figure 5) 16 MHz 24 MHz Idle Mode 12 MHz (Figure 5) 16 MHz 24 MHz Power Down Mode Test Conditions V 1.0 VOH Unit 0.3 50 75 A A 10 A VIN 0.45V 0.45 VIN VIN 650 750 40 225 10 VCC 2V A A k pF 1 MHz, 25 C (Note 4) 11.5 20 26 38 mA mA mA 3.5 7.5 9.5 13.5 mA mA mA 5 50 A 9 87C51/80C51BH/80C31BH NOTES: 1. ``Typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are at room temp, 5V. 2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic. 3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. See Figures 6 through 8 for ICC test conditions. Minimum VCC for Power Down is 2V. 5. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit portPort 0: 26 mA Ports 1, 2, and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions. 272335 ±26 Figure 5. 87C51/BH I CC vs Frequency 10 87C51/80C51BH/80C31BH 272335 ±10 Figure 6. I CC Test Condition, Active Mode. All other pins are disconnected. 272335 ±9 272335 ±8 Figure 7. I CC Test Condition, Idle Mode. All other pins are disconnected. Figure 9. I CC Test Condition, Power Down Mode. All other pins are disconnected. VCC 2V to 5.5V. 272335 ±11 Figure 8. Clock Signal Waveform for I CC Tests in Active and Idle Modes TCLCH TCHCL 5 ns 11 87C51/80C51BH/80C31BH L:Logic level LOW, or ALE. EXPLANATION OF THE AC SYMBOLS P:PSEN. Each timing symbol has 5 characters. The first character is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Q:Output data. R:RD signal. T:Time. V:Valid. W:WR signal. A:Address. X:No longer a valid logic level. C:Clock. Z:Float. D:Input data. For example, H:Logic level HIGH. I:Instruction (program memory contents). TAVLL Time from Address Valid to ALE Low. TLLPL Time from ALE Low to PSEN Low. AC CHARACTERISTICS: PSEN (Over Operating Conditions; Load Capacitance for Port 0, ALE, and 100 pF; Load Capacitance for All Other Outputs 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. Oscillator Symbol Parameter 1/TCLCL Oscillator Frequency 87C51/BH 87C51-1/BH-1 87C51-2/BH-2 87C51-24/BH-24 12 MHz Min TLHLL ALE Pulse Width 127 TAVLL Address Valid to ALE Low 87C51/BH 87C51-24/BH-24 43 TLLAX Address Hold After ALE Low 53 TLLIV ALE Low to Valid Instr In 87C51/BH 87C51-24/BH-24 Max 24 MHz Min Max Variable Units Min Max 3.5 3.5 0.5 3.5 12 16 12 24 MHz MHz MHz MHz 43 2TCLCL 40 ns 12 TCLCL 40 TCLCL 30 ns ns 12 TCLCL 30 ns 234 4TCLCL 100 4TCLCL 75 91 ns ns TLLPL ALE Low to PSEN Low 53 12 TCLCL 30 ns TPLPH PSEN Pulse Width 205 80 3TCLCL 45 ns TPLIV PSEN Low to Valid Instr In 87C51/BH 87C51-24/BH-24 12 145 35 3TCLCL 105 3TCLCL 90 ns ns 87C51/80C51BH/80C31BH EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued) Oscillator Symbol Parameter 12 MHz Min Max 0 24 MHz Min Max 0 Units Variable Min Max TPXIX Input Instr Hold After PSEN TPXIZ Input Instr Float After PSEN 87C51/BH 87C51-24/BH-24 59 TAVIV Address to Valid Instr In TPLAZ PSEN Low to Address Float TRLRH RD Pulse Width 400 150 6TCLCL 100 ns TWLWH WR Pulse Width 400 150 6TCLCL 100 ns TRLDV RD Low to Valid Data In 87C51/BH 87C51-24/BH-24 TCLCL 25 TCLCL 20 312 103 5TCLCL 105 ns 10 10 10 ns 252 Data Hold After RD TRHDZ Data Float After RD 0 107 TLLDV ALE Low to Valid Data In 87C51/BH 87C51-24/BH-24 517 Address to Valid Data In 87C51/BH 87C51-24/BH-24 585 ALE Low to RD or WR Low 200 TAVWL Address to RD or WR Low 87C51/BH 87C51-24/BH-24 203 Data Valid to WR Transition 87C51/BH 80C51-24/BH-24 33 TQVWX ns ns 23 2TCLCL 60 ns 243 8TCLCL 150 8TCLCL 90 ns ns 285 9TCLCL 165 9TCLCL 90 ns ns 3TCLCL ns 0 300 75 ns ns 5TCLCL 165 5TCLCL 95 113 TLLWL ns 21 TRHDX TAVDV 0 0 175 3TCLCL 50 ns 50 77 4TCLCL 130 4TCLCL 90 ns ns 12 TCLCL 50 TCLCL 30 ns ns 13 87C51/80C51BH/80C31BH EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued) Oscillator Symbol Parameter 12 MHz Min TWHQX TQVWH Data Hold After WR 87C51/BH 87C51-24/BH-24 33 Data Valid to WR High 87C51/BH 87C51-24/BH-24 433 TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE High 87C51/BH 87C51-24/BH-24 Max 24 MHz Min Units Variable Min Max 7 TCLCL 50 TCLCL 35 ns ns 222 7TCLCL 150 7TCLCL 70 ns ns 0 43 Max 0 123 12 71 TCLCL 40 TCLCL 30 0 ns TCLCL 40 TCLCL 30 ns ns EXTERNAL PROGRAM MEMORY READ CYCLE 272335 ±12 EXTERNAL DATA MEMORY READ CYCLE 272335 ±13 14 87C51/80C51BH/80C31BH EXTERNAL DATA MEMORY WRITE CYCLE 272335-14 EXTERNAL CLOCK DRIVE All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. Symbol Parameter 1/TCLCL Oscillator Frequency 87C51/BH 87C51-1/BH-1 87C51-2/BH-2 87C51-24/BH-24 TCHCX TCLCX TCLCH TCHCL Min Max Units 3.5 3.5 0.5 3.5 12 16 12 24 MHz MHz MHz MHz High Time 87C51/BH 8751-24/BH-24 20 0.35TCLCL 0.65TCLCL ns ns Low Time 87C51/BH 87C51-24/BH-24 20 0.35TCLCL 0.65TCLCL ns ns Rise Time 87C51/BH 87C51-24/BH-24 20 10 ns ns Fall Time 87C51/BH 87C51-24/BH-24 20 10 ns ns EXTERNAL CLOCK DRIVE WAVEFORM 272335 ±15 15 87C51/80C51BH/80C31BH SERIAL PORT TIMING-SHIFT REGISTER MODE Symbol Parameter 12 MHz Oscillator Min Max 24 MHz Oscillator Min Max Variable Oscillator Min TXLXL Serial Port Clock Cycle Time 1.0 0.500 12TCLCL TQVXH Output Data Setup to Clock Rising Edge 700 284 10TCLCL 133 TXHQX Output Data Hold After Clock Rising Edge 87C51/BH 87C51-24/BH-24 TXHDX Input Data Hold After Clock Rising Edge TXHDV Clock Rising Edge to Input Data Valid Units Max s ns ns 50 0 700 34 2TCLCL 117 2TCLCL 34 0 0 283 ns 10TCLCL 133 ns SHIFT REGISTER MODE TIMING WAVEFORMS 272335 ±18 AC TESTING INPUT, OUTPUT WAVEFORMS 272335 ±19 AC inputs during testing are driven at VCC 0.5 for a Logic ``1'' and 0.45V for a Logic ``0.'' Timing measurements are made at VIH min for a Logic ``1'' and VIL max for a Logic ``0''. 16 FLOAT WAVEFORMS 272335 ±20 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/V OL level occurs. IOL/I OH 20 mA. 87C51/80C51BH/80C31BH PROGRAMMING THE 87C51 DEFINITION OF TERMS The part must be running with a 4 MHz to 6 MHz oscillator. The address of an EPROM location to be programmed is applied to address lines while the code byte to be programmed in that location is applied to data lines. Control and program signals must be held at the levels indicated in Table 4. Normally EA/V PP is held at logic high until just before ALE/PROG is to be pulsed. The EA/V PP is raised to VPP, ALE/PROG is pulsed low and then EA/V PP is returned to a high (also refer to timing diagrams). ADDRESS LINES: P1.0±P1.7, P2.0±P2.5, P3.4 respectively for A0 ±A14. DATA LINES: P0.0±P0.7 for D0±D7. CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. PROGRAM SIGNALS: ALE/PROG , EA/V PP. NOTE: Exceeding the VPP maximum for any amount of time could damage the device permanently. The VPP source must be well regulated and free of glitches. Table 4. EPROM Programming Modes Mode Program Code Data RST PSEN H L ALE/ PROG P2.6 P2.7 P3.3 P3.6 P3.7 12.75V L H H H H Verify Code Data H L H L L L H H Program Encryption Array Address 0 ±3F H L 12.75V L H H L H Bit 1 H L 12.75V H H H H H Bit 2 H L 12.75V H H H L L Bit 3 H L 12.75V H L H H L H L H L L L L L Program Lock Bits Read Signature Byte H EA/ VPP H 272335 ±21 See Table 4 for proper input on these pins Figure 10. Programming the EPROM 17 87C51/80C51BH/80C31BH 272335 ±22 For compatibility, 25 pulses may be used. Figure 11. Programming Waveforms PROGRAMMING ALGORITHM Refer to Table 4 and Figures 10 and 11 for address, data, and control signals set up. To program the 87C51 the following sequence must be exercised. 1. Input the valid address on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/V PP from VCC to 12.75V 0.25V. 5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and the lock bits. Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached. Program Verify Verification may be done after programming either one byte or a block of bytes. In either case a complete verify of the array will ensure reliable programming of the 87C51. The lock bits cannot be directly verified. Verification of the lock bits is done by observing that their features are enabled. ROM and EPROM Lock System The program lock system, when programmed, protects the onboard program against software piracy. 18 The 80C51BH has a one level program lock system and a 64-byte encryption table. If program protection is desired, the user submits the encryption table with their code and both the lock bit and encryption array are programmed by the factory. The encryption array is not available without the lock bit. For the lock bit to be programmed, the user must submit an encryption table. The 87C51 has a 3-level program lock system and a 64-byte encryption array. Since this is an EPROM device, all locations are user-programmable. See Table 5. Encryption Array Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1's). Every time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed (XNOR) with the code byte, creating an Encryption Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in its original, unmodified form. For programming the Encryption Array, refer to Table 4 (Programming the EPROM). When using the encryption array, one important factor needs to be considered. lf a code byte has the value 0FFH, verifying the byte will produce the encryption byte value. lf a large block ( 64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. For this reason all unused code bytes should be programmed with some value other than 0FFH, and not all of them the same value. This will ensure maximum program protection. 87C51/80C51BH/80C31BH Program Lock Bits The 87C51 has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data. Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to full functionality. Reading the Signature Bytes The 87C51 and 80C51BH have 3 signature bytes in locations 30H, 31H, and 60H. To read these bytes follow the procedure for EPROM verify, but activate the control lines provided in Table 4 for Read Signature Byte. Location Device 30H All Contents 89H 31H All 58H 60H 87C51 51H 80C51BH 11H Erasure Characteristics (Windowed Devices Only) Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2. Exposing the EPROM to an ultraviolet lamp of 12,000 W/cm 2 rating for 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1's state. Table 5. Program Lock Bits and the Features Program Lock Bits Protection Type LB1 LB2 LB3 1 U U U No program lock features enabled. (Code verify will still be encrypted by the encryption array if programmed.) 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled. 19 87C51/80C51BH/80C31BH EPROM PROGRAMMING, EPROM AND ROM VERIFICATION CHARACTERISTICS: (TA 21 C to 27 C, VCC Symbol 5V 10%, VSS 0V) Parameter Min VPP Programming Supply Voltage IPP Programming Supply Current 1/TCLCL Oscillator Frequency TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold After PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold After PROG 48TCLCL TEHSH P2.7 (ENABLE) High to VPP 48TCLCL Max 12.5 4 Units 13.0 V 75 mA 6 MHz TSHGL VPP Setup to PROG Low 10 s TGHSL VPP Hold After PROG 10 s TGLGH PROG Width 90 TAVQV Address to Data Valid TELQV ENABLE Low to Data Valid TEHQZ Data Float After ENABLE 0 TGHGL PROG High to PROG Low 10 110 s 48TCLCL 48TCLCL 48TCLCL s EPROM PROGRAMMING, EPROM AND ROM VERIFICATION WAVEFORMS 272335 ±23 For programming conditions see Figure 10. 5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits. 20