96D4-32G2400ER-AT

Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com Rev. Date: Apr. 21, 2016 ATP A4B32QB4BNRCSE 32GB DDR4-2400 REGISTERED ECC DIMM DESCRIPTION The ATP A4B32QB4BNRCSE is a high performance 32GB DDR4-2400 Registered ECC SDRAM memory module. It is organized as 4096M x 72 in a 288-pin Dual-In-Line Memory Module (DIMM) package. The module utilizes thirty-six 2048Mx4 DDR4 SDRAMs in FBGA package. The module consists of a 512-byte serial EEPROM, which contains the module configuration information. KEY FEATURES                      High Density: 32GB (4096M x 72) DIMM Rank: 2 Rank Cycle Time: 0.83ns (1200MHz) CAS Latency: 17 Power supply: VDD=1.2V ± 0.06V VPP=2.5V± 0.125V VDDSPD=2.2V~3.6V Support ECC error detection and correction Nominal and dynamic on-die termination(ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion(DBI) for data bus 16 internal banks(x4); 4 groups of 4 banks each Internal self calibration through ZQ Temperature controlled refresh (TCR) Asynchronous Reset 7.8 s refresh interval at lower than TCASE85°C, 3.9s refresh interval at 85°C < TCASE < 95 °C Support address and command signals parity function Selectable BC4 or BL8 on-the fly(OTF) Dynamic On Die Termination Fly-by topology PCB Height: 1.23 inches(31.25mm) Minimum Thickness of Golden Finger: 30 Micro-inch RoHS compliant Part No. A4B32QB4BNRCSE Max Freq 1200MHz (0.83ns@CL=17) x2 Your Ultimate Memory Solution! Page 1 of 12 Interface POD12 ATP A4B32QB4BNRCSE PIN DESCRIPTION Pin Name A0~A17 A10/AP A12/BC_n BA0,BA1 BG0,BG1 RAS_n CAS_n WE_n CS0_n CK0_t CK0_c C0~C2 CKE0 ODT0 ACT_n DQ0~DQ63 CB0~CB7 DQS0_t~DQS8_t DQS0_c~DQS8_c SCL SDA SA0~SA2 PARITY VDD VPP VREFCA VSS VDDSPD ALERT_n RESET_n EVENT_n VTT VDDQ ZQ NC NF RFU Description Address Inputs Address Input/Auto precharge Address Input/Burst chop SDRAM Bank Address Bank group address inputs Row address strobe input Column address strobe input Write enable input Chip Selects Clock Inputs, positive line Clock Inputs, negative line Chip ID Clock Enables On-die termination control lines input Command input: ACT_n indicates an ACTIVATE command. Data Input /Output Data check bits Input/Output Data strobes Data strobes, negative line Serial clock for temperature sensor/SPD EEPROM SPD Data Input /Output Serial address inputs Parity for command and address Power supply DRAM activating power supply Reference voltage for control, command, and address pins. Ground SPD Power Alert output Active LOW asynchronous reset Temperature sensor Event Output SDRAM I/O termination supply DRAM DQ power supply Reference ball for ZQ calibration No Connect No function Reserved for future use Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 2 of 12 ATP A4B32QB4BNRCSE PIN ASSIGNMENT No. Designation No. Designation No. Designation No. Designation 1 NC 145 NC 74 CK0_t 218 CK1_t 2 VSS 146 VREFCA 75 CK0_c 219 CK1_c 3 DQ4 147 VSS 76 VDD 220 VDD 4 VSS 148 DQ5 77 VTT 221 VTT 5 DQ0 149 VSS 6 VSS 150 DQ1 78 EVENT_n 7 TDQS9_t, DQS9_t 151 VSS 79 8 TDQS9_c, DQS9_c 152 DQS0_c 80 KEY 222 PARITY A0 223 VDD VDD 224 BA1 9 VSS 153 DQS0_t 81 BA0 225 A10/AP 10 DQ6 154 VSS 82 RAS_n/A16 226 VDD 11 VSS 155 DQ7 83 VDD 227 RFU 12 DQ2 156 VSS 84 S0_n 228 WE_n /A14 13 VSS 157 DQ3 85 VDD 229 VDD 14 DQ12 158 VSS 86 CAS_n/A15 230 NC 15 VSS 159 DQ13 87 ODT0 231 VDD 16 DQ8 160 VSS 88 VDD 232 A13 17 VSS 161 DQ9 89 S1_n 233 VDD 18 TDQS10_t, DQS10_t 162 VSS 90 VDD 234 A17 19 TDQS10_c, DQS10_c 163 DQS1_c 91 ODT1 235 NC,C2 20 VSS 164 DQS1_t 92 VDD 236 VDD 21 DQ14 165 VSS 93 C0,CS2_n,NC 237 NC,CS3_c,C1 22 VSS 166 DQ15 94 VSS 238 SA2 23 DQ10 167 VSS 95 DQ36 239 VSS 24 VSS 168 DQ11 96 VSS 240 DQ37 25 DQ20 169 VSS 97 DQ32 241 VSS 26 VSS 170 DQ21 98 VSS 242 DQ33 27 DQ16 171 VSS 99 TDQS13_t, DQS13_t 243 VSS 28 VSS 172 DQ17 100 TDQS13_c, DQS13_c 244 DQS4_c 29 TDQS11_t, DQS11_t 173 VSS 101 VSS 245 DQS4_t 30 TDQS11_c, DQS11_c 174 DQS2_c 102 DQ38 246 VSS 31 VSS 175 DQS2_t 103 VSS 247 DQ39 32 DQ22 176 VSS 104 DQ34 248 VSS DQ35 33 VSS 177 DQ23 105 VSS 249 34 DQ18 178 VSS 106 DQ44 250 VSS 35 VSS 179 DQ19 107 VSS 251 DQ45 36 DQ28 180 VSS 108 DQ40 252 VSS 37 VSS 181 DQ29 109 VSS 253 DQ41 38 DQ24 182 VSS 110 TDQS14_t, DQS14_t 254 VSS 39 VSS 183 DQ25 111 TDQS14_c, DQS14_c 255 DQS5_c 40 TDQS12_t, DQS12_t 184 VSS 112 VSS 256 DQS5_t 41 TDQS12_c, DQS12_c 185 DQS3_c 113 DQ46 257 VSS Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 3 of 12 ATP A4B32QB4BNRCSE No. Designation No. Designation No. Designation No. Designation 42 VSS 186 DQS3_t 114 VSS 258 DQ47 43 DQ30 187 VSS 115 DQ42 259 VSS 44 VSS 188 DQ31 116 VSS 260 DQ43 45 DQ26 189 VSS 117 DQ52 261 VSS 46 VSS 190 DQ27 118 VSS 262 DQ53 47 CB4 191 VSS 119 DQ48 263 VSS 48 VSS 192 VB5 120 VSS 264 DQ49 49 CB0 193 VSS 121 TDQS15_t, DQS15_t 265 VSS 50 VSS 194 CB1 122 TDQS15_c, DQS15_c 266 DQS6_c 51 TDQS17_t, DQS17_t 195 VSS 123 VSS 267 DQS6_t 52 TDQS17_c, DQS17_c 196 DQS8_c 124 DQ54 268 VSS DQ55 53 VSS 197 DQS8_t 125 VSS 269 54 CB6 198 VSS 126 DQ50 270 VSS 55 VSS 199 VB7 127 VSS 271 DQ51 56 CB2 200 VSS 128 DQ60 272 VSS 57 VSS 201 CB3 129 VSS 273 DQ61 58 RESET_n 202 VSS 130 DQ56 274 VSS 59 VDD 203 CKE1 131 VSS 275 DQ57 60 CKE0 204 VDD 132 TDQS16_t, DQS16_t 276 VSS 61 VDD 205 RFU 133 TDQS16_c, DQS16_c 277 DQS7_c 62 ACT_n 206 VDD 134 VSS 278 DQS7_t 63 BG0 207 BG1 135 DQ62 279 VSS 64 VDD 208 ALERT_n 136 VSS 280 DQ63 65 A12/BC_n 209 VDD 137 DQ58 281 VSS 66 A9 210 A11 138 VSS 282 DQ59 67 VDD 211 A7 139 SA0 283 VSS 68 A8 212 VDD 140 SA1 284 VDDSPD 69 A6 213 A5 141 SCL 285 SDA 70 VDD 214 A4 142 VPP 286 VPP 71 A3 215 VDD 143 VPP 287 VPP 72 A1 216 A2 144 RFU 288 VPP 73 VDD 217 VDD Note: 1. VPP is 2.5V DC Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 4 of 12 ATP A4B32QB4BNRCSE FUNCTIONAL BLOCK DIAGRAM (PART1 OF 3) BG[0:1] BG[0:1]A -> BG[0:1]: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 BG[0:1]B -> BG[0:1]: SDRAMs U[4:7], U[13:16], U[22:25], U[31:34] BA[0:1] BA[0:1]A -> BA[0:1]: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 BA[0:1]B -> BA[0:1]: SDRAMs U[4:7], U[13:16], U[22:25], U[31:34] A0-A17 ACT_n C[0:2] PARITY CKE0 R E G I S T E R CKE1 ODT0 ODT1 CS0_n CS1_n A[0:17]A->A[0:17]: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 A[0:17]B->A[0:17]: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 ACTA_n -> ACT_n: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 ACTB_n -> ACT_n: SDRAMs U[4:7], U[13:16], U[22:25], U[31:34] C[2:0]A -> C[2:0]: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 C[2:0]B -> C[2:0]: SDRAMs U[4:7], U[13:16], U[22:25], U[31:34] PARA -> PAR: SDRAMs U[0:3], U[8:12], U[17:21], U[26:30], U35 PARB -> PAR: SDRAMs U[4:7], U[13:16], U[22:25], U[31:34] CKE0A -> CKE: SDRAMs U[0:3], U[8:12], U18 CKE0B -> CKE: SDRAMs U[4:7], U[13:16] CKE1A -> CKE: SDRAMs U[18:21], U[26:30], U35 CKE1B -> CKE: SDRAMs U[22:25], U[31:34] ODT0A -> ODT: SDRAMs U[0:3], U[8:12], U18 ODT0B -> ODT: SDRAMs U[4:7], U[13:16] ODT1A -> ODT: SDRAMs U[18:21], U[26:30], U35 ODT1B -> ODT: SDRAMs U[4:7], U[13:16] CS0A_n -> CS_n: SDRAMs U[0:3], U[8:12], U18 CS0B_n -> CS_n: SDRAMs U[4:7], U[13:16] CS1A_n -> CS_n: SDRAMs U[18:21], U[26:30], U35 CS1B_n -> CS_n: SDRAMs U[4:7], U[13:16] CK0_t Y0_t -> CK_t: SDRAMs U[4:7], U[22:25] Y1_t -> CK_t: SDRAMs U[0:3], U8, U[18:21], U26 Y2_t -> CK_t: SDRAMs U[13:16], U[31:34] Y3_t -> CK_t: SDRAMs U[9:12], U17, U[27:30], U35 CK0_c Y0_c -> CK_c: SDRAMs Y1_c -> CK_c: SDRAMs Y2_c -> CK_c: SDRAMs Y3_c -> CK_c: SDRAMs CK1_t U[4:7], U[22:25] U[0:3], U8, U[18:21], U26 U[13:16], U[31:34] U[9:12], U17, U[27:30], U35 CK1_c RESET_n QRST_n -> RESET_n: All SDRAMs ALERT_n ERROR_IN_n