96D4-8G2666ER-AT

Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com Rev. Date: Apr. 10, 2017 ATP A4B08QD8BNTDSE 8GB DDR4-2666 REGISTERED ECC DIMM DESCRIPTION The ATP A4B08QD8BNTDSE is a high performance 8GB DDR4-2666 Registered ECC SDRAM memory module. It is organized as 1024M x 72 in a 288-pin Dual-In-Line Memory Module (DIMM) package. The module utilizes nine 1024Mx8 DDR4 SDRAMs in FBGA package. The module consists of a 512-byte serial EEPROM, which contains the module configuration information. KEY FEATURES                      High Density: 8GB (1024M x 72) DIMM Rank: 1 Rank Cycle Time: 0.75ns (1333MHz) CAS Latency: 19(DDR4-2666),17(DDR4-2400),15(DDR4-2133) Power supply: VDD=1.2V ± 0.06V VPP=2.5V± 0.125V VDDSPD=2.2V~3.6V Support ECC error detection and correction Nominal and dynamic on-die termination(ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion(DBI) for data bus 16 internal banks(x8); 4 groups of 4 banks each Internal self calibration through ZQ Temperature controlled refresh (TCR) Asynchronous Reset 7.8 s refresh interval at lower than TCASE85°C, 3.9s refresh interval at 85°C < TCASE < 95 °C Support address and command signals parity function Selectable BC4 or BL8 on-the fly(OTF) Dynamic On Die Termination Fly-by topology PCB Height: 1.23 inches(31.25mm) Minimum Thickness of Golden Finger: 30 Micro-inch RoHS compliant Part No. A4B08QD8BNTDSE Max Freq 1333MHz (0.75ns@CL=19) x2 Your Ultimate Memory Solution! Page 1 of 10 Interface POD12 ATP A4B08QD8BNTDSE PIN DESCRIPTION Pin Name A0~A16 A10/AP A12/BC_n BA0,BA1 BG0,BG1 RAS_n CAS_n WE_n CS0_n CK0_t CK0_c CKE0 C0~C2 ODT0 ACT_n DQ0~DQ63 CB0~CB7 DQS0_t~DQS8_t DQS0_c~DQS8_c TDQS9_t~TDQS17_t TDQS9_c~TDQS17_c SCL SDA SA0~SA2 PARITY VDD VPP VREFCA VSS VDDSPD ALERT_n RESET_n EVENT_n VTT VDDQ ZQ NC NF RFU Description Address Inputs Address Input/Auto precharge Address Input/Burst chop SDRAM Bank Address Bank group address inputs Row address strobe input Column address strobe input Write enable input Chip Selects Clock Inputs, positive line Clock Inputs, negative line Clock Enables Chip ID On-die termination control lines input Command input: ACT_n indicates an ACTIVATE command. Data Input /Output Data check bits Input/Output Data strobes Data strobes, negative line Termination Data Strobe Termination Data Strobe, negative line Serial clock for temperature sensor/SPD EEPROM SPD Data Input /Output Serial address inputs Parity for command and address Power supply DRAM activating power supply Reference voltage for control, command, and address pins. Ground SPD Power Alert output Active LOW asynchronous reset Temperature sensor Event Output SDRAM I/O termination supply DRAM DQ power supply Reference ball for ZQ calibration No Connect No function Reserved for future use Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 2 of 10 ATP A4B08QD8BNTDSE PIN ASSIGNMENT No. Designation No. Designation No. Designation No. Designation 1 12V 145 12V 74 CK0_t 218 CK1_t 2 VSS 146 VREFCA 75 CK0_c 219 CK1_c 3 DQ4 147 VSS 76 VDD 220 VDD 4 VSS 148 DQ5 77 VTT 221 VTT 5 DQ0 149 VSS 6 VSS 150 DQ1 78 EVENT_n 222 PARITY 7 DQS9_t, DM0_n, DBI0_n, TDQS9_t 151 VSS 79 A0 223 VDD 8 TDQS9_c, DQS9_c 152 DQS0_c 80 VDD 224 BA1 KEY 9 VSS 153 DQS0_t 81 BA0 225 A10/AP 10 DQ6 154 VSS 82 RAS_n/A16 226 VDD 11 VSS 155 DQ7 83 VDD 227 RFU 12 DQ2 156 VSS 84 S0_n 228 WE_n /A14 13 VSS 157 DQ3 85 VDD 229 VDD 14 DQ12 158 VSS 86 CAS_n/A15 230 Save_n,NC 15 VSS 159 DQ13 87 ODT0 231 VDD 16 DQ8 160 VSS 88 VDD 232 A13 17 VSS 161 DQ9 89 S1_n 233 VDD 18 DQS10_t, DM1_n, DBI1_n, TDQS10_t 162 VSS 90 VDD 234 A17,NC 19 TDQS10_c, DQS10_c 163 DQS1_c 91 ODT1 235 C2, NC 20 VSS 164 DQS1_t 92 VDD 236 VDD 21 DQ14 165 VSS 93 S2_n, C0 237 S3_n, C1 22 VSS 166 DQ15 94 VSS 238 SA2 23 DQ10 167 VSS 95 DQ36 239 VSS 24 VSS 168 DQ11 96 VSS 240 DQ37 25 DQ20 169 VSS 97 DQ32 241 VSS 26 VSS 170 DQ21 98 VSS 242 DQ33 27 DQ16 171 VSS 99 DQS13_t, DM4_n, DBI4_n, TDQS13_t 243 VSS VSS 28 172 DQ17 100 TDQS13_c, DQS13_c 244 DQS4_c 29 DQS11_t, DM2_n, DBI2_n, TDQS11_t 173 VSS 101 VSS 245 DQS4_t 30 TDQS11_c, DQS11_c 174 DQS2_c 102 DQ38 246 VSS 31 VSS 175 DQS2_t 103 VSS 247 DQ39 32 DQ22 176 VSS 104 DQ34 248 VSS 33 VSS 177 DQ23 105 VSS 249 DQ35 34 DQ18 178 VSS 106 DQ44 250 VSS DQ45 35 VSS 179 DQ19 107 VSS 251 36 DQ28 180 VSS 108 DQ40 252 VSS 37 VSS 181 DQ29 109 VSS 253 DQ41 38 DQ24 182 VSS 110 DQS14_t, DM5_n, DBI5_n, TDQS14_t 254 VSS 39 VSS 183 DQ25 111 TDQS14_c, DQS14_c 255 DQS5_c Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 3 of 10 ATP A4B08QD8BNTDSE No. Designation No. Designation No. Designation No. Designation 40 DQS12_t, DM3_n, DBI3_n, TDQS12_t 184 VSS 112 VSS 256 DQS5_t 41 TDQS12_c, DQS12_c 185 DQS3_c 113 DQ46 257 VSS 42 VSS 186 DQS3_t 114 VSS 258 DQ47 43 DQ30 187 VSS 115 DQ42 259 VSS 44 VSS 188 DQ31 116 VSS 260 DQ43 45 DQ26 189 VSS 117 DQ52 261 VSS 46 VSS 190 DQ27 118 VSS 262 DQ53 47 CB4,NC 191 VSS 119 DQ48 263 VSS 48 VSS 192 CB5,NC 120 VSS 264 DQ49 49 CB0,NC 193 VSS 121 265 VSS VSS 194 CB1,NC 122 DQS15_t, DM6_n, DBI6 n, TDQS15 t TDQS15_c, DQS15_c 266 DQS6_c 195 VSS 123 VSS 267 DQS6_t 196 DQS8_c 124 DQ54 268 VSS DQ55 50 51 52 DQS17_t, DM8_n, DBI8 n, TDQS17 t TDQS17_c, DQS17_c 53 VSS 197 DQS8_t 125 VSS 269 54 CB6,NC 198 VSS 126 DQ50 270 VSS 55 VSS 199 CB7,NC 127 VSS 271 DQ51 56 CB2,NC 200 VSS 128 DQ60 272 VSS 57 VSS 201 CB3,NC 129 VSS 273 DQ61 58 RESET_n 202 VSS 130 DQ56 274 VSS 59 VDD 203 CKE1 131 VSS 275 DQ57 60 CKE0 204 VDD 132 DQS16_t, DM7_n, DBI7_n, TDQS16_t 276 VSS 61 VDD 205 RFU 133 TDQS16_c, DQS16_c 277 DQS7_c 62 ACT_n 206 VDD 134 VSS 278 DQS7_t 63 BG0 207 BG1 135 DQ62 279 VSS 64 VDD 208 ALERT_n 136 VSS 280 DQ63 65 A12 209 VDD 137 DQ58 281 VSS 66 A9 210 A11 138 VSS 282 DQ59 67 VDD 211 A7 139 SA0 283 VSS 68 A8 212 VDD 140 SA1 284 VDDSPD 69 A6 213 A5 141 SCL 285 SDA 70 VDD 214 A4 142 VPP 286 VPP 71 A3 215 VDD 143 VPP 287 VPP 72 A1 216 A2 144 RFU 288 VPP 73 VDD 217 VDD Note: 1. VPP is 2.5V DC Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 4 of 10 ATP A4B08QD8BNTDSE FUNCTIONAL BLOCK DIAGRAM Note: The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 5 of 10 ATP A4B08QD8BNTDSE ABSOLUTE MAXIMUM DC RATINGS Item Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VPP pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Operating Temperature Symbol VDD VDDQ VPP VIN, VOUT TSTG TCASE Rating -0.4V ~ 1.5V -0.4V ~ 1.5V -0.4V ~ 3.0V -0.4V ~ 1.975V -55 to +100 0 to +95 Units V V V V o C o C Notes 1,3 1,3 4 1 1,2 1,2 Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV 4. VPP must be equal or greater than VDD/VDDQ at all times. AC & DC OPERATING CONDITIONS Recommended operating conditions Item Supply Voltage 1,2,3 Supply Voltage for Output 1,2,3 DRAM Activating Power Supply3 Input reference voltage command/ address bus Termination reference voltage (DC) – command/address bus4 Input High Voltage (DC) Input Low Voltage (DC) Input High Voltage (AC) Input Low Voltage (AC) Symbol VDD VDDQ VPP Min. 1.14 1.14 2.375 Typical 1.2 1.2 2.5 Max. 1.26 1.26 2.75 Units V V V VREFCA(DC) TBD TBD TBD V VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) 0.49 * VDD20mA TBD TBD TBD - 0.50 * VDD - 0.51 * VDD+ 20mA TBD TBD TBD Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz. 4. VTT termination voltages in excess of specification limit will adversely affect command and address signals' voltage margins, and reduce timing margins. RELIABILITY MTBF @25 oC (Hours) 1 FIT @ 25 oC 2 MTBF @40 oC (Hours) 1 FIT @ 40 oC2 7,609,000 135 3,802,000 270 Note: 1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual components in the module. It assumes nominal voltage, with all other parameters within specified range. 2. Failures per Billion Device-Hours Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 6 of 10 V V V V V ATP A4B08QD8BNTDSE IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART1 OF 2) Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’ s component data sheet) Symbol Proposed Conditions Value Units 620 mA 36 mA 840 mA 520 mA 540 mA 320 mA 500 mA 610 mA 27 mA 370 mA 1,400 mA Operating One Bank Active-Precharge Current (AL=0) IDD0 IPP0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern Operating One Bank Active-Precharge IPP Current Same condition with IDD0 Operating One Bank Active-Read-Precharge Current (AL=0) IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling; DM_n: sta-ble at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern Precharge Standby Current (AL=0) IDD2N CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according ; Pattern Details: Refer to Component Datasheet for detail pattern Precharge Power-Down Current IDD2P CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 IDD2Q CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 Precharge Quiet Standby Current Active Standby Current IDD3N IPP3N CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:Refer to Component Datasheet for detail pattern Active Standby IPP Current Same condition with IDD3N Active Power-Down Current IDD3P CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 Operating Burst Read Current IDD4R CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 82; AL: 0; CS_n: High between RD; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one according ; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 7 of 10 ATP A4B08QD8BNRCSE IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART2 OF 2) Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’ s component data sheet) Symbol Proposed Conditions Value Units 1,250 mA 2,220 mA 162 mA 230 mA 320 mA 180 mA 220 mA 1,740 mA 81 mA Operating Burst Write Current IDD4W CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern Burst Refresh Current (1X REF) IDD5B IPP5B CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B Self Refresh Current: Normal Temperature Range IDD6N TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL Self-Refresh Current: Extended Temperature Range) IDD6E TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL Self-Refresh Current: Reduced Temperature Range IDD6R TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL Auto Self-Refresh Current IDD6A TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4;Partial Array Self-Refresh (PASR): Full Array; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL Operating Bank Interleave Read Current IDD7 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern IPP7 Operating Bank Interleave Read IPP Current IDD8 Maximum Power Down Current 110 mA Power Consumption per DIMM 2,664 mW PDIMM Same condition with IDD7 System is operating at 1200MHz clock with VDD = 1.2V. This parameter is calculated at a common loading. Your Ultimate Memory Solution! Page 8 of 10 ATP A4B08QD8BNTDSE TIMING PARAMETER Parameter Symbol Clock cycle time at CL=17, CWL=12 Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACTIVE to PRECHARGE command period Average clock high pulse width Average clock low pulse width DQS, DQS to DQ skew, per group, per access DQ output hold time from DQS, DQS DQ low-impedance time from CK, CK DQ high-impedance time from CK, CK DQS, DQS READ Preamble DQS, DQS differential READ Postamble DQS, DQS output high time DQS, DQS output low time DQS, DQS WRITE Preamble DQS, DQS WRITE Postamble DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from RL+BL/2) DQS, DQS differential input low pulse width DQS, DQS differential input high pulse width DQS, DQS rising edge to CK, CK rising edge DQS, DQS falling edge setup time to CK, CK rising edge DQS, DQS falling edge hold time to CK, CK rising edge DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write trans-action to internal read command for different bank group Delay from start of internal write trans-action to internal read command for same bank group WRITE recovery time Mode Register Set command cycle time Mode Register Set command update delay CAS to CAS command delay for same bank group CAS to CAS command delay for different bank group Auto precharge write recovery + precharge time Multi-Purpose Register Recovery Time ACTIVE to ACTIVE command delay to same bank group for 1KB page size Four activate window for 1KB page size Command and Address setup time to CK, CK referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK referenced to Vih(ac) / Vil(ac) levels Power-up and RESET calibration time Normal operation Full calibration time Normal operation short calibration time Exit Reset from CKE HIGH to a valid command Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT dynamic change skew 8Gb REFRESH to REFRESH OR REFRESH to ACTIVE command interval Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C) Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C) Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL Power Down Entry to Exit Timing Write leveling output delay Write leveling output error Note: 1. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 9 of 10 tCK tAA tRCD tRP tRC tRAS tCH(avg) tCL(avg) tDQSQ tQH tLZ(DQ) tHZ(DQ) tRPRE tRPST tQSH tQSL tWPRE tWPST tLZ(DQS) tHZ(DQS) tDQSL tDQSH tDQSS tDSS tDSH tDLLK tRTP tWTR_S tWTR_L tWR tMRD tMOD tCCD_L tCCD_S tDAL tMPRR tRRD tFAW tIS(base) tIH(base) tZQinit tZQoper tZQCS tXPR DDR4-2666 Min Max 0.75