96SD1I-1G400NN-IN1

DDR W/T SODIMM Approval Sheet Customer Product Number M1SF-1GMCX103-JA61 Module speed PC-3200 Pin 200 pin CAS Latency CL-3 SDRAM Operating Temp -20 ℃ ~ 85 ℃ SDRAM Information Micron 64Mx8 Date 23 May 2017 rd Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 1. Features Key Parameter Data Rate MT/s Industry Speed Nomenclature Grade CL=2 CL=2.5 PC-3200 F 266 333 • JEDEC Standard 200-pin Small Outline Dual tRCD tRP tRC CL=3 (ns) (ns) (ns) 400 15 15 55 • Auto Refresh (CBR) and Self Refresh In-Line Memory Module Modes support. • Intend for 400 MHz applications • Serial Presence Detect with EEPROM • Inputs and Outputs are SSTL-2 compatible • Operation Temperature Rating • VDD=VDDQ= 2.6 Volt ± 0.1 (PC-3200) - • Differential clock input (-20°C ≤ TA ≤ +85°C) • Programmable Device Operation: • DLL aligns DQ and DQS transition with CK - transition Burst Type: Sequential or Interleave • Bi-Directional data strobe with one clock cycle - Device CAS# Latency: 2,2.5 and 3 • Built with 512Mb DDR SDRAMs - Burst Length: 2, 4 or 8 • RoHS Compliant (Section 13) 2 Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 2. Environmental Requirements iDIMM are intended for use in standard office environments that have limited capacity for heating and air conditioning. Symbol Parameter Rating Units Notes TOPR Operating Temperature (ambient) -20 to +85 °C 1 TSTG Storage Temperature -50 to +100 °C 1 HOPR Operating Humidity (relative) 10 to 90 % 2 HSTG Storage Humidity (without condensation) 5 to 95 % 2 PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 2,3 1. The component maximum case temperature (Tcase) shall not exceed the value specified in the DDR DRAM component specification. 2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3. Up to 9850 ft. Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 3. Ordering Information DDR W/T SODIMM Part Number Density M1SF-1GMCX103-JA61 1GB DIMM Number Number Organization of DRAM of rank 128M x64 16 2 Speed PC-3200 ECC N/A Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 4. Pin Assignments and Descriptions Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 5. Architecture Pin Definition Pin Name Description Pin Name Description CK0 – CK1 A0 - A13 SDRAM address bus (A14 or A15) Differential SDRAM Clocks CK0# - CK1# BA0 - BA1 SDRAM Bank Address Inputs SCL SDRAM row address strobe SDA Serial Presence Detect Clock Input (or BA2) Serial Presence Detect Data RAS# input/output Serial Presence Detect Address CAS# SDRAM column address strobe SA0 – SA2 Inputs WE# SDRAM write enable VDD Power Supply S0# - S1# DIMM Rank Select Lines VDDID VDD Identification Flag CK0 – CKE1 SDRAM clock enable lines VDDQ SDRAM I/O Driver power supply DQ0 – DQ63 DIMM memory data bus VREF SDRAM I/O Reference supply DIMM ECC check bit VSS Ground CB0 – CB7 Serial EEPROM positive power DQS0 – DQS17 SDRAM data strobes VDDSPD supply DM0 – DM7 NC SDRAM data masks Reset Reset enable Spare Pin Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 6. Function Block Diagram: - (1GB, 2 Ranks, 64Mx8 DDR SDRAM base SODIMM) Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 7. Absolute Maximum Ratings Symbol Rating Units Operation Temperature -20 to 85 °C Storage Temperature -50 to 100 °C VINPUT Voltage input pins relative to Vss -1.0 to +3.6 V VIO Voltage on I/O pins relative to Vss -0.5 to +3.6 V VDD Voltage on VDD supply relative to Vss -1.0 to +3.6 V Voltage on VDDQ supply relative to Vss -1.0 to +3.6 V 50 mA TA TSTG VDDQ IOS Note: Parameter Output short Circuit Current Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 8. AC & DC Operating Conditions - AC Operating Conditions Value Symbol Parameter Units Min Max Notes VIH (AC) Input High (Logic1) Voltage VREF + 0.31 - V VIL (AC) Input Low (Logic0) Voltage - VREF + 0.31 V VID (AC) Input differential Voltage: CK, /CK 0.7 VDDQ + 0.6 V 1 VIX (AC) Input crossing point Voltage: CK, /CK 0.5* VDDQ + 0.2 0.5* VDDQ - 0.2 V 2 Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 8 Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM - DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Typ. Max Units Supply Voltage (DDR266,333) 2.3 2.5 2.7 V Supply Voltage (DDR400) 2.5 2.6 2.7 V Supply Voltage (DDR266,333) 2.3 2.5 2.7 V Supply Voltage (DDR400) 2.5 2.6 2.7 V Notes VDD VDDQ VIH (DC) Input High (Logic1) Voltage VIL (DC) Input Low (Logic0) Voltage VTT VREF Termination Voltage I/O Reference Voltage VREF + 0.15 - VDDQ + 0.3 V 1 -0.3 - VREF - 0.15 V 1 VREF-0.04 VREF VREF+0.04 V 3 0.49VDDQ 0.5VDDQ 0.51VDDQ V 2 VIN(DC) Input Voltage Level: CK, /CK -0.3 - VDDQ + 0.3 V VID(DC) Input Differential Voltage: CK, /CK 0.36 - VDDQ + 0.6 V V-I Matching 0.71 - 1.4 VI(RATIO) V Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Rev 1.0 May 2017 2008© InnoDisk Corp. All rights reserved InnoDisk Corp. reserves the right to change the Products and Specification without notices. DDR W/T SODIMM 9. Operating, Standby, and Refresh Currents - 1GB SODIMM (2 Rank, 64Mx8 DDR SDRAMs) Symbol Parameter/Condition PC-3200 Unit 1200 mA 1360 mA 80 mA 368 mA 288 mA 640 mA 1920 mA 1920 mA 1920 mA 80 mA 3680 mA One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing I DD0 twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address I DD1 and control inputs changing once per clock cycle I DD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once I DD2F per clock cycle.VIN=VREF for DQ, DQS and DM I DD3P One bank active ; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge;tRC=tRAS(max); tCK=tCK(min); DQ, DM I DD3N and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once I DD4R per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once I DD4W per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for I DD5 DDR266A & DDR266B at 133Mhz; distributed refresh I DD6 CKE=