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AQD-D3L16R16-SM

AQD-D3L16R16-SM

  • 厂商:

    ADVANTECH(研华)

  • 封装:

    240-RDIMM

  • 描述:

    MODULE DDR3L SDRAM 16GB 240RDIMM

  • 数据手册
  • 价格&库存
AQD-D3L16R16-SM 数据手册
240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Advantech AQD-D3L16R16-SM Datasheet Rev. 1.0 2014-10-14 Transcend Information Inc. 1 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Description Pin Identification DDR3L Registered DIMM is high-speed, low power Symbol memory module that use 1024Mx4bits DDR3L SDRAM in A0~A15, BA0~BA2 FBGA package, 1 pcs register in TFBGA package and a /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /S0, /S1 Chip Selects 2048 bits serial EEPROM on a 240-pin printed circuit board. DDR3L Registered DIMM is a Dual In-Line Function Address Inputs Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the CKE0, CKE1 Clock Enables use of system clock. Data I/O transactions are possible on ODT0, ODT1 On-die termination control both edges of DQS. Range of operation frequencies, DQ0~DQ63 programmable latencies allow the same device to be CB0~CB7 useful for a variety of high bandwidth, high performance Data Input/Output ECC Check bits DQS0~DQS8 Data Strobe memory system applications. /DQS0~/DQS8 Features DM0~DM8 Data Masks  JEDEC standard 1.35V(1.28V~1.45V) Power supply CK0, /CK0 Clocks Input  JEDEC standard 1.5V(1.425V~1.575V) Power supply /RESET Reset Pin  VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) /EVENT Temperature Event Pin  RoHS compliant products.  Clock Freq: 800MHZ for 1600Mb/s/Pin Parity error found on address and /ERROUT  Programmable CAS Latency: 11 control bus  Programmable Additive Latency (Posted /CAS): Parity bit for address and Control Par-In 0,CL-2 or CL-1 clock bus  Programmable /CAS Write Latency (CWL) = 8(DDR3-1600)  8 bit pre-fetch  Burst Length: 4, 8 VDD Core and I/O Power VSS Ground VREFDQ, VREFCA Input/Output Reference  Bi-directional Differential Data-Strobe VTT  Internal calibration through ZQ pin VDDSPD  On Die Termination with ODT pin  Serial presence detect with EEPROM  On DIMM thermal Sensor SPD Clock Input SDA SPD Data NC 2 SPD Power SCL SA0~SA2 Transcend Information Inc. Termination Voltage SPD Address No Connection 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.. Transcend Information Inc. 3 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Pin Assignments Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name 01 VREFDQ 41 VSS 81 DQ32 121 VSS 161 TDQS17 02 VSS 42 /DQS8 82 DQ33 122 DQ4 162 /TDQS17 03 DQ0 43 DQS8 83 VSS 123 DQ5 163 VSS 04 DQ1 44 VSS 84 /DQS4 124 VSS 164 CB6 05 VSS 45 CB2 85 DQS4 125 TDQS9 165 CB7 06 /DQS0 46 CB3 86 VSS 126 /TDQS9 166 VSS 07 DQS0 47 VSS 87 DQ34 127 VSS 167 NC 08 VSS 48 VTT 88 DQ35 128 DQ6 168 /RESET 09 DQ2 49 VTT 89 VSS 129 DQ7 169 CKE1,NC 10 DQ3 50 CKE0 90 DQ40 130 VSS 170 VDD 11 VSS 51 VDD 91 DQ41 131 DQ12 171 A15 12 DQ8 52 BA2 92 VSS 132 DQ13 172 A14 13 DQ9 53 /Err_Out 93 /DQS5 133 VSS 173 VDD 14 VSS 54 VDD 94 DQS5 134 TDQS10 174 A12 15 /DQS1 55 A11 95 VSS 135 /TDQS10 175 A9 16 DQS1 56 A7 96 DQ42 136 VSS 176 VDD 17 VSS 57 VDD 97 DQ43 137 DQ14 177 A8 18 DQ10 58 A5 98 VSS 138 DQ15 178 A6 19 DQ11 59 A4 99 DQ48 139 VSS 179 VDD 20 VSS 60 VDD 100 DQ49 140 DQ20 180 A3 21 DQ16 61 A2 101 VSS 141 DQ21 181 A1 22 DQ17 62 VDD 102 /DQS6 142 VSS 182 VDD 23 VSS 63 NC 103 DQS6 143 TDQS11 183 VDD 24 /DQS2 64 NC 104 VSS 144 /TDQS11 184 CK0 25 DQS2 65 VDD 105 DQ50 145 VSS 185 /CK0 26 VSS 66 VDD 106 DQ51 146 DQ22 186 VDD 27 DQ18 67 VREFCA 107 VSS 147 DQ23 187 /EVENT 28 DQ19 68 Par-In 108 DQ56 148 VSS 188 A0 29 VSS 69 VDD 109 DQ57 149 DQ28 189 VDD 30 DQ24 70 A10/AP 110 VSS 150 DQ29 190 BA1 31 DQ25 71 BA0 111 /DQS7 151 VSS 191 VDD 32 VSS 72 VDD 112 DQS7 152 TDQS12 192 /RAS 33 /DQS3 73 /WE 113 VSS 153 /TDQS12 193 /S0 34 DQS3 74 /CAS 114 DQ58 154 VSS 194 VDD 35 VSS 75 VDD 115 DQ59 155 DQ30 195 ODT0 36 DQ26 76 /S1 116 VSS 156 DQ31 196 A13 37 DQ27 77 117 SA0 157 VSS 197 VDD ODT1,NC 38 VSS 78 VDD 118 SCL 158 CB4 198 /S3,NC 39 CB0 79 /S2,NC 119 SA2 159 CB5 199 VSS 40 CB1 80 VSS 120 VTT 160 VSS 200 DQ36 ODT1, CKE1:Connected to the register on 2 and 4 rank RDIMM ; NC on 1 rank RDIMM /S2, /S3:Connected to the register on 4 rank RDIMM ; NC on 1 or 2 rank RDIMM Transcend Information Inc. 4 Pin No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin Name DQ37 VSS TDQS13 /TDQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS TDQS14 /TQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS TDQS15 /TDQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS TDQS16 /TDQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Block Diagram 16GB, 2Gx72 Module(2 Rank x4) Transcend Information Inc. 5 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Transcend Information Inc. 6 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 C Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. At 0 - 85C, operation temperature range are the temperature which all DRAM specification will be supported. Note 1,2 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.4 ~ 1.975 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.4 ~ 1.975 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1  Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Supply voltage Supply voltage for Output Symbol VDD VDDQ I/O Reference Voltage (DQ) VREFDQ(DC) I/O Reference Voltage (CMD/ADD) VREFCA(DC) AC Input Logic High VIH(AC) AC Input Logic Low VIL(AC) DC Input Logic High VIH(DC) DC Input Logic Low VIL(DC) Transcend Information Inc. Voltage 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 7 Min Typ. Max 1.283 1.425 1.283 1.425 0.49*VDDQ 0.49*VDDQ VREF+0.160 VREF+0.175 VREF+0.09 VREF+0.1 VSS VSS 1.35 1.5 1.35 1.5 0.50*VDDQ 0.50*VDDQ - 1.45 1.575 1.45 1.575 0.51*VDDQ 0.51*VDDQ VREF-0.160 VREF-0.175 VDD VDD VREF-0.09 VREF-0.1 Unit Note s V 1, 2 V 1, 2 V V V 3 3 V V V 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. IDD Specification parameters Definition ( IDD values are for full operating range of Voltage and Temperature) 16GB, 2Gx72 Module(2 Rank x4) Parameter Symbol DDR3 1600 CL11 Unit IDD0 1750 mA IDD1 2020 mA IDD2P 1130 mA IDD2Q 1390 mA IDD2N 1360 mA IDD3P 1310 mA IDD3N 1710 mA IDD4R 2560 mA IDD4W 2650 mA IDD5 3600 mA IDD6 570 mA Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Transcend Information Inc. 8 240Pin DDR3L 1600 RDIMM 16GB Based on 1Gx4 AQD-D3L16R16-SM Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: IDD7 3990 mA 1.Module IDD was calculated on the specific brand DRAM(3X nm) component IDD and can be differently measured according to DQ loading capacitor. Timing Parameters & Specifications Speed Parameter DDR3 1600 Unit Symbol Min Max Average Clock Period tCK 1.25
AQD-D3L16R16-SM 价格&库存

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