AQD-D3L4GN16-MG

240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Advantech AQD-D3L4GN16-MG Datasheet Rev. 1.1 2013-09-30 Advantech 1 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Description Pin Identification AQD-D3L4GN16-MG is a DDR3 Unbuffered DIMM, Symbol Function non-ECC, high-speed, low power memory module that A0~A15, BA0~BA2 Address/Bank input use 8 pcs of 512Mx8bits DDR3 low voltage SDRAM in DQ0~DQ63 Bi-direction data bus FBGA package and a 2048 bits serial EEPROM on a DQS0~DQS7 Data strobes 240-pin printed circuit board. AQD-D3L4GN16-MG is a /DQS0~/DQS7 Differential Data strobes CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) CKE0, CKE1 Clock Enable Input ODT0, ODT1 On-die termination control line on both edges of DQS. Range of operation frequencies, /S0, /S1 DIMM rank select lines programmable latencies allow the same device to be /RAS Row address strobe useful for a variety of high bandwidth, high performance /CAS Column address strobe memory system applications. /WE Write Enable DM0~DM7 Data masks/high data strobes VDD Core power supply  JEDEC standard 1.35V(1.283V~1.45V) Power supply VDDQ I/O driver power supply  JEDEC standard 1.5V(1.425V~1.575V) Power supply VREFDQ I/O reference supply Dual In-Line Memory Module and intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible Features  RoHS compliant products VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Command/address reference VREFCA  Clock Freq: 800MHZ for 1600Mb/s/Pin. supply  Programmable CAS Latency: 6, 7, 8, 9, 10, 11 VDDSPD  Programmable Additive Latency (Posted /CAS): SPD EEPROM power supply I2C serial bus address select for SA0~SA2 0,CL-2 or CL-1 clock EEPROM  Programmable /CAS Write Latency (CWL) SCL I2C serial bus clock for EEPROM  8 bit pre-fetch SDA I2C serial bus data for EEPROM  Burst Length: 4, 8 VSS Ground /RESET Set DRAMs Known State  Internal calibration through ZQ pin VTT SDRAM I/O termination supply  On Die Termination with ODT pin NC No Connection = 8(DDR3-1600)  Bi-directional Differential Data-Strobe  Serial presence detect with EEPROM  Asynchronous reset Advantech 2 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Dimensions (Unit: millimeter) Advantech 3 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Pin Assignments Pin Pin No. name Pin Pin Pin No. name No. Pin Pin Pin name No. name Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS 2 VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DM3 182 VDD 212 DM5 3 DQ0 33 /DQS3 63 CK1(NC) 93 /DQS5 123 DQ5 153 NC 183 VDD 213 NC 4 DQ1 34 DQS3 64 /CK1(NC) 94 DQS5 124 VSS 154 VSS 184 CK0 214 VSS 5 VSS 35 VSS 65 VDD 95 VSS 125 DM0 155 DQ30 185 /CK0 215 DQ46 6 /DQS0 36 DQ26 66 VDD 96 DQ42 126 NC 156 DQ31 186 VDD 216 DQ47 7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 NC 217 VSS 8 VSS 38 VSS 68 NC 98 VSS 128 DQ6 158 NC 188 A0 218 DQ52 9 DQ2 39 NC 69 VDD 99 DQ48 129 DQ7 159 NC 189 VDD 219 DQ53 10 DQ3 40 NC 70 A10(AP) 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS 11 VSS 41 VSS 71 BA0 101 VSS 131 DQ12 161 NC 191 VDD 221 DM6 12 DQ8 42 NC 72 VDD 102 /DQS6 132 DQ13 162 NC 192 /RAS 222 NC 13 DQ9 43 NC 73 /WE 103 DQS6 133 VSS 163 VSS 193 /CS0 223 VSS 14 VSS 44 VSS 74 /CAS 104 VSS 134 DM1 164 NC 194 VDD 224 DQ54 15 /DQS1 45 NC 75 VDD 16 DQS1 46 NC 76 17 VSS 47 VSS 18 DQ10 48 NC 78 VDD 19 DQ11 49 NC 79 20 VSS 50 CKE0 21 DQ16 51 22 DQ17 52 23 VSS 24 /DQS2 25 105 DQ50 135 NC 165 NC 195 ODT0 225 DQ55 /CS1(NC) 106 DQ51 136 VSS 166 VSS 196 A13 226 VSS 77 ODT1(NC) 107 VSS 137 DQ14 167 NC 197 VDD 227 DQ60 108 DQ56 138 DQ15 168 /RESET 198 NC 228 DQ61 NC 109 DQ57 139 VSS 169 CKE1(NC) 199 VSS 229 VSS 80 VSS 110 VSS 140 DQ20 170 VDD 200 DQ36 230 DM7 VDD 81 DQ32 111 /DQS7 141 DQ21 171 A15(NC) 201 DQ37 231 NC BA2 82 DQ33 112 DQS7 142 VSS 172 A14(NC) 202 VSS 232 VSS 53 NC 83 VSS 113 VSS 143 DM2 173 VDD 203 DM4 233 DQ62 54 VDD 84 /DQS4 114 DQ58 144 NC 174 A12 204 NC 234 DQ63 DQS2 55 A11 85 DQS4 115 DQ59 145 VSS 175 A9 205 VSS 235 VSS 26 VSS 56 A7 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD 27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118 SCL 148 VSS 178 A6 208 VSS 238 SDA 29 VSS 59 A4 89 VSS 119 SA2 149 DQ28 179 VDD 209 DQ44 239 VSS 30 DQ24 60 VDD 90 DQ40 120 VTT 150 DQ29 180 A3 210 DQ45 240 VTT Note: 1. 2. Advantech CS1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs CK1,NC and CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated 4 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Block Diagram 4GB, 512Mx64 Module(1 Rank x8) This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. Advantech 5 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 C Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1,2 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.4 ~ 1.975 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.4 ~ 1.975 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1 Storage temperature TSTG -55~+100 C 1,2 Note: 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Parameter Symbol Voltage Rating Min Typ. Max Unit Notes 1.283 1.35 1.45 1.35V V 1.5V 1.425 1.5 1.575 1.35V 1.283 1.35 1.45 V Supply voltage for Output VDDQ 1.5V 1.425 1.5 1.575 I/O Reference Voltage (DQ) 1.35V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V VREFDQ(DC) I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.5V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 1.35V VREF+0.160 V AC Input Logic High VIH(AC) 1.5V VREF+0.175 1.35V VREF-0.160 V AC Input Logic Low VIL(AC) 1.5V VREF-0.175 1.35V VREF+0.09 VDD V DC Input Logic High VIH(DC) 1.5V VREF+0.1 VDD 1.35V VSS VREF-0.09 V DC Input Logic Low VIL(DC) 1.5V VSS VREF-0.1 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. Supply voltage Advantech VDD 6 1, 2 1, 2 3 3 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature) 4GB, 512Mx64 Module(1 Rank x8) Parameter Symbol DDR3 1600 CL11 Unit IDD0 440 mA IDD1 528 mA IDD2P-0 144 mA IDD2P-1 256 mA IDD2Q 256 mA IDD2N 256 mA IDD3P 304 mA IDD3N 304 mA IDD4R 1256 mA IDD4W 1000 mA IDD5B 1240 mA IDD6 160 mA IDD6ET 200 mA IDD7 1760 mA Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Self refresh temperature current (SRT-enabled): MAX TC = 95°C Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1. Advantech Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently measured according to DQ loading capacitor. 7 240Pin DDR3 1.35V 1600 UDIMM 4GB Based on 512Mx8 AQD-D3L4GN16-MG Timing Parameters & Specifications Speed Parameter DDR3 1600 Unit Symbol Min Max Average Clock Period tCK 1.25