AQD-D4U4GE24-SG

288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Advantech AQD-D4U4GE24-SG Datasheet Rev. 1.0 2017-03-13 Advantech 1 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Description DDR4 1.2V ECC Unbuffered DIMM is high-speed, low Pin Identification power memory module that use 512Mx8bits DDR4 Symbol SDRAM in FBGA package and a 4096 bits serial Function A0–A17 Register address input Unbuffered DIMM is a Dual In-Line Memory Module and BA0, BA1 Register bank select input is intended for mounting into 288-pin edge connector BG0, BG1 Register bank group select input RAS_n2 Register row address strobe input CAS_n3 Register column address strobe input on both edges of DQS. Range of operation frequencies, WE_n4 Register write enable input programmable latencies allow the same device to be CS0_n, CS1_n, EEPROM on a 288-pin printed circuit board. DDR4 1.2V sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible DIMM Rank Select Lines input useful for a variety of high bandwidth, high performance CS2_n, CS3_n memory system applications. CKE0, CKE1 Register on-die termination control lines Features ODT0, ODT1  RoHS compliant products input  JEDEC standard 1.2V (1.14V to 1.26V) Power supply  VDDQ=1.2V (1.14V to 1.26V)  Clock Freq: 1200MHZ for 2400Mb/s/Pin  16 Banks (4 Bank Groups)  Programmable CAS Latency: 10, 11, 12, 13, 14,15,16, 17,18  Programmable Additive Latency (Posted /CAS): 0,CL-2 or CL-1 clock  Programmable /CAS Write Latency (CWL) = 12,16 (DDR4-2400) ACT_n Register input for activate input DQ0–DQ63 DIMM memory data bus CB0–CB7 DIMM ECC check bits DQS0_t– Data Buffer data strobes (positive line DQS17_t of differential pair) DQS0_c– Data Buffer data strobes (negative line DQS17_c of differential pair) Register clock input (positive line of CK0_t, CK1_t differential pair)  8 bit pre-fetch Register clocks input (negative line of  Burst Length: 4, 8 CK0_c, CK1_c differential pair)  Bi-directional Differential Data-Strobe  On Die Termination with ODT pin I2C serial bus clock for SPD/TS and SCL  Serial presence detect with EEPROM register  Asynchronous reset I2C serial bus data line for SPD/TS and SDA  PCB: 30µ gold finger Advantech Register clock enable lines input register 2 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG I2C slave address select for SPD/TS SA0–SA2 and register PAR Register parity input VDD SDRAM core power supply VPP SDRAM activating power supply SDRAM command/address reference VREFCA supply VSS Power supply return (ground) VDDSPD Serial SPD/TS positive power supply ALERT_n Register ALERT_n output Set Register and SDRAMs to a Known RESET_n State SPD signals a thermal event has EVENT_n occurred VTT SDRAM I/O termination supply RFU Reserved for future use NC No Connection Advantech 3 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Dimensions (Unit: millimeter) Advantech 4 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Pin Assignments Pin Pin Pin Pin Pin Pin Pin Pin Pin name No. No. name No. name No. name No. 1 NC 145 NC 39 2 VSS 146 VREFCA 40 VSS 183 DQ25 DM3_n, 184 VSS 77 Pin name Pin No. Pin name VTT 221 VTT KEY Pin Pin Pin Pin No. name No. name 114 VSS 258 DQ47 115 DQ42 259 VSS DBI3_n, NC 3 DQ4 147 VSS 41 NC 185 DQS3_c 78 EVENT_n 222 PARITY 116 VSS 260 DQ43 4 VSS 148 DQ5 42 VSS 186 DQS3_t 79 A0 223 VDD 117 DQ52 261 VSS 5 DQ0 149 VSS 43 DQ30 187 VSS 80 VDD 224 BA1 118 VSS 262 DQ53 6 VSS 150 DQ1 44 VSS 188 DQ31 81 BA0 225 A10/AP 119 DQ48 263 VSS DM0_n,DBI0_ 151 VSS 45 DQ26 189 VSS 82 RAS_n/A16 226 VDD 120 VSS 264 DQ49 46 VSS 190 DQ27 83 RFU 121 DM6_n, 265 VSS 7 n, NC 8 NC 152 DQS0_c VDD 227 DBI6_n, NC 9 VSS 153 DQS0_t 47 CB4, NC 191 10 DQ6 154 VSS 48 11 VSS 155 DQ7 49 12 DQ2 156 VSS 50 VSS 13 VSS 157 DQ3 51 DM8_n, VSS VSS 192 CB5, NC CB0, NC 193 VSS 84 CS0_n 85 VDD 228 WE_n/A14 122 NC 266 DQS6_c 229 86 CAS_n/A15 230 VDD 123 VSS 267 DQS6_t NC 124 DQ54 268 VSS 194 CB1, NC 87 ODT0 231 VDD 125 VSS 269 DQ55 195 88 VDD 232 A13 126 DQ50 270 VSS VSS DBI8_n, NC 14 DQ12 158 VSS 52 NC 196 DQS8_c 89 CS1_n 233 VDD 127 VSS 271 DQ51 15 VSS 159 DQ13 53 VSS 197 DQS8_t 90 VDD 234 NC 128 DQ60 272 VSS 16 DQ8 160 VSS 54 VSS 91 ODT1 235 NC 129 VSS 273 DQ61 17 VSS 161 DQ9 55 92 VDD 236 VDD 130 DQ56 274 VSS 18 DM1_n, 162 VSS 56 93 NC 237 NC 131 VSS 275 DQ57 94 VSS 238 SA2 132 DM7_n, 276 VSS CB6, NC 198 VSS 199 CB7, NC CB2, NC 200 VSS DBI1_n, NC 19 NC 163 DQS1_c 57 VSS 201 CB3, NC DBI7_n, NC 20 VSS 164 DQS1_t 58 21 DQ14 165 VSS 59 VDD 22 VSS 166 DQ15 60 23 DQ10 167 VSS 61 Advantech RESET_n 202 VSS 95 DQ36 239 VSS 133 NC 277 DQS7_c 203 CKE1 96 VSS 240 DQ37 134 VSS 278 DQS7_t CKE0 204 VDD 97 DQ32 241 VSS 135 DQ62 279 VSS VDD 205 RFU 98 VSS 242 DQ33 136 VSS 280 DQ63 5 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG 24 VSS 168 DQ11 62 ACT_n 206 VDD 99 DM4_n, 243 VSS 137 DQ58 281 VSS DBI4_n, NC 25 DQ20 169 VSS 63 BG0 207 BG1 100 NC 244 DQS4_c 138 VSS 282 DQ59 26 VSS 170 DQ21 64 VDD 208 ALERT_n 101 VSS 245 DQS4_t 139 SA0 283 VSS 27 DQ16 171 VSS 28 VSS 172 29 DM2_n, 173 65 A12/BC_n 209 VDD 102 DQ38 246 VSS 140 SA1 284 VDDSPD DQ17 66 A9 210 A11 103 VSS 247 DQ39 141 SCL 285 SDA VSS 67 VDD 211 A7 104 DQ34 248 VSS 142 VPP 286 VPP DBI2_n, NC 30 NC 174 DQS2_c 68 A8 212 VDD 105 VSS 249 DQ35 143 VPP 287 VPP 31 VSS 175 DQS2_t 69 A6 213 A5 106 DQ44 250 VSS 144 RFU 288 VPP 32 DQ22 176 VSS 70 VDD 214 A4 107 VSS 251 DQ45 33 VSS 177 DQ23 71 A3 215 VDD 108 DQ40 252 VSS 34 DQ18 178 VSS 72 A1 216 A2 109 VSS 253 DQ41 35 VSS 179 DQ19 73 VDD 217 VDD 110 DM5_n, 254 VSS DBI5_n, NC 36 DQ28 180 VSS 74 CK0_t 218 CK1_t 111 NC 255 DQS5_c 37 VSS 181 DQ29 75 CK0_c 219 CK1_c 112 VSS 256 DQS5_t 38 DQ24 182 VSS 76 VDD 220 VDD 113 DQ46 257 VSS NOTE : 1. Address A17 is only valid for 16 Gb x4 based SDRAMs. 2. RAS_n is a multiplexed function with A16. 3. CAS_n is a multiplexed function with A15. 4. WE_n is a multiplexed function with A14. Advantech 6 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Block Diagram 4GB, 512Mx72 Module(1 Rank x8) This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. Advantech 7 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 85 C 1,2 Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. At 0 - 85C, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1,3 Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1,3 Voltage on VPP pin relative to Vss VPP -0.3 ~ 3.0 V 4 Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1,3 Storage temperature TSTG -55~+100 C 1,2 Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV 4. VPP must be equal or greater than VDD/VDDQ at all times. AC & DC Operating Conditions Recommended DC operating conditions Symbol Parameter Min. 1.14 1.14 2.375 Rating Typ. 1.2 1.2 2.5 Max. 1.26 1.26 2.75 VDD Supply Voltage VDDQ Supply Voltage for Output VPP Peak-to-Peak Voltage NOTE: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz. Unit NOTE V V V 1,2,3 1,2,3 3 Unit NOTE AC & DC Logic Input Levels for Single-Ended Signals Symbol Parameter DDR4-1600/1866/2133/2400 Min. Max. VREFCA+ 0.075 VDD VSS VREFCA-0.075 VREF + 0.1 Note 2 Note 2 VREF - 0.1 0.49*VDD 0.51*VDD VIH.CA(DC75) DC input logic high V VIL.CA(DC75) DC input logic low V VIH.CA(AC100) AC input logic high V 1 VIL.CA(AC100) AC input logic low V 1 VREFCA(DC) Reference Voltage for ADD, CMD inputs V 2,3 NOTE : 1. See “Overshoot and Undershoot Specifications” on section. 2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV) 3. For reference : approx. VDD/2 ± 12mV Advantech 8 288 Pin DDR4 1.2V 2400 ECC UDIMM 4GB Based on 512Mx8 AQD-D4U4GE24-SG Timing Parameters & Specifications Speed Parameter DDR4 2400 Unit Symbol Min Max Average Clock Period tCK 0.833