AQD-D4U4GN21-SG

288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Advantech AQD-D4U4GN21-SG Datasheet Rev. 1.0 2015-03-13 1 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Description Pin Identification Symbol DDR4 Unbuffered DIMM is high-speed, low power memory module that use 512Mx8bits DDR4 SDRAM in FBGA package and a 4Kbits serial EEPROM on a 288-pin printed circuit board. DDR4 Unbuffered DIMM is A0~A17 BA0, BA1 SDRAM address bus SDRAM bank select BG0, BG1 RAS_n SDRAM bank group select SDRAM row address strobe CAS_n WE_n a Dual In-Line Memory Module and is intended for mounting into 288-pin edge connector sockets. Synchronous design allows precise cycle control with the CS0_n, CS1_n CKE0, CKE1 use of system clock. Data I/O transactions are possible ODT0, ODT1 on both edges of DQS. Range of operation frequencies, ACT_n DQ0–DQ63 programmable latencies allow the same device to be CB0–CB7 useful for a variety of high bandwidth, high performance DQS0_t–DQS8_t memory system applications. Function DQS0_c–DQS8_c Features SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines SDRAM on-die termination control lines SDRAM activate DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair)  RoHS compliant products. CK0_t, CK1_t SDRAM clocks (positive line of differential pair)  JEDEC standard 1.2V ± 0.06V power supply CK0_c, CK1_c SDRAM clocks (negative line of differential pair)  VDDQ=1.2V ± 0.06V PARITY VDD  Clock Freq: 1067MHZ for 2133Mb/s/Pin.  Programmable CAS Latency: 10,11,12,13,14,15,16  12 V Programmable Additive Latency (Posted /CAS): VREFCA 0,CL-2 or CL-1 clock VSS  Programmable /CAS Write Latency (CWL) = 11, 14(DDR4-2133)  8 bit pre-fetch  Burst Length: 4, 8 SDRAM parity input SDRAM I/O and core power supply Optional power Supply on socket but not used on UDIMM SDRAM command/address reference supply Power supply return (ground) VDDSPD Serial SPD EEPROM positive power supply SCL SDA I C serial bus clock for EEPROM 2 I C serial bus data line for EEPROM 2 2 SA0–SA2 ALERT_n I C slave address select for EEPROM SDRAM ALERT_n  Serial presence detect with EEPROM VPP RESET_n SDRAM Supply Set DRAMs to a Known State  On DIMM Thermal Sensor EVENT_n  Bi-directional Differential Data-Strobe  On Die Termination with ODT pin  Asynchronous reset 2 VTT SPD signals a thermal event has occurred SDRAM I/O termination supply RFU NC Reserved for future use No Connection 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Dimensions (Unit: millimeter) Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Pin Assignments Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NC VSS DQ4 VSS DQ0 VSS NC NC VSS DQ6 VSS DQ2 VSS DQ12 VSS DQ8 VSS NC NC VSS DQ14 VSS DQ10 VSS DQ20 VSS DQ16 VSS NC NC VSS DQ22 VSS DQ18 VSS DQ28 VSS DQ24 VSS NC NC VSS DQ30 VSS DQ26 VSS NC VSS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NC VSS NC NC VSS NC VSS NC VSS RESET_n VDD CKE0 VDD ACT_n BG0 VDD A12/BC_n A9 VDD A8 A6 VDD A3 A1 VDD CK0_t CK0_c VDD VTT EVENT_n A0 VDD BA0 RAS_n/A16 VDD CS0_n VDD CAS_n/A15 ODT0 VDD CS1_n VDD ODT1 VDD NC VSS DQ36 VSS 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DQ32 VSS NC NC VSS DQ38 VSS DQ34 VSS DQ44 VSS DQ40 VSS NC NC VSS DQ46 VSS DQ42 VSS DQ52 VSS DQ48 VSS NC NC VSS DQ54 VSS DQ50 VSS DQ60 VSS DQ56 VSS NC NC VSS DQ62 VSS DQ58 VSS SA0 SA1 SCL VPP VPP RFU 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 NC VREFCA VSS DQ5 VSS DQ1 VSS DQS0_c DQS0_t VSS DQ7 VSS DQ3 VSS DQ13 VSS DQ9 VSS DQS1_c DQS1_t VSS DQ15 VSS DQ11 VSS DQ21 VSS DQ17 VSS DQS2_c DQS2_t VSS DQ23 VSS DQ19 VSS DQ29 VSS DQ25 VSS DQS3_c DQS3_t VSS DQ31 VSS DQ27 VSS NC 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 VSS NC VSS DQS8_c DQS8_t VSS NC VSS NC VSS CKE1 VDD RFU VDD BG1 ALERT_n VDD A11 A7 VDD A5 A4 VDD A2 VDD CK1_t CK1_c VDD VTT PARITY VDD BA1 A10/AP VDD RFU WE_n/A14 VDD NC VDD A13 VDD NC NC VDD NC SA2 VSS DQ37 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 VSS DQ33 VSS DQS4_c DQS4_t VSS DQ39 VSS DQ35 VSS DQ45 VSS DQ41 VSS DQS5_c DQS5_t VSS DQ47 VSS DQ43 VSS DQ53 VSS DQ49 VSS DQS6_c DQS6_t VSS DQS5 VSS DQ51 VSS DQ61 VSS DQ57 VSS DQS7_c DQS7_t VSS DQ63 VSS DQ59 VSS VDDSPD SDA VPP VPP VPP Note: 1. VPP is 2.5V DC. 2. Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs. 3. Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM 4. The 5th VPP is required on all modules, DIMMs. 4 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Block Diagram 4GB, 512Mx64 Module(1 Rank x8) This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. 5 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 85 C 1,2 Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. At 0 - 85C, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1 Voltage on VPP pin relative to Vss VPP -0.3 ~ 3.0 V 3 Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1 Storage temperature TSTG -55~+100 C 1,2 Note: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. VPP must be equal or greater than VDD/VDDQ at all times. AC & DC Operating Conditions Recommended DC operating conditions (SSTL –1.5) Rating Parameter Symbol Min Typ. Unit Note s V V V 1, 2 1, 2 3 Max Supply voltage VDD 1.14 1.2 1.26 Supply voltage for Output VDDQ 1.14 1.2 1.26 Wordline supply voltage VPP 2.375 2.5 2.75 Note: Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. DC bandwidth is limited to 20MHz Single-ended AC & DC input levels for Command and Address DDR4-1600/1866/2133 Parameter Symbol Unit Note Min Max I/O Reference Voltage (CMD/ADD) VREFCA(DC) 0.49*VDDQ 0.51*VDDQ V 1,2 DC Input Logic High VIH(DC) VREF+0.075 VDD V DC Input Logic Low VIL(DC) VSS VREF-0.075 V AC Input Logic High VIH(AC) VREF+0.1 Note 1 V AC Input Logic Low VIL(AC) Note 1 VREF-0.1 V Note: The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV) For reference : approx. VDD/2 ± 12mV 6 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Differential AC and DC Input Levels DDR4-1600/1866/2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3 V 1 differential input low DC VILdiff(DC) NOTE 3 -0.150 V 1 differential input high AC VIHdiff(AC) 2 x (VIH(AC) - VREF) NOTE 3 V 2 differential input low AC VILdiff(AC) NOTE 3 2 x (VIL(AC) -VREF) V 2 Note: Used to define a differential signal slew-rate. for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA; These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Single-ended AC & DC output levels Parameter Symbol DDR4-1600/1866/2133 Unit Note DC output high measurement level VOH(DC) 1.1 x VDDQ V DC output mid measurement level VOM(DC) 0.8 x VDDQ V DC output low measurement level VOL(DC) 0.5 x VDDQ V AC output high measurement level VOH(AC) (0.7 + 0.15) x VDDQ V 1 AC output low measurement level VOL(AC) (0.7 - 0.15) x VDDQ V 1 Note: The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ. Differential AC & DC output levels Parameter Symbol DDR4-1600/1866/2133 Unit Note AC differential output high VOHdiff(AC) +0.3 x VDDQ V 1 measurement level AC differential output low VOLdiff(AC) -0.3 x VDDQ V 1 measurement level Note: The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs. 7 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG IDD Specification parameters Definition ( IDD values are for full operating range of Voltage and Temperature) 4GB, 512Mx64 Module(1 Rank x8) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Symbol DDR4 2133 CL15 Unit IDD0 TBD mA IDD1 TBD mA IDD2P TBD mA IDD2Q TBD mA IDD2N TBD mA IDD3P TBD mA IDD3N TBD mA IDD4R TBD mA IDD4W TBD mA IDD5 TBD mA IDD6 TBD mA IDD7 TBD mA Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1.Module IDD was calculated on the specific brand DRAM(2Xnm) component IDD and can be differently measured according to DQ loading capacitor. 8 288Pin DDR4 2133 UDIMM 4GB Based on 512Mx8 AQD-D4U4GN21-SG Timing Parameters & Specifications Speed Parameter Average Clock Period CK high-level width CK low-level width DQS_t,DQS_c to DQ skew, per group, per access DQS_t,DQS_c to DQ Skew determin-istic, per group, per access DDR4 2133 Unit Symbol tCK tCH tCL Min 0.938 0.48 0.48 Max