AQD-D4U8GE24-HE

288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE Advantech AQD-D4U8GE24-HE Datasheet Rev. 0.0 2016-12-13 1 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE Description DQS0_t–DQS17_t Data Buffer data strobes AQD-D4U8GE24-HE is a DDR4 2400Mbps ECC U-DIMM DQS0_c–DQS17_c Data Buffer data strobes CK0_t, CK1_t SDRAM clocks CK0_c, CK1_c SDRAM clocks ODT0 &ODT1 On-die termination control line CS0_n–CS3_n DIMM Rank Select Lines input. high-speed, memory module that use 18pcs of 1024Mx 8 bits DDR4 SDRAM in FBGA package and a 4K bits serial EEPROM on a 288-pin printed circuit board. AQD-D4U8GE24-HE is a Dual In-Line Memory Module and is intended for mounting into 288-pin edge connector 2 Row address strobe 3 Column address strobe WE_n 4 Write Enable DM0~DM7 Data masks/high data strobes VDD Core power supply VDDQ I/O driver power supply Features VREFCA Command/address reference supply  RoHS compliant products. VDDSPD SPD EEPROM power supply sockets. RAS_n Synchronous design allows precise cycle control with the CAS_n use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.  JEDEC standard 1.2V(1.14V~1.26V) Power supply I2C serial bus address select for SA0~SA2 VDDQ= 1.2V(1.14V~1.26V) EEPROM  VPP = 2.5V +0.25V / -0.125V SCL I2C serial bus clock for EEPROM SDA I2C serial bus data for EEPROM VSS Ground RESET_n Set DRAMs Known State  Burst Length (BL) switch on-the-fly BL8 or BC4 VTT DRAM I/O termination supply  Bi-directional Differential Data-Strobe VPP SDRAM Supply  On Die Termination, Nominal, Park, and Dynamic ODT ALERT_n SDRAM ALERT_n  Serial presence detect with EEPROM EVENT_n  Data transfer rates: PC3-12800 Programmable CAS Latency: 10,11,12,13,14,15,16,17,18  8 bit pre-fetch Asynchronous reset RFU  PCB edge connector treated with 30u” Gold-Plating Reserved for future use 1. Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs Pin Identification Symbol SPD signals a thermal event has occurred this connection pin is NC. Function A0–A171, BA0~BA1 Address/Bank input DQ0~DQ63 Bi-direction data bus. 2. RAS_n is a multiplexed function with A16. 3. CAS_n is a multiplexed function with A15. 4. WE_n is a multiplexed function with A14. 2 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE Dimensions (Unit: millimeter) Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE Pin Assignments Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back Pin Back Pin 1 12V 2 VSS 41 NC 42 VSS 81 BA0 121 DM6,DBI6 161 DQ9 82 RAS_n/A16 122 NC 162 VSS 201 CB3 202 VSS 3 4 DQ4 43 DQ30 VSS 44 VSS 83 VDD 123 VSS 163 84 CS0_n 124 DQ54 164 DQS1C 203 CKE1 DQS1T 204 VDD 5 DQ0 45 DQ26 6 VSS 46 VSS 85 VDD 125 VSS 86 CAS_n/A15 126 DQ50 165 VSS 205 166 DQ15 206 7 DM0,DBI0 47 CB4 87 ODT0 127 VSS 167 VSS 207 8 NC 9 VSS 48 VSS 88 VDD 49 CB0 89 CS1_n 128 DQ60 168 DQ11 129 VSS 169 VSS 10 QD6 11 VSS 50 VSS 90 51 DM8,DBI8 91 VDD 130 DQ56 170 ODT1 131 VSS 171 12 DQ2 13 VSS 52 NC 92 53 VSS 93 VDD 132 DM7,DBI7 NC 133 NC 14 DQ12 54 CB6 94 VSS 134 15 VSS 55 16 DQ8 56 VSS 95 DQ36 CB2 96 VSS 17 VSS 18 DM1,DBI1 57 VSS 97 58 RESET_n 98 19 NC 59 VDD 99 20 VSS 60 CKE0 100 21 DQ14 61 VDD 101 VSS 241 VSS 281 VSS 242 DQ33 282 DQ59 243 VSS 283 VSS 244 DQS4C 284 VDDSPD RFU 245 DQS4T 285 SDA VDD 246 VSS 286 VPP BG1 247 DQ39 287 VPP 208 ALERT_n 248 VSS 288 VPP 209 VDD 249 DQ35 DQ21 210 A11 250 VSS VSS 211 A7 251 DQ45 172 DQ17 212 VDD 252 VSS 173 VSS 213 A5 253 DQ41 VSS 174 DQS2C 214 A4 254 VSS 135 DQ62 175 DQS2T 215 VDD 255 DQS5C 136 VSS 176 VSS 216 A2 256 DQS5T DQ32 137 DQ58 177 DQ23 217 VDD 257 VSS VSS 138 VSS 178 VSS 218 CK1T 258 DQ47 DM4,DBI4 139 SA0 179 DQ19 219 CK1C 259 VSS 140 SA1 180 VSS 220 VDD 260 DQ43 141 SCL 181 DQ29 221 VTT 261 VSS 22 VSS 62 ACT_n 102 23 DQ10 63 BG0 103 DQ38 142 VPP 182 VSS 222 PARITY 262 DQ53 VSS 143 VPP 183 DQ25 223 VDD 263 VSS 24 VSS 64 VDD 25 DQ20 65 A12/BC_n 104 DQ34 144 RFU 184 VSS 224 BA1 264 DQ49 105 VSS 145 12V 185 DQS3C 225 A10_AP 265 VSS 26 VSS 66 A9 106 DQ44 146 VREFCA 186 DQS3T 226 VDD 266 DQS6C 27 DQ16 28 VSS 67 VDD 107 VSS 147 VSS 187 VSS 227 RFU 267 DQS6T 68 A8 108 DQ40 148 DQ8 188 DQ31 228 WE_n/A14 268 VSS 29 DM2,DBI2 30 NC 69 A6 109 VSS 149 VSS 189 VSS 229 VDD 269 DQ55 70 VDD 110 DM5,DBI5 150 DQ1 190 DQ27 230 NC 270 VSS 31 32 VSS 71 A3 111 NC 151 VSS 191 VSS 231 VDD 271 DQ51 DQ22 72 A1 112 VSS 152 DQS0C 192 CB5 232 A13 272 VSS 33 VSS 73 VDD 113 DQ46 153 DQS0T 193 VSS 233 VDD 273 DQ61 34 DQ18 74 CK0T 114 VSS 154 VSS 194 CB1 234 NC 274 VSS 35 VSS 75 CK0C 115 DQ42 155 DQ7 195 VSS 235 NC 275 DQ57 36 DQ28 76 VDD 116 VSS 156 VSS 196 DQS8C 236 VDD 276 VSS 37 VSS 77 VTT 117 DQ52 157 DQ3 197 DQS8T 237 NC 277 DQS7C 38 DQ24 78 EVENT_n 118 VSS 158 VSS 198 VSS 238 SA2 278 DQS7T 39 VSS 79 A0 119 DQ48 159 DQ13 199 CB7 239 VSS 279 VSS 40 DM3,DBI3 80 VDD 120 VSS 160 VSS 200 VSS 240 DQ37 280 DQ63 NC 4 Back 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE 8GB, 1024Mx9 Module (1 Rank x8)  This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. 5 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 C Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1,2 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1 Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Supply voltage Symbol Voltage Unit Notes Min Typ. Max VDD 1.2V 1.14 1.2 1.26 V 1,2,3 VDDQ 1.2V 1.14 1.2 1.26 V 1,2,3 I/O Reference Voltage (DQ) VREFDQ(DC) I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.2V 1.2V 0.49*VDD 0.49*VDD 0.50*VDD 0.50*VDD 0.51*VDD 0.51*VDD V V 4 4 AC Input Logic High VIH(AC) 1.2V VREF+100 - VDD AC Input Logic Low VIL(AC) 1.2V VSS - VREF–100 mV DC Input Logic High VIH(DC) 1.2V VREF+75 - VDD mV Supply voltage for Output 2 2 mV DC Input Logic Low VIL(DC) 1.2V mV VSS VREF-75 Note: (1) Under all conditions VDDQ must be less than or equal to VDD. (2) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. (3) The DC bandwidth is limited to 200MHz. (4) The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx. ±12mV) 6 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE IDD Specification parameters Definition - 8GB (1 Rank x8) Parameter Symbol Unit 1 342 mA 1 54 mA 1 432 mA 243 mA 288 mA 2 162 mA 2 198 mA 2 408 mA 2 135 mA 2 333 mA 1 1116 mA 1 1080 mA 1 1746 mA 1 585 mA 2 198 mA 2 252 mA 1 1368 mA 1 171 mA One bank ACTIVATE-PRECHARGE current IDD0 One bank ACTIVATE-PRECHARGE, wordline boost, IPP current IPP0 One Bank Active-Read-Precharge Current IDD1 2 Precharge Standby Current DDR4 2400 CL17 IDD2N Precharge standby ODT current IDD2NT Precharge Power-Down Current IDD2P Precharge Quiet Standby Current IDD2Q Active standby current IDD3N Active standby IPP current IPP3N Active Power-Down Current IDD3P Burst Read Current IDD4R Burst write current IDD4W Burst refresh current (1x REF) IDD5B Burst refresh IPP current (1x REF) IPP5B Self refresh current: Normal temperature range (0–85°C) IDD6N Self refresh current: Extended temperature range (0–95°C) IDD6E Bank interleave read current IDD7 Bank interleave read IPP current IPP7 1 2 mA Maximum power-down current IDD8 108 Note: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3.IDD current measure method and detail patterns are described on DDR4 component datasheet. Only for reference.  Timing Parameters & Specifications 7 288Pin DDR4 2400 1.2V U-DIMM 8GB Based on 1024Mx8 AQD-D4U8GE24-HE Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Average high pulse width Average low pulse width Absolute Clock Period Absolute clock HIGH pulse width Absolute clock LOW pulse width Clock Period Jitter- total Clock Period Jitter- deterministic Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter deterministic Cycle to Cycle Period Jitter during DLL locking period Duty Cycle Jitter Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across 13 cycles Cumulative error across 14 cycles Cumulative error across 15 cycles Cumulative error across 16 cycles Cumulative error across 17 cycles Cumulative error across 18 cycles Cumulative error across n = 13, 14 . . . 49, 50 cycles Command and Address setup time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels Command and Address setup time to CK_t, CK_c referenced to Vref levels Command and Address hold time to CK_t, CK_c referenced to Vih(dc) / Vil(dc) levels Command and Address hold time to CK_t, CK_c referenced to Vref levels Control and Address Input pulse width for each input Command and Address Timing CAS_n to CAS_n command delay for same bank group CAS_n to CAS_n command delay for different bank group ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 1/2KB page size Four activate window for 2KB page size Four activate window for 1KB page size Four activate window for 1/2KB page size Delay from start of internal write transaction to internal read command for different bank group Delay from start of internal write transaction to internal read command for same bank group Internal READ Command to PRECHARGE Command delay WRITE recovery time Symbol tCK (DLL_OFF) tCK(avg) tCH(avg) tCL(avg) tCK(abs) tCH(abs) tCL(abs) JIT(per)_tot JIT(per)_dj tJIT(per, lck) tJIT(cc)_total tJIT(cc)_dj DDR4-1866 MAX MIN 8 1.071