288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Advantech
AQD-D4U8GR21-HZ
Datasheet
Rev. 0.0
2015-1-8
1
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Description
DQS0_t–DQS17_t
Data Buffer data strobes
AQD-D4U8GR21-HZ is a DDR4 2133Mbps R-DIMM
DQS0_c–DQS17_c
Data Buffer data strobes
CK0_t, CK1_t
Register clock input
CK0_c, CK1_c
Registert clocks input
ODT0 &ODT1
On-die termination control line
CS0_n–CS3_n
DIMM Rank Select Lines input.
high-speed, memory module that use 18pcs of 1024Mx
72 bits DDR4 SDRAM in FBGA package and a 4K bits
serial EEPROM on a 288-pin printed circuit board.
AQD-D4U8GR21-HZ is a Dual In-Line Memory Module
and is intended for mounting into 288-pin edge connector
sockets.
RAS_n
2
Row address strobe
Synchronous design allows precise cycle control with the
CAS_n
3
Column address strobe
use of system clock. Data I/O transactions are possible
WE_n4
Write Enable
DM0~DM7
Data masks/high data strobes
VDD
Core power supply
VDDQ
I/O driver power supply
Features
VREFCA
Command/address reference supply
RoHS compliant products.
VDDSPD
SPD EEPROM power supply
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
I2C serial bus address select for
JEDEC standard 1.2V(1.14V~1.26V) Power supply
SA0~SA2
VDDQ= 1.2V(1.14V~1.26V)
EEPROM
VPP = 2.5V +0.25V / -0.125V
SCL
I2C serial bus clock for EEPROM
SDA
I2C serial bus data for EEPROM
VSS
Ground
RESET_n
Set DRAMs Known State
Bi-directional Differential Data-Strobe
VTT
DRAM I/O termination supply
Supports ECC error correction and detection
VPP
SDRAM Supply
ALERT_n
Register ALERT_n output
Data transfer rates: PC4-2133
Programmable CAS Latency: 9,11,12,13,14,15,16
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4
On Die Termination, Nominal, Park, and Dynamic ODT
Serial presence detect with EEPROM
EVENT_n
Asynchronous reset
PCB edge connector treated with 30u” Gold-Plating
Pin Identification
Symbol
RFU
Address/Bank input
DQ0~DQ63
Bi-direction data bus.
Reserved for future use
1. Address A17 is only valid for 16 Gb x4 based SDRAMs.
2. RAS_n is a multiplexed function with A16.
Function
A0–A171, BA0~BA1
SPD signals a thermal event has
occurred
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
2
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Dimensions (Unit: millimeter)
Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Pin Assignments
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Back
Pin
Back
Pin
Back
Pin
161
DQ9
201
CB3
162
VSS
202
VSS
Back
241
VSS
281
VSS
242
DQ33
282
DQ59
1
12V
41
81
BA0
121
2
VSS
42
VSS
82
RAS_n/A16
122
3
DQ4
43
DQ30
83
VDD
123
VSS
163
DQS1C
203
CKE1
243
VSS
283
VSS
4
VSS
44
VSS
84
S0_n
124
DQ54
164
DQS1T
204
VDD
244
DQS4C
284
VDDSPD
5
DQ0
45
DQ26
85
VDD
125
VSS
165
VSS
205
RFU
245
DQS4T
285
SDA
VSS
46
VSS
86
CAS_n/A15
126
DQ50
166
DQ15
206
VDD
246
VSS
286
VPP
47
CB4
87
ODT0
127
VSS
167
VSS
207
BG1
247
DQ39
287
VPP
288
VPP
6
7
8
DQS9T,DM0,
DBI0,TDQS9T
DQS9C,
TDQS9C
DQS15T,DM6,
DBI6,TDQS15T
DQS15C,
TDQS15C
Pin
DQS12C,
TDQS12C
48
VSS
88
VDD
128
DQ60
168
DQ11
208
ALERT_n
248
VSS
9
VSS
49
CB0
89
S1_n
129
VSS
169
VSS
209
VDD
249
DQ35
10
QD6
50
VSS
90
VDD
130
DQ56
170
DQ21
210
A11
250
VSS
11
VSS
51
91
ODT1
131
VSS
171
VSS
211
A7
251
DQ45
12
DQ2
52
92
VDD
132
172
DQ17
212
VDD
252
VSS
13
VSS
53
VSS
93
S2_n,C[0]
133
173
VSS
213
A5
253
DQ41
14
DQ12
54
CB6
94
VSS
134
VSS
174
DQS2C
214
A4
254
VSS
15
VSS
55
VSS
95
DQ36
135
DQ62
175
DQS2T
215
VDD
255
DQS5C
16
DQ8
56
CB2
96
VSS
136
VSS
176
VSS
216
A2
256
DQS5T
17
VSS
57
VSS
97
DQ32
137
DQ58
177
DQ23
217
VDD
257
VSS
58
RESET_n
98
VSS
138
VSS
178
VSS
218
CK1T
258
DQ47
59
VDD
99
139
SA0
179
DQ19
219
CK1C
259
VSS
18
19
DQS10T,DM1,
DBI1,TDQS10T
DQS10C,
TDQS10C
DQS17T,DM8,
DBI8,TDQS17T
DQS17C,
TDQS17C
DQS13T,DM4,
DBI4,TDQS13T
DQS13C,
TDQS13C
DQS16T,DM7,
DBI7,TDQS16T
DQS16C,
TDQS16C
20
VSS
60
CKE0
100
140
SA1
180
VSS
220
VDD
260
DQ43
21
DQ14
61
VDD
101
VSS
141
SCL
181
DQ29
221
VTT
261
VSS
22
VSS
62
ACT_n
102
DQ38
142
VPP
182
VSS
222
PARITY
262
DQ53
23
DQ10
63
BG0
103
VSS
143
VPP
183
DQ25
223
VDD
263
VSS
24
VSS
64
VDD
104
DQ34
144
RFU
184
VSS
224
BA1
264
DQ49
25
DQ20
65
A12
105
VSS
145
12V
185
DQS3C
225
A10_AP
265
VSS
26
VSS
66
A9
106
DQ44
146
VREFCA
186
DQS3T
226
VDD
266
DQS6C
27
DQ16
67
VDD
107
VSS
147
VSS
187
VSS
227
RFU
267
DQS6T
28
VSS
68
A8
108
DQ40
148
DQ8
188
DQ31
228
WE_n/A14
268
VSS
69
A6
109
VSS
149
VSS
189
VSS
229
VDD
269
DQ55
70
VDD
110
150
DQ1
190
DQ27
230
SAVE_n
270
VSS
29
30
DQS11T,DM2,
DBI2,TDQS11T
DQS11C,
TDQS11C
DQS14T,DM5,
DBI5,TDQS14T
DQS14C,
TDQS14C
31
VSS
71
A3
111
151
VSS
191
VSS
231
VDD
271
DQ51
32
DQ22
72
A1
112
VSS
152
DQS0C
192
CB5
232
A13
272
VSS
33
VSS
73
VDD
113
DQ46
153
DQS0T
193
VSS
233
VDD
273
DQ61
34
DQ18
74
CK0T
114
VSS
154
VSS
194
CB1
234
A17,NC
274
VSS
35
VSS
75
CK0C
115
DQ42
155
DQ7
195
VSS
235
C[2].NC
275
DQ57
36
DQ28
76
VDD
116
VSS
156
VSS
196
DQS8C
236
VDD
276
VSS
37
VSS
77
VTT
117
DQ52
157
DQ3
197
DQS8T
237
S3_n,C[1]
277
DQS7C
38
DQ24
78
EVENT_n
118
VSS
158
VSS
198
VSS
238
SA2,RFU
278
DQS7T
39
VSS
79
A0
119
DQ48
159
DQ13
199
CB7
239
VSS
279
VSS
40
DQS12T,DM3,
DBI3,TDQS12T
80
VDD
120
VSS
160
VSS
200
VSS
240
DQ37
280
DQ63
4
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
8GB, 1024Mx18 Module (1 Rank x4)
This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make
changes in specifications at any time without prior notice.
5
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Operating Temperature
TOPER
0 to 85
C
Note:
Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
Note
1,2
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.3 ~ 1.5
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.3 ~ 1.5
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.3 ~ 1.5
V
1
Storage temperature
TSTG
-55~+100
C
1,2
1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
Note:
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions
Rating
Parameter
Supply voltage
Symbol
Voltage
Unit Notes
Min
Typ.
Max
VDD
1.2V
1.14
1.2
1.26
V
1,2,3
VDDQ
1.2V
1.14
1.2
1.26
V
1,2,3
I/O Reference Voltage (DQ)
VREFDQ(DC)
I/O Reference Voltage (CMD/ADD) VREFCA(DC)
1.2V
1.2V
0.49*VDD
0.49*VDD
0.50*VDD
0.50*VDD
0.51*VDD
0.51*VDD
V
V
4
4
AC Input Logic High
VIH(AC)
1.2V
VREF+100
-
VDD
AC Input Logic Low
VIL(AC)
1.2V
VSS
-
VREF–100
mV
DC Input Logic High
VIH(DC)
1.2V
VREF+75
-
VDD
mV
Supply voltage for Output
2
2
mV
DC Input Logic Low
VIL(DC)
1.2V
mV
VSS
VREF-75
Note:
(1) Under all conditions VDDQ must be less than or equal to VDD.
(2) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
(3) The DC bandwidth is limited to 200MHz.
(4) The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD
(for reference: approx. ±12mV)
6
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
IDD Specification parameters Definition - 8GB (1 Rank x4)
Parameter
Symbol
DDR4 2133 CL15
One bank ACTIVATE-PRECHARGE current
IDD01
504
mA
One bank ACTIVATE-PRECHARGE, wordline boost, IPP current
IPP01
46.8
mA
One Bank Active-Read-Precharge Current
IDD11
648
mA
IDD2N2
270
mA
Precharge standby ODT current
IDD2NT1
324
mA
Precharge Power-Down Current
IDD2P
2
198
mA
Precharge Quiet Standby Current
IDD2Q
2
270
mA
Active standby current
IDD3N2
486
mA
Active standby IPP current
IPP3N
2
46.8
mA
Active Power-Down Current
IDD3P2
360
mA
Burst Read Current
IDD4R
1
1494
mA
Burst write current
IDD4W
1
1566
mA
Burst refresh current (1x REF)
IDD5B
1
2160
mA
Burst refresh IPP current (1x REF)
IPP5B
1
390.6
mA
Self refresh current: Normal temperature range (0–85°C)
IDD6N
2
198
mA
Self refresh current: Extended temperature range (0–95°C)
IDD6E
2
252
mA
Precharge Standby Current
Unit
Bank interleave read current
IDD7
1
1998
mA
Bank interleave read IPP current
IPP71
203.4
mA
mA
Maximum power-down current
IDD82
90
Note: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
3.IDD current measure method and detail patterns are described on DDR4 component datasheet. Only for
reference.
7
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Timing Parameters & Specifications
Speed
Parameter
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Average high pulse width
Average low pulse width
Absolute Clock Period
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock Period Jitter- total
Clock Period Jitter- deterministic
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter deterministic
Cycle to Cycle Period Jitter during DLL locking
period
Duty Cycle Jitter
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 . . . 49, 50
cycles
Command and Address Timing
CAS_n to CAS_n command delay for same
bank group
CAS_n to CAS_n command delay for different bank
group
ACTIVATE to ACTIVATE Command delay to different
bank group for 2KB page size
ACTIVATE to ACTIVATE Command delay to different
bank group for 2KB page size
ACTIVATE to ACTIVATE Command delay to different
bank group for 1/2KB page size
ACTIVATE to ACTIVATE Command delay to same
bank group for 2KB page size
ACTIVATE to ACTIVATE Command delay to same
bank group for 1KB page size
ACTIVATE to ACTIVATE Command delay to same
bank group for 1/2KB page size
Four activate window for 2KB page size
Four activate window for 1KB page size
Four activate window for 1/2KB page size
Delay from start of internal write transaction to
internal read command for different bank group
Delay from start of internal write transaction to
internal read command for same bank group
Internal READ Command to PRECHARGE Command
delay
WRITE recovery time
Write recovery time when CRC and DM are enabled
delay from start of internal write transaction to
internal read command for different bank group with
both CRC and DM enabled
delay from start of internal write transaction to
internal read command for same bank group with
both CRC and DM enabled
DLL locking time
Mode Register Set command cycle time
Mode Register Set command update delay
Multi-Purpose Register Recovery Time
Multi Purpose Register Write Recovery Time
Symbol
tCK (DLL_OFF)
tCK(avg)
tCH(avg)
tCL(avg)
tCK(abs)
tCH(abs)
tCL(abs)
JIT(per)_tot
JIT(per)_dj
tJIT(per, lck)
tJIT(cc)_total
tJIT(cc)_dj
DDR4-2133
MAX
MIN
8
tbd –(Definition tbd)
0.48
0.52
0.48
0.52
tCK(avg)min +
tCK(avg)max +
tJIT(per)min_to t
tJIT(per)m ax_tot
0.45
0.45
-0.1
0.1
TBD
TBD
TBD
TBD
0.2
TBD
ns
ps
tCK(avg)
tCK(avg)
TBD
UI
tJIT(cc, lck)
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
Units
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tERR(nper)
tCK(avg)
tCK(avg)
tCK(avg)
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
tCCD_L
5
-
nCK
tCCD_S
4
-
nCK
tRRD_S(2K)
Max(4nCK,5.3ns)
-
nCK
tRRD_S(1K)
Max(4nCK,3.7ns)
-
nCK
tRRD_S(1/2K)
Max(4nCK,3.7ns)
-
nCK
tRRD_L(2K)
Max(4nCK,6.4ns)
-
nCK
tRRD_L(1K)
Max(4nCK,5.3ns)
-
nCK
tRRD_L(1/2K)
Max(4nCK,5.3ns)
-
nCK
tFAW_2K
tFAW_1K
tFAW_1/2K
30
21
15
-
ns
ns
ns
tWTR_S
max(2nCK,2.5ns)
-
tWTR_L
max(4nCK,7.5ns)
-
tRTP
max(4nCK,7.5ns)
-
tWR
15
tWR+max
(5nCK,3.75ns)
-
ns
-
ns
tWR_CRC _DM
tWTR_S_C
RC_DM
tWTR_S+max
(5nCK,3.75ns)
-
ns
tWTR_L_C
RC_DM
tWTR_L+max
(5nCK,3.75ns)
-
ns
tDLLK
tMRD
tMOD
tMPRR
tWR_MPR
TBD
8
max(24nCK,15ns)
1
tMOD (min)
-
nCK
nCK
8
nCK
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Speed
Parameter
Clock Timing
CS_n to Command Address Latency
CS_n to Command Address Latency
DRAM Data Timing
DQS_t,DQS_c to DQ skew, per group, per access
DQS_t,DQS_c to DQ Skew deterministic, per group,
per access
DQ output hold time from DQS_t,DQS_c
DQ output hold time deterministic from DQS_t, DQS_c
DQS_t,DQS_c to DQ Skew total, per group, per
access;DBI enabled
DQ output hold time total from DQS_t, DQS_c; DBI
enabled
DQ to DQ offset , per group, per access referenced to
DQS_t, DQS_c
Data Strobe Timing
DQS_t,DQS_c differential output high time
DQS_t,DQS_c differential output low time
MPSM Timing
Command path disable delay upon MPSM entry
Symbol
4
-
nCK
tDQSQ
-
TBD
tCK(avg)/2
tDQSQ
-
TBD
tCK(avg)/2
tQH
tQH
TBD
TBD
-
tCK(avg)/2
UI
tDQSQ
-
TBD
UI
tQH
TBD
-
UI
tDQSQ
TBD
TBD
UI
tQSH
tQSL
TBD
TBD
TBD
TBD
tCK(avg)/2
tCK(avg)/2
tMPED
tCKMPE
Valid clock requirement before MPSM exit
tCKMPX
Exit MPSM to commands requiring a locked DLL
CS setup time to CKE
CS hold time to CKE
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation Short calibration time
Reset/Self Refresh Timing
Exit Reset from CKE HIGH to a valid command
Exit Self Refresh to commands not requiring a locked
DLL
SRX to commands not requiring a locked DLL in Self
Refresh ABORT
Exit Self Refresh to ZQCL,ZQCS and MRS
(CL,CWL,WR,RTP and Gear Down)
Exit Self Refresh to commands requiring a locked DLL
Minimum CKE low width for Self refresh entry to exit
timing
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down when CA Parity is enabled
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
Power Down Timing
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE or PREA command to Power Down
entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down
entry (BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
Units
tCAL
Valid clock requirement after MPSM entry
Exit MPSM to commands not requiring a locked DLL
DDR4-2133
MAX
MIN
tXMP
tMOD(min) +
tCPDED(min)
tMOD(min) +
tCPDED(min)
tCKSRX(min)
TBD
-
tMPX_S
tMPX_H
tXMP(min) +
tXSDLL(min)
TBD
TBD
tZQinit
tZQoper
tZQCS
1024
512
128
-
tXPR
max
(5nCK,tRFC(min)+
10ns)
-
tXS
tRFC(min)+10ns
-
tXS_ABORT(min)
tRFC4(min)+10ns
-
tXS_FAST (min)
tRFC4(min)+10ns
-
tXSDLL
tDLLK(min)
-
tCKESR
tCKE(min)+1nCK
-
tCKSRE
max(5nCK,10ns)
-
tCKSRE_PAR
max
(5nCK,10ns)+PL
-
tCKSRX
max(5nCK,10ns)
-
tXP
max (4nCK,6ns)
-
tCKE
tCPDED
tPD
tACTPDEN
max (3nCK, 5ns)
4
tCKE(min)
2
9*tREFI
-
tPRPDEN
2
-
nCK
tRDPDEN
RL+4+1
WL+4+(tWR/
tCK(avg))
-
nCK
-
nCK
tWRAPDEN
WL+4+WR+1
-
nCK
tWRPBC4DEN
WL+2+(tWR/
tCK(avg))
-
nCK
tWRAPBC4DEN
WL+2+WR+1
-
nCK
tREFPDEN
tMRSPDEN
1
tMOD(min)
-
nCK
tXMPDLL
tWRPDEN
9
nCK
nCK
nCK
nCK
nCK
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
Speed
Parameter
Clock Timing
PDA Timing
Mode Register Set command cycle time in PDA
mode
Mode Register Set command update delay in PDA
mode
ODT Timing
Asynchronous RTT turn-on delay (Power-Down
with DLL frozen)
Asynchronous RTT turn-off delay (Power-Down
with DLL frozen)
RTT dynamic change skew
Write Leveling Timing
First DQS_t/DQS_n rising edge after write leveling
mode is programmed
DQS_t/DQS_n delay after write leveling mode is
programmed
Write leveling setup time from rising CK_t, CK_c
crossing to rising DQS_t/DQS_n crossing
Write leveling hold time from rising DQS_t/DQS_n
crossing to rising CK_t, CK_ crossing
Write leveling output delay
Write leveling output error
CA Parity Timing
Commands not guaranteed to be executed during
this time
Delay from errant command to ALERT_n
assertion
Pulse width of ALERT_n signal when asserted
Time from when Alert is asserted till controller must
start providing DES commands in Persistent CA
parity mode
Parity Latency
CRC Error Reporting
CRC error to ALERT_n latency
CRC ALERT_n pulse width
tREFI
tRFC1 (min)
tRFC2 (min)
tRFC4 (min)
Symbol
tMRD_PDA
DDR4-2133
MAX
MIN
Units
max(16nCK,10ns)
tMOD
tMOD_PDA
tAONAS
1.0
9.0
ns
tAOFAS
1.0
9.0
ns
tADC
0.3
0.7
tCK(avg)
tWLMRD
40
-
nCK
tWLDQSEN
25
-
nCK
tWLS
0.13
-
tCK(avg)
tWLH
0.13
-
tCK(avg)
tWLO
tWLOE
0
9.5
ns
ns
tPAR_UNKNOWN
-
Max(2nCK,3ns)
tPAR_ALERT_ON
-
PL+6ns
tPAR_ALERT_PW
64
128
nCK
tPAR_ALERT_RSP
-
57
nCK
4
PL
nCK
tCRC_ALERT
CRC_ALERT_PW
6
13
10
ns
nCK
2Gb
4Gb
8Gb
16Gb
2Gb
4Gb
8Gb
16Gb
2Gb
4Gb
8Gb
16Gb
160
260
350
TBD
110
160
260
TBD
90
110
160
TBD
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
SERIAL PRESENCE DETECT SPECIFICATION (AQD-D4U8GR21-HZ Serial Presence Detect)
Function Described
Byte
0
Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage
1
SPD Revision
2
Key Byte / DRAM Device Type
3
Key Byte / Module Type
4
SDRAM Density and Banks
5
SDRAM Addressing
Function
23
Version 1.0
10
0C
01
84
21
00
00
00
00
00
03
00
0B
80
00
00
08
0C
FC
2B
00
00
6C
6C
6C
11
08
74
20
08
00
05
70
03
00
78
1E
2B
2B
00
15
0D
15
0D
15
0D
15
0D
15
0D
15
0D
15
0D
15
0D
15
0D
00
DDR4 SDRAM
RDIMM
4Gb
4 bank group / 4 bank
Row : 16
Column : 10
6
SDRAM Device Type
7
SDRAM Optional Features
-
8
SDRAM Thermal and Refresh Options
-
9
Other SDRAM Optional Features
10
Reserved
11
Module Nominal Voltage, VDD
12
Module Organization
13
Module Memory Bus Width
14
Module Thermal Sensor
Mono / Single die
PPR not support
1.2v
1Rank
x4
8bit ECC
64bits
Thermal Sensor on module
15~16 Reserved
-
17
Timebases
18
SDRAM Minimum Cycle Time (tCKAVGmin)
19
SDRAM Maximum Cycle Time (tCKAVGmax)
20
CAS Latencies Supported, First Byte
21
CAS Latencies Supported, Second Byte
22
CAS Latencies Supported, Third Byte
23
CAS Latencies Supported, Fourth Byte
24
Minimum CAS Latency Time(tAAmin)
13.5 ns
25
Minimum RAS to CAS Delay Time (tRCDmin)
13.5 ns
26
Minimum Row Precharge Delay Time (tRPmin)
13.5 ns
27
Upper Nibbles for tRASmin and tRCmin
28
Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
29
Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significatn Byte
30
Minimum Refresh Recovery Delay Time (tRFC1min), Least Significant Byte
31
Minimum Refresh Recovery Delay Time (tRFC1min), Most Significant Byte
32
Minimum Refresh Recovery Delay Time (tRFC2min), Least Significant Byte
33
Minimum Refresh Recovery Delay Time (tRFC2min), Most Significant Byte
34
Minimum Refresh Recovery Delay Time (tRFC4min), Least Significant Byte
35
Minimum Refresh Recovery Delay Time (tRFC4min), Most Significant Byte
36
Upper Nibble for tFAW
37
Minimum Four Activate WIndow Delay Time (tFAWmin), Least Significant Byte
38
Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
39
Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
40
Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
MTB: 125ps
Connector to SDRAM Bit Mapping
61
Connector to SDRAM Bit Mapping
62
Connector to SDRAM Bit Mapping
63
Connector to SDRAM Bit Mapping
64
Connector to SDRAM Bit Mapping
65
Connector to SDRAM Bit Mapping
66
Connector to SDRAM Bit Mapping
67
Connector to SDRAM Bit Mapping
68
Connector to SDRAM Bit Mapping
69
Connector to SDRAM Bit Mapping
70
Connector to SDRAM Bit Mapping
71
Connector to SDRAM Bit Mapping
72
Connector to SDRAM Bit Mapping
73
Connector to SDRAM Bit Mapping
74
Connector to SDRAM Bit Mapping
75
Connector to SDRAM Bit Mapping
76
Connector to SDRAM Bit Mapping
77
Connector to SDRAM Bit Mapping
FTB: 1ps
0.938 ns
1.5 ns
CL 9,10,11,12,13,14
CL 15,16,18,20
-
33 ns
46.5 ns
260 ns
160 ns
110 ns
15 ns
3.7 ns
5.3 ns
5.355 ns
41~59 Reserved, Base Configuration Section
60
HEX Value
SPD Total: 512Bytes, SPD Used : 384Bytes
-
78~116 Reserved, Base Configuration Section
-
11
288Pin DDR4 2133 1.2V R-DIMM
8GB Based on 1024Mx4
AQD-D4U8GR21-HZ
117
Fine Offset for Minimum CAS to CAS Delay Time(tCCD_Lmin), same bank group
118
Fine Offset for Minimum Activate to Activate Delay Time(tRRD_Lmin), different bank group
119
Fine Offset for Minimum Activate to Activate Delay Time(tRRD_Smin), same bank group
120
Fine Offset for Minimum Activate to Activate/Refresh Delay Time(tRCmin)
121
Fine Offset for Minimum Row Precharge Delay Time(tRPmin)
122
Fine Offset for Minimum RAS to CAS Delay Time(tRCDmin)
123
Fine Offset for Minimum CAS Latency Time(tAAmin)
124
Fine Offset for SDRAM Maximum Cycle Time(tCKAVGmax)
125
Fine Offset for SDRAM Minimum Cycle Time(tCKAVGmin)
126
Cyclical Redundancy Code for Base Configuration Section, LSB
CRC-CCITT(LOW)
127
Cyclical Redundancy Code for Base Configuration Section, MSB
CRC-CCITT(HIGH)
128
(Registered): Raw Card Extension, Module Nominal Height
129
(Registered): Module Maximum Thickness
130
(Registered): Reference Raw Card Used
131
(Registered): DIMM Module Attributes
132
(Registered): RDIMM Thermal Heat Spreader Solution
133
(Registered): Register Manufacturer ID Code, LSB
134
(Registered): Register Manufacturer ID Code, MSB
135
(Registered): Register Revision Number
136
(Registered): Address Mapping from Register to DRAM
Standard
137
(Registered): Register Output Drive Strength for Control
Drive Strength,CS, CA, ODT, CKE - all moderate drive
138
(Registered): Register Output Drive Strength for CK
Revision 0
mm
-
Raw Card C
Revision 0
1 Register/1 Row
Montage
-
Driveve Strength, CK1, CK0 - all moderate drive
139~253 (Registered): Reserved
-
254
(Registered): Cyclical Redundancy Code for Module Specific Section, LSB
CRC-CCITT(LOW)
255
(Registered): Cyclical Redundancy Code for Module Specific Section, MSB
CRC-CCITT(HIGH)
256~319 Hybrid Memory Architecyure Specific Parameters
-
320
Module Manufacturer ID Code, LSB
321
Module Manufacturer ID Code, MSB
322
Module ID: Module Manufacturing Location
*Note: 1
323
Module ID: Module Manufacturing Date(Year)
*Note: 2
324
Module ID: Module Manufacturing Date(Week)
*Note: 3
A-DATA
325~328 Module ID : Module Serial Number
*Note: 4
329~348 Module Part Number
*Note: 5
349
Module Revision Code
350
DRAM Manufacturer's JEDEC ID Code, LSB
351
DRAM Manufacturer's JEDEC ID Code, MSB
352
DRAM Stepping
Hynix Technology
-
353~381 Manufacturer’s Specific Data
382
Reserved
383
Reserved
-
384~511 End User Programmable
*Note: 6
Note :
1. Byte 322 -- Manufacturing location by manufacturing location (00:Taiwan /01:China)
2. Byte 323 -- Module manufacturing date by year (YY).
3. Byte 324 -- Module manufacturing date by week (WW).
4. Bytes 325~328 -- Module Serial Number.
5. Bytes 329~348 -- Manufacturer Part Number by module part number , (Unused digits are coded as ASCII
blanks (20h)).
6. Bytes 353~381 -- These bytes are undefined and can be used for ADATA's own purpose. Digits are coded as
00h except the following:
6-1. Bytes 353~367 -- Manufacturer's Specific Data by working order number.
6-2. Bytes 368~381 -- Manufacturer's Specific Data by SPD naming number.
7. Bytes 384~511 -- These bytes are undefined and can be used for ADATA's own purpose. Digits are coded as
00h except the following:
7-1. Bytes 384 -- The byte is coded as ADh.
12
EC
B4
CE
00
00
00
00
00
C1
1E
BC
11
11
02
05
00
86
32
B1
00
55
05
00
D9
ED
00
04
CB
00
80
AD
FF
00
00
00
-