AQD-SD3L2GN16-SR

204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Advantech AQD-SD3L2GN16-SR Rev. 0.0 2021-01-28 1 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Description Pin Identification AQD-SD3L2GN16-SR is a DDR3L 1600Mbps SO-DIMM high-speed, memory module that use 8pcs of 256Mx 64 Symbol Function bits DDR3L SDRAM in FBGA package and a 2K bits A0~A14, BA0~BA2 Address/Bank input serial EEPROM on a 204-pin printed circuit board. DQ0~DQ63 Bi-direction data bus. DQS0~DQS7 Data strobes /DQS0~/DQS7 Differential Data strobes CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) CKE0, CKE1 Clock Enable Input. on both edges of DQS. Range of operation frequencies, ODT0, ODT1 On-die termination control line programmable latencies allow the same device to be /S0, /S1 DIMM rank select lines. useful for a variety of high bandwidth, high performance /RAS Row address strobe memory system applications. /CAS Column address strobe /WE Write Enable DM0~DM7 Data masks/high data strobes VDD Core power supply  Backward compatible for 1.5V(1.425V~1.575V) VDDQ I/O driver power supply  VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) VREFDQ DQ reference supply AQD-SD3L2GN16-SR is a Dual In-Line Memory Module and is intended for mounting into 204-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible Features  Lead-free and Halogen free products are RoHS Compliant  JEDEC standard 1.35V(1.28V~1.45V) Power supply  MRS Cycle with address key programs Command/address reference - CAS Latency( 5,6,7,8,9,10,11) VREFCA supply - Burst Length (BL):8 and 4 with Burst Chop(BC) VDDSPD  Bi-directional, differential data strobe (DQS and /DQS)  Differential clock input (CK, /CK) operation SPD EEPROM power supply I2C serial bus address select for SA0~SA2  8 bit pre-fetch EEPROM  Double-data-rate architecture; two data transfers per SCL I2C serial bus clock for EEPROM  Internal calibration through ZQ pin SDA I2C serial bus data for EEPROM  On Die Termination with ODT pin VSS Ground /RESET Set DRAMs Known State VTT DRAM I/O termination supply NC No Connection clock cycle  Auto refresh and self refresh Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C  PCB Gold Plating: 30u” min 2 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Dimensions (Unit: millimeter) Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Pin Assignments 204-PIN SODIMM Front PIN 1 Name 204-PIN SODIMM Back PIN Name PIN Name PIN Name PIN Name PIN Name PIN Name PIN Name VREFDQ 53 DQ19 105 VDD 157 DQ42 2 VSS 54 VSS 106 VDD 158 DQ46 A10/AP 159 DQ43 4 DQ4 56 DQ28 108 BA1 160 DQ47 3 VSS 55 VSS 107 5 DQ0 57 DQ24 109 BA0 161 VSS 6 DQ5 58 DQ29 110 /RAS 162 VSS 7 DQ1 59 DQ25 111 VDD 163 DQ48 8 VSS 60 VSS 112 VDD 164 DQ52 9 VSS 61 VSS 113 /WE 165 DQ49 10 /DQS0 62 /DQ3 114 /S0 166 DQ53 11 DM0 63 DM3 115 /CAS 167 VSS 12 DQS0 64 DQ3 116 ODT0 168 VSS 13 VSS 65 VSS 117 VDD 169 /DQS6 14 VSS 66 VSS 118 VDD 170 DM6 15 DQ2 67 DQ26 119 A13 171 DQS6 16 DQ6 68 DQ30 120 ODT1 172 VSS 17 DQ3 69 DQ27 121 /S1 173 VSS 18 DQ7 70 DQ31 122 NC 174 DQ54 19 VSS 71 VSS 123 VDD 175 DQ50 20 VSS 72 VSS 124 VDD 176 DQ55 21 DQ8 73 CKE0 125 TEST 177 DQ51 22 DQ12 74 CKE1 126 VREFCA 178 VSS 23 DQ9 75 VDD 127 VSS 179 VSS 24 DQ13 76 VDD 128 VSS 180 DQ60 25 VSS 77 NC 129 DQ32 181 DQ56 26 VSS 78 A15(NC) 130 DQ36 182 DQ61 27 /DQS1 79 BA2 131 DQ33 183 DQ57 28 DM1 80 A14 132 DQ37 184 VSS 29 DQS1 81 VDD 133 VSS 185 VSS 30 /RESET 82 VDD 134 VSS 186 /DQS7 31 VSS 83 A12//BC 135 /DQS4 187 DM7 32 VSS 84 A11 136 DM4 188 DQS7 33 DQ10 85 A9 137 DQS4 189 VSS 34 DQ14 86 A7 138 VSS 190 VSS 35 DQ11 87 VDD 139 VSS 191 DQ58 36 DQ15 88 VDD 140 DQ38 192 DQ62 37 VSS 89 A8 141 DQ34 193 DQ59 38 VSS 90 A6 142 DQ39 194 DQ63 39 DQ16 91 A5 143 DQ35 195 VSS 40 DQ20 92 A4 144 VSS 196 VSS 41 DQ17 93 VDD 145 VSS 197 SA0 42 DQ21 94 VDD 146 DQ44 198 NC 43 VSS 95 A3 147 DQ40 199 VDDSPD 44 VSS 96 A2 148 DQ45 200 SDA 45 /DQS2 97 A1 149 DQ41 201 SA1 46 DM2 98 A0 150 VSS 202 SCL 47 DQS2 99 VDD 151 VSS 203 VTT 48 VSS 100 VDD 152 /DQS5 204 VTT 49 VSS 101 CK0 153 DM5 50 DQ22 102 CK1 154 DQS5 51 DQ18 103 /CK0 155 VSS 52 DQ23 104 /CK1 156 VSS 4 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR 2GB, 512M x4 Module (1 Rank x16) 5 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Operating Temperature Condition Parameter Symbol Rating Unit Normal Operating Temperature Range TOPER 0 to 85 C Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.4 ~ 1.8 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.4 ~ 1.8 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.8 V 1 Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Symbol Voltage Unit Notes Min Typ. Max 1.35V 1.283 1.35 1.45 V 1.5V 1.425 1.5 1.575 V 1.35V 1.283 1.35 1.45 V Supply voltage for Output VDDQ 1.5V 1.425 1.5 1.575 V I/O Reference Voltage (DQ) VREFDQ(DC) 1.35V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.5V 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ V 1.35V VREF+0.135 V AC Input Logic High VIH(AC) 1.5V VREF+0.175 V 1.35V VREF-0.135 V AC Input Logic Low VIL(AC) 1.5V VREF-0.175 V 1.35V VREF+0.09 VDD V DC Input Logic High VIH(DC) 1.5V VREF+0.1 VDD V 1.35V VSS VREF-0.09 V DC Input Logic Low VIL(DC) 1.5V VSS VREF-0.1 V Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. Supply voltage VDD 6 1, 2 1, 2 3 3 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR IDD Specification parameters Definition - 2GB (1 Rank x16) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Symbol DDR3L 1600 CL11 Unit IDD0 240 mA IDD1 316 mA IDD2P 96 mA IDD2Q 136 mA IDD2N 136 mA IDD3P 180 mA IDD3N 248 mA IDD4R 796 mA IDD4W 640 mA IDD5 716 mA IDD6 72 mA IDD7 880 mA Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: 1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently measured according to DQ loading capacitor. 7 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Timing Parameters & Specifications Speed Parameter DDR3L 1600 Unit Symbol Min Max Average Clock Period tCK 8 - ns CK high-level width tCH 0.47 0.53 tCK CK low-level width tCL 0.47 0.53 tCK tDQSQ - 125 ps DQ output hold time from DQS, /DQS tQH 0.38 - tCK DQ low-impedance time from CK, /CK tLZ(DQ) -450 225 ps tHZ(DQ) - 225 tDS 10 - tDH 45 tDIPW 360 - ps tRPRE 0.9 - tCK DQS, /DQS to DQ skew, per group, per access DQ high-impedance time from CK, /CK Data setup time to DQS, /DQS reference to Vih(ac)Vil(ac) levels Data hold time to DQS, /DQS reference to Vih(ac)Vil(ac) levels DQ and DM input pulse width for each input ps ps ps DQS, /DQS Read preamble DQS, /DQS differential Read postamble DQS, /DQS Write preamble tRPST 0.3 - tCK tWPRE 0.9 - tCK DQS, /DQS Write postamble tWPST 0.3 - tCK tLZ(DQS) -450 225 ps - 225 ps 0.45 0.55 tCK 0.45 0.55 tCK -0.27 0.27 tCK 0.18 - tCK 0.18 - tCK Max (4tck, 7.5ns) - tWR 15 - ns Mode register set command cycle time tMRD 4 - tCK /CAS to /CAS command delay tCCD 4 - nCK Auto precharge write recovery + precharge time tDAL DQS, /DQS low-impedance time DQS, /DQS high-impedance time tHZ(DQS) DQS, /DQS differential input low pulse tDQSL width DQS, /DQS differential input high tDQSH pulse width DQS, /DQS rising edge to CK, /CK tDQSS rising edge DQS, /DQS falling edge setup time to tDSS CK, /CK rising edge DQS, /DQS falling edge hold time to tDSH CK, /CK rising edge Delay from start of Internal write tWTR transaction to Internal read command Write recovery time tWR+tRP/tck 8 nCK 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Active to active command period for 1KB page size Speed Parameter tRRD Max (4tck, 7.5ns) DDR3L 1600 Unit Min Max (4tck, 6ns) Max tFAW 30 - ns Power-up and RESET calibration time tZQinitl 512 - tCK Normal operation Full calibration time tZQoper 256 - tCK tZQcs 64 - tCK tXS Max (5tCK, tRFC+10ns) - tXSDLL tDLL(min) - Active to active command period for 2KB page size Four Activate Window for 1KB page size Normal operation short calibration time Exit self refresh to commands not requiring a locked DLL Exit self refresh to commands requiring a locked DLL Internal read to precharge command delay Minimum CKE low width for Self refresh entry to exit timing Exit power down with DLL to any valid command: Exit Precharge Power Down with DLL CKE minimum pulse width (high and low pulse width) Symbol ns tRRD Max tRTP (4tck, 7.5ns) tCKESR tCK(min)+1tCK Max tXP (3tCK, 6ns) - tCK - tCKE Max (3tCK, 5ns) tAONPD 2 8.5 ns tAOFPD 2 8.5 ns ODT turn-on tAON -225 225 ps ODT turn-off tAOF 0.3 0.7 tCK Asynchronous RTT turn-on delay (Power-Down mode) Asynchronous RTT turn-off delay (Power-Down mode) 9 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR SERIAL PRESENCE DETECT SPECIFICATION (AQD-SD3L2GN16-SR Serial Presence Detect) 10 204Pin DDR3L 1.35V 1600 SO-DIMM 2GB Based on 256M x 16 AQD-SD3L2GN16-SR Note： 1. Byte 119 -- Manufacturing location by manufacturing location (00:Taiwan /01:China) 2. Byte 120 -- Module manufacturing date by year (YY). 3. Byte 121 -- Module manufacturing date by week (WW). 4. Bytes 122~125 -- Module Serial Number. 5. Bytes 128~145 -- Manufacturer Part Number by module part number , (Unused digits are coded as ASCII blanks (20h)). 6. Bytes 152~163 -- Manufacturer's Specific Data by working order number. (Unused digits are coded as 00h.) 7. Bytes 164~175 -- Manufacturer's Specific Data by SPD naming number. (Unused digits are coded as 00h.) 8. Bytes 176~255 --These bytes are undefined and can be used for Advantech's own purpose. (Unused digits are coded as 00h.) 11