AQD-SD4L8GN24-HEI

260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI Advantech AQD-SD4L8GN24-HEI Datasheet Rev. 0.0 2017-05-17 1 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI Description DQ0~DQ63 Bi-direction data bus. DQS0_t–DQS17_t Data Buffer data strobes DQS0_c–DQS17_c Data Buffer data strobes CK0_t, CK1_t Register clock input CK0_c, CK1_c Registert clocks input and is intended for mounting into 260-pin edge connector ODT0 &ODT1 On-die termination control line sockets. CS0_n–CS3_n DIMM Rank Select Lines input. AQD-SD4L8GN24-HEI is a DDR4 2400Mbps SO-DIMM high-speed, memory module that use 8pcs of 1024M x 8 bits DDR4 SDRAM in FBGA package and a 4K bits serial EEPROM on a 260-pin printed circuit board. AQD-SD4L8GN24-HEI is a Dual In-Line Memory Module 2 Row address strobe 3 Column address strobe WE_n 4 Write Enable DM0~DM7 Data masks/high data strobes VDD Core power supply Features VDDQ I/O driver power supply  RoHS compliant products. VREFCA Command/address reference supply  JEDEC standard 1.2V(1.14V~1.26V) Power supply VDDSPD SPD EEPROM power supply Synchronous design allows precise cycle control with the RAS_n use of system clock. Data I/O transactions are possible CAS_n on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. VDDQ= 1.2V(1.14V~1.26V) I2C serial bus address select for SA0~SA2  VPP = 2.5V +0.25V / -0.125V EEPROM  Data transfer rates: PC3-12800 SCL I2C serial bus clock for EEPROM SDA I2C serial bus data for EEPROM VSS Ground RESET_n Set DRAMs Known State  Bi-directional Differential Data-Strobe VTT DRAM I/O termination supply  On Die Termination, Nominal, Park, and Dynamic ODT VPP SDRAM Supply ALERT_n Register ALERT_n output Programmable CAS Latency: 10,11,12,13,14,15,16,17,18  8 bit pre-fetch  Burst Length (BL) switch on-the-fly BL8 or BC4  Serial presence detect with EEPROM Asynchronous reset EVENT_n  Anti - sulfur resistor used RFU  Industrial Temperature( -40°C ~ 95 °C) A0–A171, BA0~BA1 Reserved for future use 1. Address A17 is only valid for 16 Gb x4 based SDRAMs. Pin Identification Symbol SPD signals a thermal event has occurred 2. RAS_n is a multiplexed function with A16. Function 3. CAS_n is a multiplexed function with A15. Address/Bank input 4. WE_n is a multiplexed function with A14. 2 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI Dimensions (Unit: millimeter) Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI Pin Assignments Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back Pin 161 ODT1 201 VSS 241 162 C0,CS2_ n,NC 202 VSS 242 Back D M7_n/D BI7_n, DQS7_t 1 12V 41 DQ10 81 VSS 121 A9 2 VSS 42 DQ11 82 VSS 122 A7 3 DQ5 43 VSS 83 DQ26 123 VSS 4 DQ4 44 VSS 84 DQ27 124 DQ54 163 VDD 203 DQ46 243 VSS 164 VREFCA 204 DQ47 244 VSS 5 VSS 45 DQ21 85 VSS 125 VSS 165 C1,CS3_ n,NC 205 VSS 245 DQ62 6 VSS 46 DQ20 86 VSS 126 DQ50 166 SA2 206 VSS 246 DQ63 7 DQ1 47 VSS 87 CB5, NC 127 VSS 167 VSS 207 DQ42 247 VSS 8 DQ0 48 VSS 88 CB4, NC 128 DQ60 168 VSS 208 DQ43 248 VSS 9 VSS 49 DQ17 89 VSS 129 VDD 169 DQ37 209 VSS 249 DQ58 10 VSS 50 DQ16 90 VSS 130 VDD 170 DQ36 210 VSS 250 DQ59 11 DQ S0_c 51 VSS 91 CB1, NC 131 A3 171 VSS 211 DQ52 251 VSS 12 D M0_n/D BI0_n, NC 52 VSS 92 CB0, NC 132 A2 172 VSS 212 DQ53 252 VSS 13 DQS0_t 53 DQ S2_c 93 VSS 133 A1 173 DQ33 213 VSS 253 SCL VSS 54 D M2_n/D BI2_n, NC 94 VSS 134 EVENT_n 174 DQ32 214 VSS 254 SDA 15 VSS 55 DQS2_t 95 DQ S8_c 135 VDD 175 VSS 215 DQ49 255 VDDSPD 16 DQ6 56 VSS 96 D M8_n/D BI8_n, NC 136 VDD 176 VSS 216 DQ48 256 SA0 17 DQ7 57 VSS 97 DQ S8_t 137 CK0_t 177 VSS 257 VPP VSS 58 DQ22 98 VSS 138 CK1_t 178 218 VSS 258 VTT 19 VSS 59 DQ23 99 VSS 139 CK0_c 179 DQS4_c D M4_n/D BI4_n, DQS4_t 217 18 219 DQS6_c 259 VPP 260 SA1 14 20 DQ2 60 VSS 100 CB6, NC 140 CK1_c 180 VSS 220 D M6_n/D BI6_n, NC 21 DQ3 61 VSS 101 CB2, NC 141 VDD 181 VSS 221 DQS6_t 22 VSS 62 DQ18 102 VSS 142 VDD 182 DQ39 222 VSS 23 VSS 63 DQ19 103 VSS 143 PARITY 183 DQ38 223 VSS 24 DQ12 64 VSS 104 CB7, NC 144 A0 184 VSS 224 DQ54 25 DQ13 65 VSS 105 CB3, NC 145 BA1 185 VSS 225 DQ55 26 VSS 66 DQ28 106 VSS 146 A10/AP 186 DQ35 226 VSS 27 VSS 67 DQ29 107 VSS 147 VDD 187 DQ34 227 VSS 28 DQ8 68 VSS 108 RESET_n 148 VDD 188 VSS 228 DQ50 29 DQ9 69 VSS 109 CKE0 149 CS0_n 189 VSS 229 DQ51 30 VSS 70 DQ24 110 CKE1 150 BA0 190 DQ45 230 VSS 31 VSS 71 DQ25 111 VDD 151 A14/WE_n 191 DQ44 231 VSS 32 DQ S1_c 72 VSS 112 VDD 152 A16/RAS_n 192 VSS 232 DQ60 33 D M1_n/D BI1_n, NC 73 VSS 113 BG1 153 VDD 193 VSS 233 DQ61 34 DQS1_t 74 DQ S3_c 114 ACT_n 154 VDD 194 DQ41 234 VSS 35 VSS 75 D M3_n/D BI3_n, NC 115 BG0 155 ODT0 195 DQ40 235 VSS 36 VSS 76 DQ S3_t 116 ALERT_n 156 A15/CAS_n 196 VSS 236 DQ57 37 DQ15 77 VSS 117 VDD 157 CS1_n 197 VSS 237 DQ56 38 DQ14 78 VSS 118 VDD 158 A13 198 VSS VSS 79 DQ30 119 A12 159 VDD 199 239 VSS 40 VSS 80 DQ31 120 A11 160 VDD 200 DQS5_c D M5_n/D BI5_n, VSS 238 39 240 DQS7_c 4 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI 8GB, 1Gx8 Module (1 Rank x8)  This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. 5 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER -40 to 85 C 1,2 Note: 1. Operating Temperature Tcase is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to the JEDEC document JESD51-2. 2. At -40 - 85C, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1 Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Supply voltage Symbol Voltage Unit Notes Min Typ. Max VDD 1.2V 1.14 1.2 1.26 V 1,2,3 VDDQ 1.2V 1.14 1.2 1.26 V 1,2,3 I/O Reference Voltage (DQ) VREFDQ(DC) I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.2V 1.2V 0.49*VDD 0.49*VDD 0.50*VDD 0.50*VDD 0.51*VDD 0.51*VDD V V 4 4 AC Input Logic High VIH(AC) 1.2V VREF+100 - VDD AC Input Logic Low VIL(AC) 1.2V VSS - VREF–100 mV DC Input Logic High VIH(DC) 1.2V VREF+75 - VDD mV Supply voltage for Output 2 2 mV DC Input Logic Low VIL(DC) 1.2V mV VSS VREF-75 Note: (1) Under all conditions VDDQ must be less than or equal to VDD. (2) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. (3) The DC bandwidth is limited to 200MHz. (4) The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx. ±12mV) 6 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI IDD Specification parameters Definition - 8GB (1 Rank x8) Parameter Symbol Unit 1 304 mA 1 48 mA 1 384 mA 216 mA 256 mA 2 144 mA 2 176 mA 2 360 mA 2 120 mA 2 296 mA 1 992 mA 1 960 mA 1 1568 mA 1 520 mA 2 176 mA 2 224 mA 1 1216 mA 1 152 mA One bank ACTIVATE-PRECHARGE current IDD0 One bank ACTIVATE-PRECHARGE, wordline boost, IPP current IPP0 One Bank Active-Read-Precharge Current IDD1 2 Precharge Standby Current DDR4 2400 CL17 IDD2N Precharge standby ODT current IDD2NT Precharge Power-Down Current IDD2P Precharge Quiet Standby Current IDD2Q Active standby current IDD3N Active standby IPP current IPP3N Active Power-Down Current IDD3P Burst Read Current IDD4R Burst write current IDD4W Burst refresh current (1x REF) IDD5B Burst refresh IPP current (1x REF) IPP5B Self refresh current: Normal temperature range (0–85°C) IDD6N Self refresh current: Extended temperature range (0–95°C) IDD6E Bank interleave read current IDD7 Bank interleave read IPP current IPP7 1 2 mA Maximum power-down current IDD8 96 Note: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3.IDD current measure method and detail patterns are described on DDR4 component datasheet. Only for reference. 7 260Pin DDR4 2400 1.2V SO-DIMM 8GB Based on 1024Mx8 AQD-SD4L8GN24-HEI  Timing Parameters & Specifications Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Average high pulse width Average low pulse width Absolute Clock Period Absolute clock HIGH pulse width Absolute clock LOW pulse width Clock Period Jitter- total Clock Period Jitter- deterministic Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter deterministic Cycle to Cycle Period Jitter during DLL locking period Duty Cycle Jitter Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across 13 cycles Cumulative error across 14 cycles Cumulative error across 15 cycles Cumulative error across 16 cycles Cumulative error across 17 cycles Cumulative error across 18 cycles Cumulative error across n = 13, 14 . . . 49, 50 cycles Command and Address setup time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels Command and Address setup time to CK_t, CK_c referenced to Vref levels Command and Address hold time to CK_t, CK_c referenced to Vih(dc) / Vil(dc) levels Command and Address hold time to CK_t, CK_c referenced to Vref levels Control and Address Input pulse width for each input Command and Address Timing CAS_n to CAS_n command delay for same bank group CAS_n to CAS_n command delay for different bank group ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 1/2KB page size Four activate window for 2KB page size Four activate window for 1KB page size Four activate window for 1/2KB page size Delay from start of internal write transaction to internal read command for different bank group Delay from start of internal write transaction to internal read command for same bank group Internal READ Command to PRECHARGE Command delay WRITE recovery time Symbol tCK (DLL_OFF) tCK(avg) tCH(avg) tCL(avg) tCK(abs) tCH(abs) tCL(abs) JIT(per)_tot JIT(per)_dj tJIT(per, lck) tJIT(cc)_total tJIT(cc)_dj DDR4-1866 MAX MIN 8 1.071