AQD-SD4U4GE21-SG

288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Advantech AQD-SD4U4GE21-SG Datasheet Rev. 1.0 2015-03-16 1 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Description Pin Identification Symbol DDR4 ECC SO-DIMMs are high-speed low power memory modules that use 512Mx8bits DDR4 SDRAM in FBGA package and a 4K-bit serial EEPROM on a 260-pin printed circuit board. DDR4 ECC SO-DIMMs are dual A0–A14 BA0, BA1 SDRAM address bus SDRAM bank select BG0, BG1 RAS_n SDRAM bank group select SDRAM row address strobe CAS_n WE_n In-Line memory modules and are intended for mounting into 260-pin edge connector sockets. The synchronous design allows precise cycle control with CS0_n, CS1_n CKE0, CKE1 the use of system clock. Data I/O transactions are ODT0, ODT1 possible on both edges of DQS. The large range of operation frequencies and programmable latencies allow ACT_n DQ0–DQ63 the same device to be useful for a variety of high CB0–CB7 bandwidth and high performance memory system DM_n/DBI_n/ applications. DQS0_t–DQS8_t Features  RoHS compliant  JEDEC standard 1.2V ± 0.06V power supply  VDDQ=1.2V ± 0.06V  Clock Freq: 1067MHZ for 2133Mb/s/Pin.  Programmable CAS Latency: 10,11,12,13,14,15,16  Programmable Additive Latency (Posted /CAS):  8 bit pre-fetch  Burst Length: 4, 8  Bi-directional Differential Data-Strobe  On Die Termination with ODT pin  Serial presence detect with EEPROM  On DIMM Thermal Sensor  Asynchronous reset SDRAM activate DIMM memory data bus DIMM ECC check bits Input data mask and data bus inversion SDRAM data strobes (positive line of differential pair) SDRAM clocks (positive line of differential pair) VDD VREFCA VSS SDRAM clocks (negative line of differential pair) SDRAM parity input SDRAM I/O and core power supply SDRAM command/address reference supply Power supply return (ground) VDDSPD Serial SPD EEPROM positive power supply SCL SDA I C serial bus clock for EEPROM 2 I C serial bus data line for EEPROM 2 2 SA0–SA2 ALERT_n I C slave address select for EEPROM SDRAM ALERT_n VPP RESET_n SDRAM Supply Set DRAMs to a Known State VTT SPD signals a thermal event has occurred SDRAM I/O termination supply RFU NC Reserved for future use No Connection EVENT_n NF 2 SDRAM on-die termination control lines CK0_t, CK1_t = 11, 14(DDR4-2133)  DIMM Rank Select Lines SDRAM clock enable lines SDRAM data strobes (negative line of differential pair) PARITY Programmable /CAS Write Latency (CWL) SDRAM column address strobe SDRAM write enable DQS0_c–DQS8_c CK0_c, CK1_c 0,CL-2 or CL-1 clock Function No function 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Pin Assignments Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No 90 VSS 178 92 94 180 182 184 VSS 98 CB0/NC VSS DM8_n/ DBI_n/NC VSS Pin Name DM4_n/ DBI4_n VSS DQ39 01 VSS 03 05 DQ5 VSS 89 VSS 177 DQS4_c 91 93 CB1/NC VSS 179 181 DQS4_t VSS 02 VSS 04 06 DQ4 VSS 07 DQ1 95 DQS8_c 183 DQ38 08 DQ0 96 09 VSS 97 DQS8_t 185 VSS 10 VSS 187 DQ34 12 CB2/NC VSS CB3/NC VSS CKE0 189 191 193 195 197 VSS DQ44 VSS DQ40 VSS DM5_n/ DBI5_n VSS DQ46 VSS DQ42 14 16 18 20 22 VSS DM0_n/ DBI0_n VSS DQ6 VSS DQ2 VSS 186 DQ35 11 DQS0_c 99 13 15 17 19 21 DQS0_t VSS DQ7 VSS DQ3 101 103 105 107 109 100 CB6/NC 188 VSS 102 104 106 108 110 VSS CB7/NC VSS RESET_n CKE1 190 192 194 196 198 DQ45 VSS DQ41 VSS DQS5_c 23 VSS 111 VDD 199 24 DQ12 112 VDD 200 DQS5_t 25 27 29 31 113 115 117 119 BG1 BG0 VDD A12 201 203 205 207 121 A9 35 37 39 41 DQ13 VSS DQ9 VSS DM1_n/ DBI_n VSS DQ15 VSS DQ10 26 28 30 32 VSS DQ8 VSS DQS1_c 114 116 118 120 ACT_n ALERT_n VDD A11 202 204 206 208 VSS DQ47 VSS DQ43 123 125 127 129 VDD A8 A6 VDD 209 211 213 215 217 VSS 34 DQS1_t 122 A7 210 VSS DQ52 VSS DQ49 VSS 36 38 40 42 VSS DQ14 VSS DQ11 124 126 128 130 VDD A5 A4 VDD 212 214 216 218 DQS6_c 44 VSS 132 A2 220 DQ53 VSS DQ48 VSS DM6_n/ DBI6_n 43 VSS 131 A3 219 45 DQ21 133 A1 221 DQS6_t 46 DQ20 134 VDD CK0_t CK0_c 223 225 227 VSS DQ55 VSS 48 50 52 136 138 140 141 VDD 229 DQ51 54 142 DQS2_t VSS DQ23 VSS 143 145 147 149 231 233 235 237 VSS DQ61 VSS DQ56 56 58 60 62 144 146 148 150 63 DQ19 151 PARITY BA1 VDD CS0_n WE_n/ A14 VSS DQ16 VSS DM2_n/ DBI2_n VSS DQ22 VSS DQ18 EVENT_n, NF VDD CK1_t/NF CK1_c/NF 47 49 51 VSS DQ17 VSS 135 137 139 53 DQS2_c 55 57 59 61 239 VSS 64 VSS 152 65 VSS 153 VDD 241 DM7_n/ DBI7_n 66 DQ28 154 67 DQ29 155 ODT0 243 VSS 68 VSS 156 69 71 VSS DQ25 157 159 CS1_n VDD 245 247 DQ62 VSS 70 72 DQ24 VSS 158 160 73 VSS 161 ODT1 249 DQ58 74 DQS3_c 162 75 DM3_n/ DBI3_n 163 VDD 251 VSS 76 DQS3_t 164 77 VSS 165 253 SCL 78 VSS 79 81 83 85 87 Note: DQ30 VSS DQ26 VSS CB5/NC 167 169 171 173 175 255 257 259 - VDDSPD VPP VPP - 80 82 84 86 88 DQ31 VSS DQ27 VSS CB4/NC 33 C1, CS3_n, NC VSS DQ37 VSS DQ33 VSS 1. NC for Non ECC SO-DIMM. 4 222 VSS 224 226 228 DQ54 VSS DQ50 VDD 230 VSS A0 A10/AP VDD BA0 RAS_n/ A16 232 234 236 238 DQ60 VSS DQ57 VSS 240 DQS7_c VDD 242 DQS7_t CAS_n/ A15 A13 VDD C0/ CS2_n/NC 244 VSS 246 248 DQ63 VSS 250 DQ59 VREFCA 252 VSS 166 SA2 254 SDA 168 170 172 174 176 VSS DQ36 VSS DQ32 VSS 256 258 260 - SA0 VTT SA1 - 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Block Diagram 4GB, 512Mx72 Module(1 Rank x8) This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. 5 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 85 C 1,2 Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. At 0 - 85C, operation temperature range is the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1 Voltage on VPP pin relative to Vss VPP -0.3 ~ 3.0 V 3 Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1 Storage temperature TSTG -55~+100 C 1,2 Note: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. VPP must be equal or greater than VDD/VDDQ at all times. AC & DC Operating Conditions Recommended DC operating conditions (SSTL –1.5) Rating Parameter Symbol Min Typ. Unit Note s V V V 1, 2 1, 2 3 Max Supply voltage VDD 1.14 1.2 1.26 Supply voltage for Output VDDQ 1.14 1.2 1.26 Wordline supply voltage VPP 2.375 2.5 2.75 Note: Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. DC bandwidth is limited to 20MHz Single-ended AC & DC input levels for Command and Address DDR4-1600/1866/2133 Parameter Symbol Unit Note Min Max I/O Reference Voltage (CMD/ADD) VREFCA(DC) 0.49*VDDQ 0.51*VDDQ V 1,2 DC Input Logic High VIH(DC) VREF+0.075 VDD V DC Input Logic Low VIL(DC) VSS VREF-0.075 V AC Input Logic High VIH(AC) VREF+0.1 Note 1 V AC Input Logic Low VIL(AC) Note 1 VREF-0.1 V Note: The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV) For reference : approx. VDD/2 ± 12mV 6 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Differential AC and DC Input Levels DDR4-1600/1866/2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3 V 1 differential input low DC VILdiff(DC) NOTE 3 -0.150 V 1 differential input high AC VIHdiff(AC) 2 x (VIH(AC) - VREF) NOTE 3 V 2 differential input low AC VILdiff(AC) NOTE 3 2 x (VIL(AC) -VREF) V 2 Note: Used to define a differential signal slew-rate. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA; These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Single-ended AC & DC output levels Parameter Symbol DDR4-1600/1866/2133 Unit Note DC output high measurement level VOH(DC) 1.1 x VDDQ V DC output mid measurement level VOM(DC) 0.8 x VDDQ V DC output low measurement level VOL(DC) 0.5 x VDDQ V AC output high measurement level VOH(AC) (0.7 + 0.15) x VDDQ V 1 AC output low measurement level VOL(AC) (0.7 - 0.15) x VDDQ V 1 Note: The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ. Differential AC & DC output levels Parameter Symbol DDR4-1600/1866/2133 Unit Note AC differential output high VOHdiff(AC) +0.3 x VDDQ V 1 measurement level AC differential output low VOLdiff(AC) -0.3 x VDDQ V 1 measurement level Note: The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs. 7 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG IDD Specification parameters Definition (IDD values are for full operating range of Voltage and Temperature) 4GB, 512Mx72 Module(1 Rank x8) Parameter Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Symbol DDR4 2133 CL15 Unit IDD0 540 mA IDD1 585 mA IDD2P 270 mA IDD2Q 351 mA IDD2N 414 mA IDD3P 396 mA IDD3N 567 mA IDD4R 1350 mA IDD4W 1440 mA IDD5 1710 mA IDD6 180 mA IDD7 1665 mA Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Note: Module IDD was calculated on the specific brand DRAM(2Xnm) component IDD and can be differently measured according to DQ loading capacitor. 8 288Pin DDR4 2133 ECC SODIMM 4GB Based on 512Mx8 AQD-SD4U4GE21-SG Timing Parameters & Specifications Speed Parameter Average Clock Period CK high-level width CK low-level width DQS_t,DQS_c to DQ skew, per group, per access DQS_t,DQS_c to DQ Skew determin-istic, per group, per access DDR4 2133 Unit Symbol tCK tCH tCL Min 0.938 0.48 0.48 Max