AQD-SD4U4GN21-HG

260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Advantech AQD-SD4U4GN21-HG Datasheet Rev. 0.0 2015-12-09 1 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Description DQS0_c–DQS17_c Data Buffer data strobes CK0_t, CK1_t Register clock input CK0_c, CK1_c Registert clocks input ODT0 &ODT1 On-die termination control line CS0_n–CS3_n DIMM Rank Select Lines input. and is intended for mounting into 260-pin edge connector RAS_n2 Row address strobe sockets. CAS_n Synchronous design allows precise cycle control with the WE_n use of system clock. Data I/O transactions are possible DM0~DM7 Data masks/high data strobes VDD Core power supply VDDQ I/O driver power supply VREFCA Command/address reference supply VDDSPD SPD EEPROM power supply AQD-SD4U4GN21-HG is a DDR4 2133Mbps SO-DIMM high-speed, memory module that use 8pcs of 512Mx 64 bits DDR4 SDRAM in FBGA package and a 4K bits serial EEPROM on a 260-pin printed circuit board. AQD-SD4U4GN21-HG is a Dual In-Line Memory Module on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be 3 4 Column address strobe Write Enable useful for a variety of high bandwidth, high performance memory system applications. Features I2C serial bus address select for  RoHS compliant products. SA0~SA2 EEPROM  JEDEC standard 1.2V(1.14V~1.26V) Power supply  VDDQ= 1.2V(1.14V~1.26V) SCL I2C serial bus clock for EEPROM  VPP = 2.5V +0.25V / -0.125V SDA I2C serial bus data for EEPROM VSS Ground RESET_n Set DRAMs Known State VTT DRAM I/O termination supply VPP SDRAM Supply  On Die Termination, Nominal, Park, and Dynamic ODT ALERT_n Register ALERT_n output  Serial presence detect with EEPROM EVENT_n  Data transfer rates: PC3-12800  Programmable CAS Latency: 9,11,12,13,14,15,16  8 bit pre-fetch  Burst Length (BL) switch on-the-fly BL8 or BC4  Bi-directional Differential Data-Strobe  Asynchronous reset RFU SPD signals a thermal event has occurred Reserved for future use  PCB edge connector treated with 30u” Gold-Plating 1. Address A17 is only valid for 16 Gb x4 based SDRAMs. Pin Identification Symbol 2. RAS_n is a multiplexed function with A16. Function 3. CAS_n is a multiplexed function with A15. A0–A171, BA0~BA1 Address/Bank input DQ0~DQ63 Bi-direction data bus. DQS0_t–DQS17_t Data Buffer data strobes 4. WE_n is a multiplexed function with A14. 2 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Dimensions (Unit: millimeter) Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified. 3 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Pin Assignments Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back Pin 161 ODT1 201 VSS 241 162 C0,CS2_ n,NC 202 VSS 242 Back D M7_n/D BI7_n, DQS7_t 1 12V 41 DQ10 81 VSS 121 A9 2 VSS 42 DQ11 82 VSS 122 A7 3 DQ5 43 VSS 83 DQ26 123 VSS 4 DQ4 44 VSS 84 DQ27 124 DQ54 163 VDD 203 DQ46 243 VSS 164 VREFCA 204 DQ47 244 5 VSS 45 DQ21 85 VSS 125 VSS VSS 165 C1,CS3_ n,NC 205 VSS 245 DQ62 6 VSS 46 DQ20 86 VSS 7 DQ1 47 VSS 87 CB5, NC 126 DQ50 166 SA2 206 VSS 246 DQ63 127 VSS 167 VSS 207 DQ42 247 VSS 8 DQ0 48 VSS 88 9 VSS 49 DQ17 89 CB4, NC 128 DQ60 168 VSS 208 DQ43 248 VSS VSS 129 VDD 169 DQ37 209 VSS 249 DQ58 10 VSS 50 DQ16 11 DQ S0_c 51 VSS 90 VSS 130 VDD 170 DQ36 210 VSS 250 DQ59 91 CB1, NC 131 A3 171 VSS 211 DQ52 251 12 D M0_n/D BI0_n, NC VSS 52 13 DQS0_t 53 VSS 92 CB0, NC 132 A2 172 VSS 212 DQ53 252 VSS DQ S2_c 93 VSS 133 A1 173 DQ33 213 VSS 253 SCL 254 SDA 14 VSS 54 D M2_n/D BI2_n, NC 94 VSS 134 EVENT_n 174 DQ32 214 VSS 15 VSS 55 DQS2_t 95 DQ S8_c 135 VDD 175 VSS 215 DQ49 255 VDDSPD 16 DQ6 56 VSS 96 D M8_n/D BI8_n, NC 136 VDD 176 VSS 216 DQ48 256 SA0 17 DQ7 57 VSS 97 DQ S8_t 137 CK0_t 177 217 VSS 257 VPP 18 VSS 58 DQ22 98 VSS 138 CK1_t 178 218 VSS 258 VTT 19 VSS 59 DQ23 99 VSS 139 CK0_c 179 DQS4_c D M4_n/D BI4_n, DQS4_t 219 DQS6_c 259 VPP 20 DQ2 60 VSS 100 CB6, NC 140 CK1_c 180 VSS 220 D M6_n/D BI6_n, NC 260 SA1 21 DQ3 61 VSS 101 CB2, NC 141 VDD 181 VSS 221 DQS6_t 22 VSS 62 DQ18 102 VSS 142 VDD 182 DQ39 222 VSS 23 VSS 63 DQ19 103 VSS 143 PARITY 183 DQ38 223 VSS 24 DQ12 64 VSS 104 CB7, NC 144 A0 184 VSS 224 DQ54 25 DQ13 65 VSS 105 CB3, NC 145 BA1 185 VSS 225 DQ55 26 VSS 66 DQ28 106 VSS 146 A10/AP 186 DQ35 226 VSS 27 VSS 67 DQ29 107 VSS 147 VDD 187 DQ34 227 VSS 28 DQ8 68 VSS 108 RESET_n 148 VDD 188 VSS 228 DQ50 29 DQ9 69 VSS 109 CKE0 149 CS0_n 189 VSS 229 DQ51 30 VSS 70 DQ24 110 CKE1 150 BA0 190 DQ45 230 VSS 31 VSS 71 DQ25 111 VDD 151 A14/WE_n 191 DQ44 231 VSS 32 DQ S1_c 72 VSS 112 VDD 152 A16/RAS_n 192 VSS 232 DQ60 33 D M1_n/D BI1_n, NC 73 VSS 113 BG1 153 VDD 193 VSS 233 DQ61 34 DQS1_t 74 DQ S3_c 114 ACT_n 154 VDD 194 DQ41 234 VSS 35 VSS 75 D M3_n/D BI3_n, NC 115 BG0 155 ODT0 195 DQ40 235 VSS 36 VSS 76 DQ S3_t 116 ALERT_n 156 A15/CAS_n 196 VSS 236 DQ57 37 DQ15 77 VSS 117 VDD 157 CS1_n 197 VSS 237 DQ56 38 DQ14 78 VSS 118 VDD 158 A13 198 238 VSS 39 VSS 79 DQ30 119 A12 159 VDD 199 40 VSS 80 DQ31 120 A11 160 VDD 200 DQS5_c D M5_n/D BI5_n, VSS 4 239 VSS 240 DQS7_c 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG 4GB, 512Mx8 Module (1 Rank x8)  This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes in specifications at any time without prior notice. 5 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Operating Temperature Condition Parameter Symbol Rating Unit Operating Temperature TOPER 0 to 85 C Note: Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. Note 1,2 Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD -0.3 ~ 1.5 V 1 Voltage on VDDQ pin relative to Vss VDDQ -0.3 ~ 1.5 V 1 Voltage on any pin relative to Vss VIN, VOUT -0.3 ~ 1.5 V 1 Storage temperature TSTG -55~+100 C 1,2 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the Note: device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions Rating Parameter Supply voltage Symbol Voltage Unit Notes Min Typ. Max VDD 1.2V 1.14 1.2 1.26 V 1,2,3 VDDQ 1.2V 1.14 1.2 1.26 V 1,2,3 I/O Reference Voltage (DQ) VREFDQ(DC) I/O Reference Voltage (CMD/ADD) VREFCA(DC) 1.2V 1.2V 0.49*VDD 0.49*VDD 0.50*VDD 0.50*VDD 0.51*VDD 0.51*VDD V V 4 4 AC Input Logic High VIH(AC) 1.2V VREF+100 - VDD AC Input Logic Low VIL(AC) 1.2V VSS - VREF–100 mV DC Input Logic High VIH(DC) 1.2V VREF+75 - VDD mV Supply voltage for Output 2 2 mV DC Input Logic Low VIL(DC) 1.2V mV VSS VREF-75 Note: (1) Under all conditions VDDQ must be less than or equal to VDD. (2) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. (3) The DC bandwidth is limited to 200MHz. (4) The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx. ±12mV) 6 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG IDD Specification parameters Definition - 4GB (1 Rank x8) Parameter Symbol DDR4 2133 CL15 One bank ACTIVATE-PRECHARGE current IDD01 224 mA One bank ACTIVATE-PRECHARGE, wordline boost, IPP current IPP01 20.8 mA One Bank Active-Read-Precharge Current IDD11 288 mA IDD2N2 120 mA Precharge standby ODT current IDD2NT1 144 mA Precharge Power-Down Current IDD2P 2 88 mA Precharge Quiet Standby Current IDD2Q 2 120 mA Active standby current IDD3N2 216 mA Active standby IPP current IPP3N 2 20.8 mA Active Power-Down Current IDD3P2 160 mA Burst Read Current IDD4R 1 664 mA Burst write current IDD4W 1 696 mA Burst refresh current (1x REF) IDD5B 1 960 mA Burst refresh IPP current (1x REF) IPP5B 1 173.6 mA Self refresh current: Normal temperature range (0–85°C) IDD6N 2 88 mA Self refresh current: Extended temperature range (0–95°C) IDD6E 2 122 mA Precharge Standby Current Unit Bank interleave read current IDD7 1 888 mA Bank interleave read IPP current IPP71 90.4 mA mA Maximum power-down current IDD82 40 Note: 1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N. 2. All ranks in this IDD/PP condition. 3.IDD current measure method and detail patterns are described on DDR4 component datasheet. Only for reference. 7 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG  Timing Parameters & Specifications Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Average high pulse width Average low pulse width Absolute Clock Period Absolute clock HIGH pulse width Absolute clock LOW pulse width Clock Period Jitter- total Clock Period Jitter- deterministic Clock Period Jitter during DLL locking period Cycle to Cycle Period Jitter Cycle to Cycle Period Jitter deterministic Cycle to Cycle Period Jitter during DLL locking period Duty Cycle Jitter Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14 . . . 49, 50 cycles Command and Address Timing CAS_n to CAS_n command delay for same bank group CAS_n to CAS_n command delay for different bank group ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size ACTIVATE to ACTIVATE Command delay to same bank group for 1/2KB page size Four activate window for 2KB page size Four activate window for 1KB page size Four activate window for 1/2KB page size Delay from start of internal write transaction to internal read command for different bank group Delay from start of internal write transaction to internal read command for same bank group Internal READ Command to PRECHARGE Command delay WRITE recovery time Write recovery time when CRC and DM are enabled delay from start of internal write transaction to internal read command for different bank group with both CRC and DM enabled delay from start of internal write transaction to internal read command for same bank group with both CRC and DM enabled DLL locking time Mode Register Set command cycle time Mode Register Set command update delay Multi-Purpose Register Recovery Time Multi Purpose Register Write Recovery Time Symbol tCK (DLL_OFF) tCK(avg) tCH(avg) tCL(avg) tCK(abs) tCH(abs) tCL(abs) JIT(per)_tot JIT(per)_dj tJIT(per, lck) tJIT(cc)_total tJIT(cc)_dj DDR4-2133 MAX MIN 8 tbd –(Definition tbd) 0.48 0.52 0.48 0.52 tCK(avg)min + tCK(avg)max + tJIT(per)min_to t tJIT(per)m ax_tot 0.45 0.45 -0.1 0.1 TBD TBD TBD TBD 0.2 TBD ns ps tCK(avg) tCK(avg) TBD UI tJIT(cc, lck) tJIT(duty) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) Units TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tERR(nper) tCK(avg) tCK(avg) tCK(avg) UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI UI tCCD_L 5 - nCK tCCD_S 4 - nCK tRRD_S(2K) Max(4nCK,5.3ns) - nCK tRRD_S(1K) Max(4nCK,3.7ns) - nCK tRRD_S(1/2K) Max(4nCK,3.7ns) - nCK tRRD_L(2K) Max(4nCK,6.4ns) - nCK tRRD_L(1K) Max(4nCK,5.3ns) - nCK tRRD_L(1/2K) Max(4nCK,5.3ns) - nCK tFAW_2K tFAW_1K tFAW_1/2K 30 21 15 - ns ns ns tWTR_S max(2nCK,2.5ns) - tWTR_L max(4nCK,7.5ns) - tRTP max(4nCK,7.5ns) - tWR 15 tWR+max (5nCK,3.75ns) - ns - ns tWR_CRC _DM tWTR_S_C RC_DM tWTR_S+max (5nCK,3.75ns) - ns tWTR_L_C RC_DM tWTR_L+max (5nCK,3.75ns) - ns tDLLK tMRD tMOD tMPRR tWR_MPR TBD 8 max(24nCK,15ns) 1 tMOD (min) - nCK nCK 8 nCK 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Speed Parameter Clock Timing CS_n to Command Address Latency CS_n to Command Address Latency DRAM Data Timing DQS_t,DQS_c to DQ skew, per group, per access DQS_t,DQS_c to DQ Skew deterministic, per group, per access DQ output hold time from DQS_t,DQS_c DQ output hold time deterministic from DQS_t, DQS_c DQS_t,DQS_c to DQ Skew total, per group, per access;DBI enabled DQ output hold time total from DQS_t, DQS_c; DBI enabled DQ to DQ offset , per group, per access referenced to DQS_t, DQS_c Data Strobe Timing DQS_t,DQS_c differential output high time DQS_t,DQS_c differential output low time MPSM Timing Command path disable delay upon MPSM entry Symbol 4 - nCK tDQSQ - TBD tCK(avg)/2 tDQSQ - TBD tCK(avg)/2 tQH tQH TBD TBD - tCK(avg)/2 UI tDQSQ - TBD UI tQH TBD - UI tDQSQ TBD TBD UI tQSH tQSL TBD TBD TBD TBD tCK(avg)/2 tCK(avg)/2 tMPED tCKMPE Valid clock requirement before MPSM exit tCKMPX Exit MPSM to commands requiring a locked DLL CS setup time to CKE CS hold time to CKE Calibration Timing Power-up and RESET calibration time Normal operation Full calibration time Normal operation Short calibration time Reset/Self Refresh Timing Exit Reset from CKE HIGH to a valid command Exit Self Refresh to commands not requiring a locked DLL SRX to commands not requiring a locked DLL in Self Refresh ABORT Exit Self Refresh to ZQCL,ZQCS and MRS (CL,CWL,WR,RTP and Gear Down) Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self refresh entry to exit timing Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down when CA Parity is enabled Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit Power Down Timing Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL CKE minimum pulse width Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE or PREA command to Power Down entry Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry Units tCAL Valid clock requirement after MPSM entry Exit MPSM to commands not requiring a locked DLL DDR4-2133 MAX MIN tXMP tMOD(min) + tCPDED(min) tMOD(min) + tCPDED(min) tCKSRX(min) TBD - tMPX_S tMPX_H tXMP(min) + tXSDLL(min) TBD TBD tZQinit tZQoper tZQCS 1024 512 128 - tXPR max (5nCK,tRFC(min)+ 10ns) - tXS tRFC(min)+10ns - tXS_ABORT(min) tRFC4(min)+10ns - tXS_FAST (min) tRFC4(min)+10ns - tXSDLL tDLLK(min) - tCKESR tCKE(min)+1nCK - tCKSRE max(5nCK,10ns) - tCKSRE_PAR max (5nCK,10ns)+PL - tCKSRX max(5nCK,10ns) - tXP max (4nCK,6ns) - tCKE tCPDED tPD tACTPDEN max (3nCK, 5ns) 4 tCKE(min) 2 9*tREFI - tPRPDEN 2 - nCK tRDPDEN RL+4+1 WL+4+(tWR/ tCK(avg)) - nCK - nCK tWRAPDEN WL+4+WR+1 - nCK tWRPBC4DEN WL+2+(tWR/ tCK(avg)) - nCK tWRAPBC4DEN WL+2+WR+1 - nCK tREFPDEN tMRSPDEN 1 tMOD(min) - nCK tXMPDLL tWRPDEN 9 nCK nCK nCK nCK nCK 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG Speed Parameter Clock Timing PDA Timing Mode Register Set command cycle time in PDA mode Mode Register Set command update delay in PDA mode ODT Timing Asynchronous RTT turn-on delay (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT dynamic change skew Write Leveling Timing First DQS_t/DQS_n rising edge after write leveling mode is programmed DQS_t/DQS_n delay after write leveling mode is programmed Write leveling setup time from rising CK_t, CK_c crossing to rising DQS_t/DQS_n crossing Write leveling hold time from rising DQS_t/DQS_n crossing to rising CK_t, CK_ crossing Write leveling output delay Write leveling output error CA Parity Timing Commands not guaranteed to be executed during this time Delay from errant command to ALERT_n assertion Pulse width of ALERT_n signal when asserted Time from when Alert is asserted till controller must start providing DES commands in Persistent CA parity mode Parity Latency CRC Error Reporting CRC error to ALERT_n latency CRC ALERT_n pulse width tREFI tRFC1 (min) tRFC2 (min) tRFC4 (min) Symbol tMRD_PDA DDR4-2133 MAX MIN Units max(16nCK,10ns) tMOD tMOD_PDA tAONAS 1.0 9.0 ns tAOFAS 1.0 9.0 ns tADC 0.3 0.7 tCK(avg) tWLMRD 40 - nCK tWLDQSEN 25 - nCK tWLS 0.13 - tCK(avg) tWLH 0.13 - tCK(avg) tWLO tWLOE 0 9.5 ns ns tPAR_UNKNOWN - Max(2nCK,3ns) tPAR_ALERT_ON - PL+6ns tPAR_ALERT_PW 64 128 nCK tPAR_ALERT_RSP - 57 nCK 4 PL nCK tCRC_ALERT CRC_ALERT_PW 6 13 10 ns nCK 2Gb 4Gb 8Gb 16Gb 2Gb 4Gb 8Gb 16Gb 2Gb 4Gb 8Gb 16Gb 160 260 350 TBD 110 160 260 TBD 90 110 160 TBD - ns ns ns ns ns ns ns ns ns ns ns ns 10 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG SERIAL PRESENCE DETECT SPECIFICATION (AQD-SD4U4GN21-HG Serial Presence Detect) Function Described Byte 0 Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage 1 SPD Revision 2 Key Byte / DRAM Device Type 3 Key Byte / Module Type 4 SDRAM Density and Banks 5 SDRAM Addressing 6 SDRAM Package Type 7 SDRAM Optional Features 8 SDRAM Thermal and Refresh Options 9 Other SDRAM Optional Features 10 Reserved 11 Module Nominal Voltage, VDD 12 Module Organization 13 Module Memory Bus Width 14 Module Thermal Sensor 15~16 Function 23 Version 1.0 10 0C 03 84 19 00 08 00 40 00 03 01 03 00 00 00 08 0C F4 03 00 00 6C 6C 6C 11 08 74 20 08 00 05 70 03 00 A8 1E 2B 2B 00 0E 2E 2E 04 03 23 24 04 00 00 24 04 04 24 24 04 04 2E 00 DDR4 SDRAM SO-DIMM 4 bank group / 4 bank 4Gb Row : 15 Column : 10 Mono / Not specified Unlimited MAC Post package repair supported 1.2V 1Rank x8 Non-ECC 64bits Non Thermal Sensor Reserved - 17 Timebases 18 SDRAM Minimum Cycle Time (tCKAVGmin) 19 SDRAM Maximum Cycle Time (tCKAVGmax) 20 CAS Latencies Supported, First Byte 21 CAS Latencies Supported, Second Byte 22 CAS Latencies Supported, Third Byte 23 CAS Latencies Supported, Fourth Byte 24 Minimum CAS Latency Time(tAAmin) 13.5 ns 25 Minimum RAS to CAS Delay Time (tRCDmin) 13.5 ns 26 Minimum Row Precharge Delay Time (tRPmin) 13.5 ns 27 Upper Nibbles for tRASmin and tRCmin 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 30 Minimum Refresh Recovery Delay Time (tRFC1min), Least Significant Byte 31 Minimum Refresh Recovery Delay Time (tRFC1min), Most Significant Byte 32 Minimum Refresh Recovery Delay Time (tRFC2min), Least Significant Byte 33 Minimum Refresh Recovery Delay Time (tRFC2min), Most Significant Byte 34 Minimum Refresh Recovery Delay Time (tRFC4min), Least Significant Byte 35 Minimum Refresh Recovery Delay Time (tRFC4min), Most Significant Byte 36 Minimum Four Activate Window Time (tFAWmin), Most Significant Nibble 37 Minimum Four Activate Window Time (tFAWmin), Least Significant Byte 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group 41~59 HEX Value SPD Total: 512Bytes, SPD Used : 384Bytes MTB: 125ps FTB: 1ps 0.938 ns 1.5 ns CL 9,11,12,13,14 CL 15,16 - 33 ns 46.5 ns 260 ns 160 ns 110 ns 21 ns 3.7 ns 5.3 ns 5.355 ns Reserved, Base Configuration Section - 60 Connector to SDRAM Bit Mapping DQ0, DQ1, DQ2, DQ3 61 Connector to SDRAM Bit Mapping DQ4, DQ5, DQ6, DQ7 62 Connector to SDRAM Bit Mapping DQ8, DQ9, DQ10, DQ11 63 Connector to SDRAM Bit Mapping DQ12, DQ13, DQ14, DQ15 64 Connector to SDRAM Bit Mapping DQ16, DQ17, DQ18, DQ19 65 Connector to SDRAM Bit Mapping DQ20, DQ21, DQ22, DQ23 66 Connector to SDRAM Bit Mapping DQ24, DQ25, DQ26, DQ27 67 Connector to SDRAM Bit Mapping DQ28, DQ29, DQ30, DQ31 68 Connector to SDRAM Bit Mapping CB0-3 69 Connector to SDRAM Bit Mapping CB4-7 70 Connector to SDRAM Bit Mapping DQ32, DQ33, DQ34, DQ35 71 Connector to SDRAM Bit Mapping DQ36, DQ37, DQ38, DQ39 72 Connector to SDRAM Bit Mapping DQ40, DQ41, DQ42, DQ43 73 Connector to SDRAM Bit Mapping DQ44, DQ45, DQ46, DQ47 74 Connector to SDRAM Bit Mapping DQ48, DQ49, DQ50, DQ51 75 Connector to SDRAM Bit Mapping DQ52, DQ53, DQ54, DQ55 76 Connector to SDRAM Bit Mapping DQ56, DQ57, DQ58, DQ59 77 Connector to SDRAM Bit Mapping DQ60, DQ61, DQ62, DQ63 78~116 Reserved, Base Configuration Section - 11 260Pin DDR4 2133 1.2V SO-DIMM 4GB Based on 512Mx8 AQD-SD4U4GN21-HG 117 Fine Offset for Minimum CAS to CAS Delay Time(tCCD_Lmin), same bank group -0.02ns 118 Fine Offset for Minimum Activate to Activate Delay Time(tRRD_Lmin), different bank group -0.076ns 119 Fine Offset for Minimum Activate to Activate Delay Time(tRRD_Smin), same bank group -0.05ns 120 Fine Offset for Minimum Activate to Activate/Refresh Delay Time(tRCmin) 0ns 121 Fine Offset for Minimum Row Precharge Delay Time(tRPmin) 0ns 122 Fine Offset for Minimum RAS to CAS Delay Time(tRCDmin) 0ns 123 Fine Offset for Minimum CAS Latency Time(tAAmin) 0ns 124 Fine Offset for SDRAM Maximum Cycle Time(tCKAVGmax) 125 Fine Offset for SDRAM Minimum Cycle Time(tCKAVGmin) 126 Cyclical Redundancy Code for Base Configuration Section, LSB CRC-CCITT(LOW) 127 Cyclical Redundancy Code for Base Configuration Section, MSB CRC-CCITT(HIGH) 128 (Unbuffered): Raw Card Extension, Module Nominal Height 129 (Unbuffered): Module Maximum Thickness 130 (Unbuffered): Reference Raw Card Used 131 (Unbuffered): Address Mapping from Edge Connector to DRAM 0ns -0.063ns Revision 0 30.00 mm - Raw Card A Revision 0 Standard 132~253 (Unbuffered): Reserved - 254 (Unbuffered): CRC for Module Specific Section, Least Significant Byte CRC-CCITT(LOW) 255 (Unbuffered): CRC for Module Specific Section, Most Significant Byte CRC-CCITT(HIGH) 256~319 Hybrid Memory Architecture Specific Parameters 320 Module Manufacturer ID Code, LSB 321 Module Manufacturer ID Code, MSB 322 Module ID: Module Manufacturing Location *Note: 1 323 Module ID: Module Manufacturing Date(Year) *Note: 2 324 Module ID: Module Manufacturing Date(Week) *Note: 3 ADATA 325~328 Module ID : Module Serial Number *Note: 4 329~348 Module Part Number *Note: 5 349 Module Revision Code 350 SDRAM Manufacturer's JEDEC ID Code, LSB 351 SDRAM Manufacturer's JEDEC ID Code, MSB 352 DRAM Stepping Hynix - 353~381 Manufacturer’s Specific Data 382 Reserved 383 Reserved *Note: 6 384~511 End User Programmable *Note: 7 EC B4 CE 00 00 00 00 00 C1 1E 93 0F 11 00 00 00 45 AD 00 04 CB 00 80 AD FF 00 00 - Note : 1. Byte 322 -- Manufacturing location by manufacturing location (00:Taiwan /01:China) 2. Byte 323 -- Module manufacturing date by year (YY). 3. Byte 324 -- Module manufacturing date by week (WW). 4. Bytes 325~328 -- Module Serial Number. 5. Bytes 329~348 -- Manufacturer Part Number by module part number , (Unused digits are coded as ASCII blanks (20h)). 6. Bytes 353~381 -- These bytes are undefined and can be used for ADATA's own purpose. Digits are coded as 00h except the following: 6-1. Bytes 353~367 -- Manufacturer's Specific Data by working order number. 6-2. Bytes 368~381 -- Manufacturer's Specific Data by SPD naming number. 7. Bytes 384~511 -- These bytes are undefined and can be used for ADATA's own purpose. Digits are coded as 00h except the following: 7-1. Bytes 384 -- The byte is coded as ADh. 12