SQR-SD3M-8G1600SNL

SQRAM SQR-SD3M-8G1600SNL Datasheet Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 1 of 14 Sep. 10, 2014 SQRAM CONTENTS 1. Description......................................................................................... 4 2. Features ............................................................................................. 4 3. Dimensions (millimeter) ................................................................... 5 4. Pin Identification ............................................................................... 6 5. Pinouts ............................................................................................... 7 6. Parameter & Operating Conditions ................................................. 8 Appendix: Part Number Table ........................................................... 14 Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 2 of 14 Sep. 10, 2014 SQRAM Revision History Rev. Date History st 1.0 2013/4/26 1. 1 release 1.1 2013/6/26 1. 2 1.2 2013/11/12 1. Correct operation temperature 1.3 2014/9/10 1. Update Operating Temperature Condition nd release Advantech reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Advantech is believed to be accurate and reliable. However, Advantech does not assure any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. Copyright © 1983-2014 Advantech Co., Ltd. All rights reserved. Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 3 of 14 Sep. 10, 2014 SQRAM 1. Description The SQR-SD3M-8G1600SNL DDR3 Industrial 1.35V SO-DIMM is high-speed, low power memory module that use 512Mx8bits DDR3 SDRAM in FBGA package and a 2048 bits serial EEPROM on a 204-pin printed circuit board. DDR3 Industrial 1.35V SO-DIMM is a Dual In-Line Memory Module and is intended for mounting into 204-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. 2. Features  Industrial Temperature : -20°C to +85°C  Gold plating of PCB gold finger is 30u”  RoHS compliant products.  JEDEC standard 1.35V (1.28V~1.45V) Power supply  JEDEC standard 1.5V (1.425V~1.575V) Power supply  VDDQ= 1.35V (1.28V~1.45V) & 1.5V (1.425V~1.575V)  Max clock Freq: 800MHZ for 1600Mb/s/Pin.  Programmable CAS Latency: 5, 6, 7, 8, 9, 10, 11  Programmable Additive Latency (Posted /CAS): 0, CL-2 or CL-1 clock  Programmable /CAS Write Latency (CWL) = 8 (DDR3-1600)  8 bit pre-fetch  Burst Length: 4, 8  Bi-directional Differential Data-Strobe  Internal calibration through ZQ pin  On Die Termination with ODT pin  Serial presence detect with EEPROM  Asynchronous reset Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 4 of 14 Sep. 10, 2014 SQRAM 3. Dimensions (millimeter) Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 5 of 14 Sep. 10, 2014 SQRAM 4. Pin Identification Symbol Function A0~A15, BA0~BA2 Address/Bank input DQ0~DQ63 Data Input / Output. DQS0~DQS7 Data strobe /DQS0~/DQS7 Differential Data strobe CK0, /CK0 CK1, /CK1 Clock Input. (Differential pair) CKE0, CKE1 Clock Enable Input. ODT0, ODT1 On-die termination control line /CS0, /CS1 DIMM Rank Select Lines. /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DM0~DM7 VDD Data masks/high data strobes Voltage power supply VDDQ Voltage Power Supply for DQS VREF Power Supply for Reference VDDSPD SPD EEPROM Power Supply SA0~SA2 I2C serial bus address select for EEPROM SCL I2C serial bus clock for EEPROM SDA I2C serial bus data for EEPROM VSS Ground /RESET Set DRAMs Known State VTT SDRAM I/O termination supply NC No Connection Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 6 of 14 Sep. 10, 2014 SQRAM 5. Pinouts No. Name No. Name No. Name No. Name No. Name No. Name 1 VREFDQ 69 DQ27 137 DQS4 2 VSS 70 DQ31 138 VSS 3 VSS 71 VSS 139 VSS 4 DQ4 72 VSS 140 DQ38 5 DQ0 73 CKE0 141 DQ34 6 DQ5 74 CKE1 142 DQ39 7 DQ1 75 VDD 143 DQ35 8 VSS 76 VDD 144 VSS 9 VSS 77 NC 145 VSS 10 DQS0 78 A15 146 DQ44 11 DM0 79 BA2 147 DQ40 12 / DQS0 80 A14 148 DQ45 13 VSS 81 VDD 149 DQ41 14 VSS 82 VDD 150 VSS 15 DQ2 83 A12 151 VSS 16 DQ6 84 A11 152 /DQS5 17 DQ3 85 A9 153 DM5 18 DQ7 86 A7 154 DQS5 19 VSS 87 VDD 155 VSS 20 VSS 88 VDD 156 VSS 21 DQ8 89 A8 157 DQ42 22 DQ12 90 A6 158 DQ46 23 DQ9 91 A5 159 DQ43 24 DQ13 92 A4 160 DQ47 25 VSS 93 VDD 161 VSS 26 VSS 94 VDD 162 VSS 27 /DQS1 95 A3 163 DQ48 28 DM1 96 A2 164 DQ52 29 DQS1 97 A1 165 DQ49 30 /RESET 98 A0 166 DQ53 31 VSS 99 VDD 167 VSS 32 VSS 100 VDD 168 VSS 33 DQ10 101 CK0 169 /DQS6 34 DQ14 102 CK1 170 DM6 35 DQ11 103 /CK0 171 DQS6 36 DQ15 104 /CK1 172 VSS 37 VSS 105 VDD 173 VSS 38 VSS 106 VDD 174 DQ54 39 DQ16 107 A10/AP 175 DQ50 40 DQ20 108 BA1 176 DQ55 41 DQ17 109 BA0 177 DQ51 42 DQ21 110 /RAS 178 VSS 43 VSS 111 VDD 179 VSS 44 VSS 112 VDD 180 DQ60 45 /DQS2 113 /WE 181 DQ56 46 DM2 114 /CS0 182 DQ61 47 DQS2 115 /CAS 183 DQ57 48 VSS 116 ODT0 184 VSS 49 VSS 117 VDD 185 VSS 50 DQ22 118 VDD 186 /DQS7 51 DQ18 119 A13 187 DM7 52 DQ23 120 ODT1 188 DQS7 53 DQ19 121 /CS1 189 VSS 54 VSS 122 NC 190 VSS 55 VSS 123 VDD 191 DQ58 56 DQ28 124 VDD 192 DQ62 57 DQ24 125 TEST 193 DQ59 58 DQ29 126 VREFCA 194 DQ63 59 DQ25 127 VSS 195 VSS 60 VSS 128 VSS 196 VSS 61 VSS 129 DQ32 197 SA0 62 /DQS3 130 DQ36 198 /EVENT 63 DM3 131 DQ33 199 VDDSPD 64 DQS3 132 DQ37 200 SDA 65 VSS 133 VSS 201 SA1 66 VSS 134 VSS 202 SCL 67 DQ26 135 /DQS4 203 Vtt 68 DQ30 136 DM4 204 Vtt * Please refer Block Diagram Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 7 of 14 Sep. 10, 2014 SQRAM 6. Parameter & Operating Conditions Operating Temperature Condition Parameter Symbol Rating Unit Notes Operating Temperature TOPER -20 to 85 C 1,2 Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. At -20 - 85C, operation temperature range are the temperature which all DRAM specification will be supported. Absolute Maximum DC Ratings Parameter Symbol Value Unit Notes VDD -0.4 ~ 1.975 V 1 VDDQ -0.4 ~ 1.975 V 1 VIN, VOUT -0.4 ~ 1.975 V 1 TSTG -55~+100 °C 1,2 Voltage on VDD relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage temperature Note: 1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC operating conditions (SSTL –1.5) Parameter Supply voltage Supply voltage for Output Symbol VDD VDDQ I/O Reference voltage (DQ) VREFDQ(DC) I/O Reference voltage (CMD/ADD) VREFCA(DC) AC Input logic high VIH(AC) AC Input logic low VIL(AC) DC Input logic high VIH(DC) DC Input logic low VIL(DC) Note: Rating Voltage Unit Notes V 1,2 V 1,2 0.51*VDDQ V 3 0.51*VDDQ V 3 Min Typ. Max 1.35V 1.283 1.35 1.45 1.5V 1.425 1.5 1.575 1.35V 1.283 1.35 1.45 1.5V 1.425 1.5 1.575 0.49*VDDQ 0.50*VDDQ 0.49*VDDQ 0.50*VDDQ VREF+0.160 VREF+0.175 - 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V VREF+0.09 VREF+0.1 - VSS VSS - V VREF-0.160 VREF-0.175 V VDD VDD VREF-0.09 VREF-0.1 V V There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance. 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together. 3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD. Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 8 of 14 Sep. 10, 2014 SQRAM IDD Specification parameters Definition IDD values are for full operating range of voltage and Temperature Parameter Symbol Max. Unit Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address IDD0 760 mA bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = IDD1 856 mA tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other IDD2P 592 mA control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are IDD2Q 752 mA FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are IDD2N 800 mA SWITCHING Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other IDD3P 1008 mA control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control IDD3N 992 mA and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = IDD4R 1,656 mA tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is IDD4W 1,480 mA HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IDD4R Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and IDD5 1,920 mA address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE ≒ 0.2V; Other control and address IDD6 352 mA bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid IDD7 2,480 mA commands; Address bus inputs are STABLE during Deselects; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ Note: loading capacitor. Specifications subject to change without notice, contact your sales representatives for the most update information. REV 1.3 Page 9 of 14 Sep. 10, 2014 SQRAM Timing Parameters & Specifications Parameter Symbol Min Max Unit Average Clock Period, CL=7 tCK 1.25