ACT-5230PC-133F22I

ACT5230 32-Bit Superscaler Microprocessor Features s s Full militarized QED RM5230 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle q 100, s High-performance floating point unit q Single 133 and 150 MHz operating frequency – Consult Factory for latest speeds q 228 Dhrystone2.1 MIPS q SPECInt95 4.2 SPECfp95 4.5 s cycle repeat rate for common single precision operations and some double precision operations q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations q Single cycle repeat rate for single precision combined multiply-add operation s System interface optomized for embedded applications q 32-bit MIPS IV instruction set q Floating system interface lowers total system cost with up to 87.5 MHz operating frequency q High performance write protocols maximize uncached write bandwidth q Operates at processor clock divisors 2 through 8 q 5V tolerant I/O's q IEEE 1149.1 JTAG boundary scan s point multiply-add instruction increases performance in signal processing and graphics applications q Conditional moves to reduce branch frequency q Index address modes (register + register) s Embedded application enhancements q Specialized Integrated on-chip caches q 16KB q 16KB instruction - 2 way set associative data - 2 way set associative q Virtually indexed, physically tagged q Write-back and write-through on per page basis q Early restart on data cache misses s DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction q I and D cache locking by set q Optional dedicated exception vector for interrupts s Fully static CMOS design with power down logic Standby reduced power mode with WAIT instruction Watts typical with less than 70 mA standby current 128-pin Power Quad-4 package (F22), Consult Factory for package configuration q q 2.5 s Integrated memory management unit q Fully q 48 associative joint TLB (shared by I and D translations) dual entries map 96 pages q Variable page size (4KB to 16MB in 4x increments) Block Diagram Data Set A Store Buffer Phase Lock Loop Instruction Set A Data Tag A DTLB Physical Data Tag B Instruction Select Sys AD Integer Instruction Register Write Buffer Read Buffer Data Set B Instruction Tag B DBus FPIBus Control Tag Floating-point Register File Floating point Control Unpacker/Packer Aux Tag Load Aligner Joint TLB Integer Register File Integer/Address Adder Integer Control Coprocessor 0 DVA System/Memory Control IVA Data TLB Virtual IntIBus Address Buffer Instruction Tag A ITLB Physical Instruction Set B FP Instruction Register Floating-point MAdd, Add, Sub,Cvt Div, SqRt Shifter/Store Aligner Logic Unit ABus PC Incrementer Branch Adder Instruction TLB Virtual Integer Multiply, Divide Program Counter Preliminary eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5230 REV 1 12/22/98 DESCRIPTION The ACT5230 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 32-bit system interface. The ACT5230 can issue both an integer and a floating point instruction in the same cycle. The ACT5230 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization. therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5230 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5230 datasheet,, these instructions are integer multiply-accumulate and 3-operand integer multiply. The ACT5230 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/ divide operations, and the program counter(PC). Register File The ACT5230 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. HARDWARE OVERVIEW The ACT5230 offers a high-level of integration targeted at high-performance embedded applications. Some of the key elements of the ACT5230 are briefly described below. Superscalar Dispatch The ACT5230 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5230 provides unparalleled price/performance in computationally intensive embedded applications. ALU The ACT5230 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle CPU Registers Like all MIPS ISA processors, the ACT5230 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. For Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark™ RM5230™, 32-Bit Superscalar Microprocessor see the QED datasheet (Revision 1.2 July 1998). Pipeline For integer operations, loads, stores, and other non-floating-point operations, the ACT5230 uses the simple 5-stage pipeline also found in the QED circuits R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5230 uses an extended seven stage pipeline for floating-point operations. Like the QED R5000, the ACT5230 does virtual to physical translation in parallel with cache access. Integer Unit Like the QED R5000, the ACT5230 implements the MIPS IV Instruction Set Architecture, and is Aeroflex Circuit Technology 2 SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700 Absolute Maximum Ratings1 Symbol TTERM TCASE TBIAS TSTG IIN IOUT Rating Terminal Voltage with respect to GND Operating Temperature Case Temperature under Bias Storage Temperature DC Input Current DC Output Current Range -0.52 to 4.6 0 to +85 -55 to +125 -55 to +125 203 50 Units V °C °C °C mA mA Notes: 1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. VIN minimum = -2.0V for pulse width less than 15nS. VIN maximum should not exceed +5.5 Volts. 3. When VIN < 0V or VIN > Vcc. 4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second. Recommended Operating Conditions Symbol VCC VIH VIL TC Parameter Power Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Case (Commercial) Minimum +3.135 0.7VCC -0.5 0 Maximum +3.465 VCC + 0.5 0.2VCC +85 Units V V V °C DC Characteristics (VCC = 3.3V ±5%; TCASE = 0°C to +85°C) Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Input High Voltage Input Low Voltage Input Current Input Current Input Current Input Capacitance Output Capacitance Sym VOL1 VOH1 VOL2 VOH2 VIH VIL IIN1 IIN2 IIN3 CIN COUT VIN = 0V VIN = VCC VIN = 5.5V IOL = 20 µA IOL = 20 µA IOL = 4 mA IOL = 4 mA 2.4 0.7VCC -0.5 -20 -20 -250 VCC + 0.5 0.2VCC +20 +20 +250 10 10 Vcc - 0.1 0.4 Conditions 133 / 150MHz Min Max 0.1 Units V V V V V V µA µA µA pF pF Aeroflex Circuit Technology 3 SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700 Power Consumption Parameter Active Operating Supply Current Symbol ICC1 ICC2 ICC3 Standby Current ISB1 ISB1 Conditions CL = 0pF, 150/75MHz, No SysAD activity CL = 50pF, 150/75MHz, R4000 write protocol without FPU operation CL = 50pF, 150/75MHz, write re-issue or pipelined writes CL = 0pF, 150/75MHz CL = 50pF, 150/75MHz 133MHz, 3.3V Typ 5 150MHz, 3.3V Typ5 TBD 1150 1250 Max TBD 1950 2250 TBD TBD Max TBD 1750 2000 TBD TBD Units mA mA mA mA mA TBD 1000 1100 Notes: 5. Typical integer instruction mix and cache miss rates. AC Characteristics (VCC = 3.3V ±5%; TCASE = 0°C to +85°C) Capacitive Load Deration 133 / 150MHz Symbol CLD Load Derate Parameter Minimum Maximum 2 ns/25pF Units Clock Parameters 133/150MHz Parameter SysClock High SysClock Low SysClock Frequency6 SysClock Period Clock Jitter for SysClock SysClock Rise Time SysClock Fall Time ModeClock Period JTA Clock Period tSCP tJitterIn tSCRise tSCFall tModeCKP tJTAGCKP Symbol tSCHigh tSCLow Transition < 5ns Transition < 5ns Test Conditions Min 4 4 33 75 30 ±250 5 5 256*tSCP 4*tSCP Max ns ns MHz ns ps ns ns ns ns Units Notes: 6. Operation of the ACT5230 is only guaranteed with the Phase Loop enabled. Aeroflex Circuit Technology 4 SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700 System Interface Parameters7 133MHz Parameter Data Output8 tDO mode14...13 = 00 mode14...13 = 01 (slowest) Data Setup Data Hold tDS tDH tRISE = 5ns tFALL= 5ns Symbol Test Conditions Min mode14...13 = 10 (fastest) mode14...13 = 11 TBD TBD 1.0 TBD 4.0 0 Max TBD TBD 8.0 TBD Min TBD TBD 1.0 TBD 4.0 0 Max TBD TBD 8.0 TBD ns ns ns ns ns ns 150MHz Units Notes: 7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal. 8. Capacitive load for all output timing is 50pF. Boot Time Interface Parameters 133/150MHz Parameter Mode Data Setup Mode Data Hold Symbol tDS tDH Test Conditions Min 4 0 Max SysClock cycles SysClock cycles Units Aeroflex Circuit Technology 5 SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700 ACT5230 Microprocessor – PQUAD Pinouts Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Aeroflex Circuit Technology Function Vcc NC NC Vcc Vss SysAD4 NC SysAD5 NC Vcc Vss SysAD6 NC Vcc Vss SysAD7 NC SysAD8 NC Vcc Vss SysAD9 NC Vcc Vss SysAD10 NC SysAD11 NC Vcc Vss SysAD12 NC Vcc Vss SysAD13 NC SysAD14 NC Vcc Vss SysAD15 NC Vcc Vss ModeClock JTDO JTDI JTCK JTMS Vcc Vss ag ck a (P e& Pin # 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 P ts ou in Function NC NC NC Vcc Vss ModeIn RdRdy* WrRdy* ValidIn* ValidOut* Release* VccP VssP SysClock Vcc Vss Vcc Vss Vcc Vss SysCmd0 SysCmd1 SysCmd2 SysCmd3 Vcc Vss SysCmd4 SysCmd5 Vcc Vss SysCmd6 SysCmd7 SysCmd8 SysCmdP Vcc Vss Vcc Vss Vcc Vss Int0* Int1* Int2* Int3* Int4* Int5* Vcc Vss NC NC NC NC t ct je ub s Pin # 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 e ng a ch o Function Vcc NMI* ExtRqst* Reset* ColdReset* VccOK BigEndian Vcc Vss SysAD16 NC Vcc Vss SysAD17 NC SysAD18 NC Vcc Vss SysAD19 NC Vcc Vss SysAD20 NC SysAD21 NC Vcc Vss SysAD22 NC Vcc Vss SysAD23 NC SysAD24 NC Vcc Vss SysAD25 NC Vcc Vss SysAD26 NC SysAD27 NC Vcc Vss NC NC Vss – ) ry to ac F ct ta on C Pin # 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function NC NC NC NC Vcc Vss SysAD28 NC SysAD29 NC Vcc Vss SysAD30 NC Vcc Vss SysAD31 NC SysADC2 SysADC6 Vcc Vss SysADC3 SysADC7 Vcc Vss SysADC0 SysADC4 Vcc Vss SysADC1 SysADC5 SysAD0 NC Vcc Vss SysAD1 NC Vcc Vss SysAD2 NC SysAD3 NC Vcc Vss NC NC NC NC Vcc Vss 6 SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Sample Ordering Information Part Number ACT-5230PC-133F22I ACT-5230PC-150F22C ACT-5230PC-200F22T ACT-5230PC-200F22M Screening Industrial Temperature Commercial Temperature Military Temperature Military Screening Speed (MHz) 133 150 200 200 Package 128 Lead PQUAD 128 Lead PQUAD 128 Lead PQUAD 128 Lead PQUAD Part Number Breakdown ACT– 5230 PC – 133 F22 M Aeroflex Circuit Technology Base Processor Type Cache Style PC = Primary Cache Screening C = C ommercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable Package Type & Size Maximum Pipeline Freq. 133 = 133MHz 150 = 150MHz 200 = 200MHz Surface Mount Package F22 = 1.10" SQ 128 Lead PQUAD * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: sales-act@aeroflex.com 7 SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700