ACT-SF41632N-39P5T

ACT-SF41632 High Speed 128Kx32 SRAM / 512Kx32 Flash Multichip Module CIRCUIT TECHNOLOGY FEATURES 4 – 128K x 8 SRAMs & 4 – 512K x 8 Flash Die in One MCM s Access Times of 25ns, 35ns (SRAM) and 60ns, 70ns, 90ns (Flash) s Organized as 128K x 32 of SRAM and 512K x 32 of Flash Memory with Common Data Bus s Low Power CMOS s Input and Output TTL Compatible Design s MIL-PRF-38534 Compliant MCMs Available s Decoupling Capacitors and Multiple Grounds for Low Noise s Commercial, Industrial and Military Temperature Ranges s Industry Standard Pinouts s TTL Compatible Inputs and Outputs s Packaging – Hermetic Ceramic q 66–Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# "P1,P5 with/without shoulders)" q 68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x .20"max (.18 max thickness available, contact factory for details) (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) s s www.aeroflex.com FLASH MEMORY FEATURES Sector Architecture (Each Die) q 8 Equal Sectors of 64K bytes each q Any combination of sectors can be erased with one command sequence. s +5V Programing, +5V Supply s Embedded Erase and Program Algorithms s Hardware and Software Write Protection s Page Program Operation and Internal Program Control Time. s 10,000 Erase/Program Cycles A E RO F LE X LA B S I NC . C ISO 9001 E RTIFIE D Block Diagram – PGA Type Package(P1 & P5) & CQFP(F2) FWE1 SWE1 OE A0–A18 SCE FCE FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 PIN DESCRIPTION I/O0-31 A0–18 FWE1-4 Data I/O Address Inputs Flash Write Enables SWE1-4 SRAM Write Enables 512K X 8 FLASH 128K X 8 SRAM 512K X 8 FLASH 128K X 8 SRAM 512K X 8 FLASH 128K X 8 SRAM 512K X 8 FLASH 128K X 8 SRAM FCE SCE OE NC VCC GND Flash Chip Enable SRAM Chip Enable Output Enable Not Connected Power Supply Ground I/O0-7 I/O8-15 I/O16-23 I/O24-31 eroflex Circuit Technology - Advanced Multichip Modules © SCD3851 REV A 5/21/98 Absolute Maximum Ratings Symbol TC TSTG VG TL Parameter Flash Data Retention Flash Endurance (Write/Erase Cycles) 10 Years 10,000 Case Operating Temperature Storage Temperature Maximum Signal Voltage to Ground Maximum Lead Temperature (10 seconds) Rating Range -55 to +125 -65 to +150 -0.5 to +7 300 Units °C °C V °C Normal Operating Conditions Symbol VCC VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Minimum +4.5 +2.2 -0.5 Maximum +5.5 VCC + 0.3 +0.8 Units V V V Capacitance (VIN = 0V, f = 1MHz, TA = 25°C) Symbol Parameter CAD COE CWE1-4 CCE CI / O A0 – A18 Capacitance OE Capacitance F/S Write Enable Capacitance F/S Chip Enable Capacitance I/O0 – I/O31 Capacitance Maximum 80 80 30 50 30 Units pF pF pF pF pF This parameter is guaranteed by design but not tested DC Characteristics (VCC = 5.0V, VSS = 0V, Tc = -55°C to +125°C) Parameter Input Leakage Current Output Leakage Current Sym ILI ILO Conditions VCC = Max, VIN = 0 to VCC FCE = SCE = VIH, OE = VIH, VOUT = 0 to VCC Min Max Units 10 10 500 80 0.4 2.4 260 300 0.45 0.85 x VCC 3.2 4.2 µA µA mA mA V V mA mA V V V SRAM Operating Supply Current x 32 I x32 SCE = VIL, OE = VIH, f = 5MHz, VCC = CC Max, FCE = VIH Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash Vcc Active Current for Read (1) Flash Vcc Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Low Vcc Lock Out Voltage ISB VOL VOH ICC1 ICC2 VOL VOH1 VLKO FCE = SCE = VIH, OE = VIH, f = 5MHz, VCC = Max IOL = 8 mA, VCC = Min, FCE = VIH IOH = -4.0 mA, , VCC = Min, FCE = VIH FCE = VIL, OE = VIH, SCE = VIH FCE = VIL, OE = VIH, SCE = VIH IOL = 12 mA, VCC = Min, SCE = VIH IOH = -2.5 mA, , VCC = Min, SCE = VIH Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V Aeroflex Circuit Technology 2 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 SRAM AC Characteristics (VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C) Read Cycle Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Enable to Output Valid Chip Select to Output in Low Z * Output Enable to Output in Low Z * Chip Deselect to Output in High Z * Output Disable to Output in High Z * * Parameters guaranteed by design but not tested Symbol tRC tAA tACE tOH tOE tCLZ tOLZ tCHZ tOHZ 3 0 12 12 0 15 3 0 20 20 –025 Min Max 25 25 25 0 20 –035 Min Max 35 35 35 Units ns ns ns ns ns ns ns ns ns Write Cycle Parameter Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Output Active from End of Write * Write to Output in High Z * Data Hold from Write Time Address Hold Time * Parameters guaranteed by design but not tested Symbol tWC tCW tAW tDW tWP tAS tOW tWHZ tDH tAH 0 0 –025 Min Max 25 20 20 15 20 0 0 10 0 0 –035 Min Max 35 25 25 20 25 0 0 20 Units ns ns ns ns ns ns ns ns ns ns SRAM Truth Table Mode Standby Read Output Disable Write SCE H L L L OE X L H X SWE X H H L Data I/O High Z Data Out High Z Data In Power Standby Active Active Active Aeroflex Circuit Technology 3 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 Timing Diagrams — SRAM Read Cycle Timing Diagrams Read Cycle 1 (SCE = OE = VIL, SWE = VIH) tRC A0-18 tAA tOH DI/O Previous Data Valid Data Valid SCE tAS SWE SEE NOTE Write Cycle Timing Diagrams Write Cycle (SWE Controlled, OE = VIH) tWC A0-18 tAW tCW tAH tWP tWHZ tDW Data Valid tOW tDH DI/O Read Cycle 2 (SWE = VIH) tRC A0-18 tAA SCE tACE tCLZ SEE NOTE Write Cycle (SCE Controlled, OE = VIH ) tWC A0-18 tAW tCHZ SEE NOTE tAH tCW tAS SCE OE tWP tOE tOLZ SEE NOTE tOHZ SEE NOTE SWE tDW DI/O Data Valid tDH DI/O High Z Data Valid UNDEFINED DON’T CARE Note: Guaranteed by design, but not tested. AC Test Circuit Current Source IOL AC Test Conditions Parameter Typical 0 – 3.0 5 1.5 Units V ns V To Device Under Test CL = 50 pF VZ ~ 1.5 V (Bipolar Supply) Input Pulse Level Input Rise and Fall Input and Output Timing Reference Level IOH Current Source Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. 4 Aeroflex Circuit Technology SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 Flash AC Characteristics – Read Only Operations (Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output High Z (1) Output Enable High to Output High Z(1) Output Hold from Address, CE or OE Change, Whichever is First Note 1. Guaranteed by design, but not tested Symbol –60 –70 –90 Units JEDEC Stand’d Min Max Min Max Min Max tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 60 60 60 30 20 20 0 70 70 70 35 20 20 0 90 90 90 35 20 20 ns ns ns ns ns ns ns Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled (Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C) Parameter Write Cycle Time Chip Enable Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation Sector Erase Time Read Recovery Time before Write Vcc Setup Time Chip Programming Time Chip Enable Hold Time Chip Erase Time 1. Toggle and Data Polling only. Symbol JEDEC Stand’d tAVAC tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tWC tCE tWP tAS tDS tDH tAH tWPH –60 –70 –90 Min Max Min Max Min Max 60 0 40 0 40 0 45 20 14 TYP 30 0 0 50 50 50 10 120 120 50 50 10 120 70 0 45 0 45 0 45 20 14 TYP 30 0 50 90 0 45 0 45 0 45 20 14 TYP 30 Units ns ns ns ns ns ns ns ns µs Sec µs µs Sec ns Sec tGHWL tVCE tOEH 1 tWHWH3 10 Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled (Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C) Parameter Write Cycle Time Write Enable Setup Time Chip Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Enable Pulse Width High Duration of Byte Programming Sector Erase Time Read Recovery Time Chip Programming Time Chip Erase Time Aeroflex Circuit Technology Symbol JEDEC Stand’d tAVAC tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tWC tWS tCP tAS tDS tDH tAH tCPH –60 –70 –90 Min Max Min Max Min Max 60 0 40 0 40 0 45 20 14 TYP 30 0 50 0 50 120 70 0 45 0 45 0 45 20 14 TYP 30 0 50 120 90 0 45 0 45 0 45 20 14 TYP 30 Units ns ns ns ns ns ns ns ns µs Sec ns Sec Sec tGHEL tWHWH3 5 120 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 AC Waveforms for Flash Memory Read Operations tRC Addresses Addresses Stable tACC FCE tDF OE tOE FWE tCE Outputs High Z tOH Output Valid High Z Write/Erase/Program Operation for Flash Memory, FWE Controlled Data Polling Addresses 5555H tWC FCE tGHWL OE tWP FWE tCE tDH AOH Data tDS PD D7 DOUT tOH tOE tWPH tDF tWHWH1 tAS PA tAH PA tRC 5.0V tCE Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 6 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 AC Waveforms Chip/Sector Erase Operations for Flash Memory tAH Addresses 5555H tAS 2AAAH Data Polling 5555H 5555H 2AAAH SA FCE tGHWL OE tWP FWE tCE Data tWPH tDH AAH tDS VCC 55H 80H AAH 55H 10H/30H tVCE Notes: 1. SA is the sector address for sector erase. AC Waveforms for Data Polling During Embedded Algorithm Operations for Flash Memory tCH FCE tDF tOE OE tOEH FWE tCE tOH * DQ7 DQ7 DQ7= Valid Data High Z tWHWH1 or 2 DQ0-DQ6 DQ0–DQ6=Invalid DQ0–DQ6 Valid Data tOE * DQ7=Valid Data (The device has completed the Embedded operation). Aeroflex Circuit Technology 7 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 Write/Erase/Program Operation for Flash Memory, FCE Controlled Data Polling Addresses 5555H tWC FCE tGHWL OE tCP FWE tWS tCPH tDH AOH Data tDS PD D7 DOUT tWHWH1 tAS PA tAH PA 5.0V Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 8 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 Pin Numbers & Functions 66 Pins — PGA-Type Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function I/O8 I/O9 I/O10 A14 A16 A11 A0 A18 I/O0 I/O1 I/O2 FWE2 SWE2 GND I/O11 A10 A9 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function A15 Vcc FCE SCE I/O3 I/O15 I/O14 I/O13 I/O12 OE A17 FWE1 I/O7 I/O6 I/O5 I/O4 I/O24 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function I/O25 I/O26 A7 A12 SWE1 A13 A8 I/O16 I/O17 I/O18 VCC SWE4 FWE4 I/O27 A4 A5 A6 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Function FWE3 SWE3 GND I/O19 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 I/O23 I/O22 I/O21 I/O20 "P1" — 1.385" SQ PGA Type Package Standard (with shoulders on Pins 1, 11, 56 & 66) "P5" — 1.385" SQ PGA Type Special Order Package (without shoulders) Bottom View (P1 & P5) Side View (P1) .245 MAX .025 .035 Side View (P5) .220 MAX Pin 56 1.400 SQ MAX 1.000 TYP .600 TYP Pin 1 .100 TYP .020 .016 .100 TYP 1.000 TYP .020 .016 Pin 66 Pin 11 .100 TYP .145 MIN .165 MIN All dimensions in inches Aeroflex Circuit Technology 9 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 Pin Numbers & Functions 68 Pins — Dual-Cavity CQFP Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function GND SWE3 A5 A4 A3 A2 A1 A0 NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Pin # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Vcc A11 A12 A13 A14 A15 A16 FCE Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function OE SWE2 A17 FWE2 FWE3 FWE4 A18 SCE SWE1 FI/O31 FI/O30 FI/O29 FI/O28 FI/O27 FI/O26 FI/O25 FI/O24 Pin # 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function GND FI/O23 FI/O22 FI/O21 FI/O20 FI/O19 FI/O18 FI/O17 FI/O16 VCC A10 A9 A8 A7 A6 FWE1 SWE4 Package Outline — Dual-Cavity CQFP "F2" Top View .990 SQ ±.010 .890 SQ MAX Pin 9 Pin 10 Pin 61 Pin 60 .015 ±.002 *.200 MAX .010 REF .010 ±.002 .010 R REF +3°/-3° .050 TYP Pin 26 Pin 27 .800 REF Pin 44 Pin 43 See Detail “A” *.180 MAX available, call factory for details .040 ±.005 Detail “A” .010 ±.005 All dimensions in inches Aeroflex Circuit Technology 10 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Ordering Information Model Number ACT-SF41632N–26P1X ACT-SF41632N–37P1X ACT-SF41632N–39P1X ACT-SF41632N–26F2X ACT-SF41632N–37F2X ACT-SF41632N–39F2X Note: (S) = Speed for SRAM, (F) = Speed for FLASH DESC Part Number TBD TBD TBD TBD TBD TBD Speed 25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns 25(S) / 60(F) ns 35(S) / 70(F) ns 35(S) / 90(F) ns Package 1.385"sq PGA-Type 1.385"sq PGA-Type 1.385"sq PGA-Type .88"sq CQFP .88"sq CQFP .88"sq CQFP Part Number Breakdown ACT– SF 416 32 N– 26 P1 M Aeroflex Circuit Technology Memory Type SF = SRAM Flash Combo Module Memory Depth, Locations 4 = 4M SRAM, 16 = 16M Flash Memory Width, Bits Pinout Options N = None Screening C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C Screened * Q = MIL-PRF-38534 Compliant/SMD Package Types & Sizes Surface Mount Packages F2 = 0.88"SQ 68 Leads Dual-Cavity CQFP Thru-Hole Packages P1 = 1.385"SQ PGA 66 Pins W/Shoulder P5 = 1.385"SQ PGA 66 Pins WO/Shoulder Memory Speed (Code) 26 = 25ns SRAM & 60ns FLASH 37 = 35ns SRAM & 70ns FLASH 39 = 35ns SRAM & 90ns FLASH * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 11 SCD3851 REV A 5/21/98 Plainview NY (516) 694-6700