CT1508-2

CT1508-2 MIL-STD-1397 Type E 10MHz Serial Manchester 4-Bit SIS / SOS Decoder Features • • • • • • • • • • • • Unique Manchester decoder requires no clock CIRCUIT TECHNOLOGY 4 Bit SIS / SOS output www.aeroflex.com Operates with ±5 volt supply Removes sync, word identifier and parity bits EX L A FL Does both data and SIS / SOS decoding Detects parity on all received data Flags received messages with word lengths greater than 4 bits Accepts self-test inputs for BITE applications C Generates one clock edge per received bit for bit counting applications E RTIFIED May be used as a serial decoder for indefinite word lengths Interfaces directly to the CT1496-2 (Manchester Encoder) and CT1469-2 (Transceiver) MIL-PRF-38534 compliant devices available B A E RO S ISO 9001 I NC . General Description CT1508-2 is a hybrid microcircuit which incorporates a serial decoder in a single package. The encoder accepts a "N" Bit (Typically 4, 34 or 35) serial Manchester encoded TTL NRZ signals and outputs a 4 bit SIS / SOS TTL output along with "N" recovered data Bits/Clocks. Aeroflex Circuit Technology is a 80,000 square foot MIL-PRF-38534 certified facility in Plainview, N.Y. DATAst DATA DATA DATAst Data Reconstruct Manchester Decoder / Clock Regenerator Master Reset DATAr CLOCKr 4 Bit SIS / SOS Register Counter SIS / SOS False +5V Gnd -5V VCC Transmission Envelope VEE S yn c Bi t 4 D at a C/I SIS / SOS Output TP1 TP1 TP1 TP1 Test Points Block Diagram eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT1508 REV A 3/22/00 Aeroflex Circuit Technology 1ST Data Bit RX Data T1 RX Data T5 Transmission Envelope T6 PW2 2ND Data Bit 3RD Data Bit PW1 T2 4TH Data Bit 5TH Data Bit VIH VIL VIH VIL T3 VOH VOL 2 DataR T7 ClockR SIS / SOS False T11 PW3 Master Reset SCDCT1508 REV A 3/22/00 Plainview NY (516) 694-6700 VOH VOL VOH VOL 3V 0V 3V 0V T4 T9 T10 Figure 1 – Decoder Timing Waveforms Absolute Maximum Ratings Parameter Supply Voltage VCC VEE Input Voltage Applied Output Voltage Power Dissipation Storage Temperature Range Operating Case Temperature Range Rating +7.0 -7.0 +0.5 to +5.5 -0.5 to +7.0 2.17 -60 to +150 -55 to +100 Units V V V V W °C °C DC Electrical Characteristics (VDD = 5V ±10%, TC = -55 °C to +100°C, unless otherwise specified) SYMBOL PARAMETER LIMIT SIS / SOS False & SIS / SOS Outputs VOH VOL Logic High Output Voltage Logic Low Output Voltage 2.4V min @ IOH = -50µA, VCC = +4.5V 0.4V max @ IOL = 2mA, VCC = +4.5V Clockr & Datar VOH VOL Logic High Output Voltage Logic Low Output Voltage 2.4V min @ IOH = -150mA, VCC = +4.5 0.4V max @ IOL = 6mA, VCC = +4.5V Transmission Envelope VOH VOL Logic High Output Voltage Logic Low Output Voltage 2.4V min @ IOH = -200mA, VCC = +4.5V 0.4V max @ IOL = 8mA, VCC = +4.5V RX DATA, RX DATA, DATAst, DATAst & Master Reset IIH IIL Logic High Input Current Logic Low Input Current 50µA max @ VIH = 2.7V, VCC = +5.5V 2mA max @ VIL = 0.4V, VCC = +5.5V DC Supply Currents ICC IEE VCC = +5.5V (pin 1) VEE = -5.5V (pin 9) 3 360mA max 35mA max SCDCT1508 REV A 3/22/00 Plainview NY (516) 694-6700 Aeroflex Circuit Technology Decoder Timing Characteristics (VCC = 5V ±10%, T C = -55 °C to +100°C, See Figure 1, unless otherwise specified) Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 PW1 PW2 PW3 Parameter / Condition Bit transition 0 - 0, 1 - 1 Bit transition 0 - 1, 1 - 0 Transmission envelope off delay ClockR low time Envelope delay time Data decode delay Clock low transition delay Word Parity Delay ClockR low time SIS / SOS false delay time minimum reset disable time Half Bit input pulse Full Bit input pulse Master reset pulse width Min 35 90 100 35 35 20 20 90 60 Typ 60 100 50 25 35 50 120 50 40 50 100 - Max 65 130 250 65 40 45 65 80 65 130 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Aeroflex Circuit Technology 4 SCDCT1508 REV A 3/22/00 Plainview NY (516) 694-6700 Functional Description and Pinout Pin # 1 9 2 4 3 6 14 Pin Name VCC VEE RX DATA RX DATA DATAST DATAST Transmission Envelope +5V ± 10% -5V ± 10% Connect to DATA output of RX Connect to DATA output of RX Connect to DATAST output of encoder Connect to DATAST output of encoder High within approximately 40nSec of reception of first half bit; goes low approximately 100nSec after reception of last half bit (normally low in inactive state). Reset to low state on clear. Goes high reception of transmission with word length greater than 4 bits. Last 4 bits received reside in this register until cleared. If valid SIS / SOS then register contains SIS / SOS message. Function Load or Drive 1 S Load 1 S Load 1 S Load 1 S Load 4 S Drives 19 SIS / SOS False 1 S Drive 20 21 22 24 17 SIS / SOS Output (Pin 24 - LSB) (Pin 20 - MSB) 1 S Drive DataR Reconstructed Data. Data state to be considered in conjunction with positive edges of ClockR. Reconstructed Clock (approximately 50% duty cycle) to be used in conjunction with Reconstructed Data and maybe used for bit counting applications. Clears all data registers, bit counter, WORD PARITY on low. Must be used after each word to initialize bit counter and parity detector. Do not connect. Do not connect. Do not connect. Do not connect. 8 ClockR 7 Master Reset 11 15 16 13 TP1 TP2 TP3 TP4 Aeroflex Circuit Technology 5 SCDCT1508 REV A 3/22/00 Plainview NY (516) 694-6700 Functional Description and Pinout (con’t) Pin # Pin Name Function Load or Drive General Notes: 1 S Load: Requires IIL = 2 mA Max. IIH = 50 µA Max. CIN