CT2565-001-2

CT2565 Bus Controller, Remote Terminal and BUS Monitor FOR MIL-STD-1553B Features I I I I I I I I I I I Second Source Compatible to the BUS-65600 RTU implements all dual redundant mode codes Selective mode code illegalization available 16 bit microprocessor compatibility BC checks status word for correct address and set flags RTU illegal mode codes externally selectable 16 bit µProcessor compatibility DMA handshaking for subsystem message transfers MIL-PRF-38534 compliant circuits available DESC SMD #5962–88585 Pending Packaging – Hermetic Metal • 78 Pin, 2.1" x 1.87" x .25" Plug-In type package • 82 Lead, 2.2" x 1.61" x .18" Flat package CIRCUIT TECHNOLOGY www.aeroflex.com A E RO F LE X LA C ISO 9001 E RTIFIED B S I NC . General Description The CT2565 is a dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), and Bus Monitor, (BM) Bus packaged in a 1.9" x 2.1" hermetic hybrid. It provides all the functions required to interface a MIL-STD-1553 dual redundant serial data bus transceiver, (Aeroflex's ACT4487 for example) and a subsystem parallel three-state data bus. Utilizing a custom monolithic IC, the CT2565 provides selectable operation as a Bus Controller, Remote Terminal or a Bus Monitor (BM). The CT2565 is compatible with most µprocessors. It provides a 16 bit three-state parallel data bus and uses direct memory access (DMA type) handshaking for subsystem transfers. All message transfer timing as well as DMA and control lines are provided internally. Subsystem overhead associated with message transfers is therefore minimized. Interface control lines are common for both BC and RT operation. The CT2565 features the capability for implementing all dual redundant MIL-STD-1553 mode codes. In addition, any mode code may (optional) be illegalized through the use of an external (200ns access time) PROM. Complete error detection capability is provided, for both BC and RTU operation. Error detection includes: response time-out, inter message gaps, sync, parity, Manchester, word count and bit count. The CT2565 complies with all the requirements of MIL-STD-1553. The hybrid is screened in accordance with the requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to +125°C. eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2565 REV B 8/10/99 STATUS INPUTS Aeroflex Circuit Technology RTADDR DBACCEPT SSFLAG SER REQ SSERR SSBUSY MODE CODE CONTROL CH A CONTROL REMOTE TERMINAL LOGIC TXINH A TXDATA A TXDATA A RXDATA A RXDATA A CH A ENCODE/ DECODE WC 0-WC4 T/R LMC ILLCMD I/O0 - I/O16 DATA BUFFERS DATA BUS BUFENA R/W EN 2 CH B CONTROL CONTROL BUS BUS CONTROLLER LOGIC I/O BUS I/O LOGIC BUFFERS PARITY CHECKER TXINH TXDATA TXDATA RXDATA RXDATA B B B B B CH B ENCODE/ DECODE RTADDR RTADR0 RTADR1 RTADR2 RTADR3 RTADR4 RTADRP RTADDR BUSREQ BUSGRNT BUSACK TIMEOUT SOM EOM INCMD CS OE WR TESTIN TESTOUT RT/BC MT BCSTART CHA/CHB LOOPER R MSGERR STATERR LWORD HSFAIL STATEN BITEN NBG RNT ADRINC NO DT BSCTRCV 12MHz SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 Figure 1 – CT2565 Block Diagram Values at nominal Power Supply Voltages unless otherwise specified PARAMETER Logic VIH VIL VOH VOL IIH IIL IOL * IOH * CIN (f = 1MHz) COUT (f = 1MHz) Power Supply +5VDC Tolerances Supply Current Internal Decoupling Temperature Range Operating (Case) Storage Physical Characteristics Size 78 pin DDIP 82 pin flatpack Weight VALUE 2.0 min 0.8 max 3.7 min 0.4 max ±100 max -0.4 max ±1.2 max ±0.4 max 20 max 20 max UNITS V V V V µA mA mA mA pF pF ±10 max 50 typ (70 max) 1.5 typ −55 to +125 −65 to +150 % mA µF °C °C 1.9 x 2.10 x 0.25 (48.30 x 53.34 x 6.35) 1.6 x 2.19 x 0.15 (40.64 x 55.63 x 3.81) 1.7 (48) in (mm) in (mm) oz (g) * I OL and IOH parameters are indicated for all logic outputs except Data Bus (DB0 – DB15) which are ±5mA for both parameters. Table 1 – CT2565 Specifications GENERAL The CT2565 uses a custom CMOS ASIC for protocol logic and I/O buffering to provide low power dissipation in its small package. The CT2565 performs a continuous on-line Built-In-Test (BIT); in this test the last transmitted word of each message transfer is wrapped around through the active receiver channel and verified against the captured encoded word. A user-defined loop test under subsystem control can also be implemented. Numerous error flags are provided to the subsystem including message error, status error, response time out and loop test error. An external 12 MHz, TTL clock connected to Pin 39 is required. Where appropriate, references to signal names and their associated pin numbers for the 78 pin Aeroflex Circuit Technology DDIP package are made throughout this document. For flatpack model pin numbers, refer to Table 10. BC/RTU/MT Initialization The CT2565 provides BC, RTU, and MT operating modes. The operating mode if dynamically selectable through two static control inputs as listed in Table 2. It is recommended that a master RESET signal be issued (80ns min) prior to mode selection to clear the internal registers. MIL-STD-1553 Word Types Figure 2 illustrates the three MIL-STD-1553 word types: Command, Data, and Status. 3 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 BIT TIMES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 COMMAND WD SYNC 5 REMOTE TERMINAL ADDRESS T/R 5 SUBADDRESS MODE 16 5 DATA WORD COUNT/MODE CODE 1 P DATA WORD SYNC STATUS WORD SYNC 5 REMOTE TERMINAL ADDRESS 1 1 1 P 3 RESERVED PARITY TERMINAL FLAG DYNAMIC BUS CONTROL ACCEPTANCE SUBSYSTEM FLAG BUSY BROADCAST COMMAND RCVD 1 1 1 1 1 1 DATA 1 MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST Note: T/R – Transmit/Receive, P – Parity Figure 2 – MIL-STD-1553 Word Types RT/BC (PIN 1) 0 1 0 MT (PIN 2) 1 1 0 MODE BC RT MT triggers an address increment (ADRINC pin) low output pulse used to increment the subsystem memory address for successive transfers. BC OPERATION In the BC mode, the CT2565 initiates all MIL-STD-1553 data and control message transfers. Figure 3 details specific message transfer flow and Table 3 lists subsystem memory allocation. The subsystem, or host processor, must provide a CT2565 protocol Control Word (See Figure 4) and MIL-STD-1553 command and data words. The CT2565 will transfer the RTU status response and provide message transfer validation during an active transfer. All parallel word transfers occur in the form of a DMA (request-grant-acknowledge) handshake with memory read or operation as shown in Figures 5 and 6. Command Transfer In the BC mode pulse BCSTART (pin 41) low. Following the pulse, the CT2565 will initiate a DMA handshake and memory read for; the control, word, command word(s) and up to 32 data words. No handshake timeout is enforced in the BC mode (CT2565) remains idle during BUSREQ to BUSGRNT), however 1553 protocol must be maintained. Note that commands are named from the BC's point-of-view (for example, a TRANSMIT CMD indicates the addressed RTU must transmit data). Table 2 – Operating Modes DMA - Type Handshake All BC and RT word transfers are preceded by a request-grant-acknowledge format DMA handshake procedure. Timing information is provided in BC, RTU and MT sections. In MT mode, the 1553 transmission is transferred along with an identification Word using a single DMA handshake containing two memory-write operations. The DMA format requires that the subsystem provide a bus grant (BUSGRNT pin 45) low within a timeout period. Note that BUSGRNT should be set to logic "1" before another bus request (BUSREQ) is issued. Memory Read/Write With the single exception of an RT command word transfer, all subsystem transfers take the form of a static memory read or write. A low pulse on both the chip select (CS) and output enable (OE) or a low pulse on CS and write enable (WE) (pins 17, 18 and 44 respectively) indicates data is valid on the parallel data bus for the duration of the pulse. The rising edge of CS Aeroflex Circuit Technology 4 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 RECEIVE Control Word Receive Command Data 1 • • Last Data Looped Data Word RTU Status TRANSMIT Control Word Transmit Command Looped Command Word RTU Status Data 1 • • Last Data Table 3 – BC Memory Allocation Loop Test Upon receipt from the subsystem, the last word to be transmitted within a given message transfer (command or Data word) is stored in a CT2565 internal register. As this word is transmitted to the 1553 bus, it is looped back through the active receiver channel for auto-BC, Short Loop verification. A LOOPERR (.5us typ) low pulse indicates a mismatch between the stored and looped word. The CT2565 also initiates a handshake with a memory write to the subsystem for user-defined, "long loop" (subsystem, CT2565, subsystem) verification. Note that both short and long loop testing are initiated for all transfers (on the last word transmitted to 1553). Subsystems response to use Long Loop Test is to compare the loaded word to what was looped back into memory. 15 NOT USED BUS CHANNEL A/B NOT USED MASK BROADCAST BIT NOT USED MODE CODE BROADCAST RT-RT 8 0 BIT BUS CHANNEL A/B DEFINITION When logic "1" transmits over 1553 Bus A. When logic "0" transmits over 1553 Bus B (See note) Always set to "0" Command Word count field signifies mode code type Multiple RTU’s addressed, no status word expected When set, RTU(b) transmits, RTU(a) receives. Both RTU Status Words are validated and sent to subsystem. MASK BROADCAST BIT MODE CODE BROADCAST RT-RT Note: Messages-transmission (routing) status pin (pin 16, Chan A/B) becomes active after loading the control word and command word respectively. The signal is cleared by RESET or EOM low. Figure 4 – BC Control Word Aeroflex Circuit Technology 5 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 CONTROL & COMMAND WORDS START BC OPERATION DATA WORDS A NO RX CMD YES HANDSHAKE (DMA) SHORT LOOP HANDSHAKE (DMA) MEMORY READ CONTROL WORD FROM SSIU NO INCREMENT MEM ADDR OUTPUT LONG LOOP MEMORY READ DATA WORD FROM SSIU STATUS FROM RT YES HANDSHAKE (DMA) INCREMENT MEM ADDR DATA TO 1553 HANDSHAKE (DMA) MEMORY WRITE STATUS WORD TO SSIU MORE DATA NO SHORT LOOP YES MEMORY READ COMMAND WORD FROM SSIU STATERR INCREMENT MEM ADDR LONG LOOP NO CMD WORD TO 1553 TIMEOUT MSGERR STATUS FROM RT YES HANDSHAKE (DMA) STATUS FROM RT YES STATERR NO A TIMEOUT MSGERR MEMORY WRITE DATA WORD TO SSIU MEMORY WRITE STATUS WORD TO SSIU MORE DATA NO YES END OF MESSAGE PULSE Notes: (1) Steps marked with " _ _ _" indicates operation is transparent to user. (2) Steps marked with " ___" indicates user interaction required. STOP Figure 3 – BC Message Transfer Flow Aeroflex Circuit Technology 6 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 TRANSFER/CONDITION CONTROL/COMMAND WORD 1 Handshake Failure LOOPED WORD Short Loop Failure Long Loop Failure RT-RT DESCRIPTION Memory read by BC subsystem. No response to Bus Request within timeout period. Looped back through receiver. Received Word ≠ last xmitted word. DMA/Write looped word to subsystem. Status-RT1, data, status-RT2 response to follow receive, transmit, commands. ERROR SIGNAL BC waits for Grant (no 1553 timing error) LOOPERR User Defined (See definitions in STATUS/DATA WORD below) TIMEOUT EOM STATERR STATERR Broadcast Mask not set (See BC Control Word) STATERR BC waits for Grant. MSGERR Status Word response: STATERR MSGERR and EOM MSGERR and EOM DMA/memory write (for each) MSGERR PIN - 46 - STATUS WORD No Status Received within 15.5µS RT Address Mismatch Error Flag(s) Set Broadcast Received bit Set NODT timeout Command RTU Address ≠ Status Word RTU Address Status Word Response from RT: Error Condition Response to Transmit Status Word mode command may allow this, all others ERROR. 4 57 68 68 68 DATA WORD Handshake Failure Transmit Command Receive Command Data Received from RTU Less than word count Greater than word count Data after Status Set (all extra words) FORMAT ERROR No subsystem response to Bus Request. Data lost: Word Count fails. 1553 transmission gap. 30 68 4 30 Transmit Command (RTU response) More data received than requested. Transmit Command: data words received after status to subsystem. 30 - Notes: (1) LOOPERR is a .5µS pulse which occurs near DMA handshake for loop back word. (2) TIMEOUT is a 40/160nS pulse which occurs 19.5µS ±0.5µS after the mid-bit parity of the last word onto the bus. (3) STATERR is a 120/166nS pulse which occurs during the status word DMA handshake. (4) MSGRR is a 40/160nS pulse which occurs approximately 100nS before INCMD goes high. It is triggered by NODT going inactive (i.e., low word count). Table 4 – BC Error Handling RTU Response The addressed RTU(s) must respond (to non-broadcast commands) within a timeout period as shown in Figures 7, 8, and 9. Figures 10 and 11 illustrate the BC Mode Code Timing. Status and data words received from the 1553 port are transferred to the subsystem via a handshake and memory write operation for each (See Message Length Checking). BC Status/Error Handling Message transfer errors are indicated using the TIMEOUT, MSGERR, LOOPERR and STATERR BC status outputs (pins 4, 30, 46 and 68 respectively). Additional error detection methods include user evaluation of status, data and (long) loop words and/or use of the 1553B dual redundant mode codes. Note that certain error conditions not reflected in the current Status Word (SW) can occur; Broadcast CMD RT-status and post RT status response may be Aeroflex Circuit Technology accessed via the Transmit Status Word mode command. Transmit Bit Word. Additional status informa tion is generated by an RTU (CT2565 for each transfer in the form of a BIT word). This word may be accessed by the BC using the TRANSMIT B-I-T WORD mode command. See RTU Error Handling and Mode Code sections). Message Length Checking. The BC stores the command word, word-count field in an internal register. By decrementing this register following each data word transfer (See BC Memory Read/Write Timing), the BC can detect an incorrect message length. For a description of the possible BC error, indicators occurring during each stage of message transfer read from left to right in Table 4. For a description of the possible causes of errors within a transfer, read from right to left. 7 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 t1 BUSREQ (19) t2 BUSGRNT (45) t4 BUSACK (59) t3 HSFAIL (5) TRI-STATE SYMBOL t1 t2 t3 t4 DESCRIPTION BUSREQ pulse width BUSREQ to BUSGRNT delay BUSGRNT pulse width BUSGRNT to BUSACK delay MIN 867 0 166 50 MAX 1667 800 200 UNITS ns ns ns ns Figure 5 – BC Handshake Timing BUSACK (59) t1 OE (18) t7 WR (44) t2 CS (17) t4 t5 ADRINC (49) t3 D0 - D15 DATA VALID t9 t8 t9 t5 t10 DATA VALID t6 t6 MEMORY READ MEMORY WRITE CYCLE Read SYMBOL t1 t2 t3 t4 t5 t6 DESCRIPTION BUSACK to OE delay OE to CS delay Data setup time CS (OE) pulse width CS to ADRINC delay ADRINC pulse width BUSACK to WR delay WR to CS delay CS and WR pulse width Data valid setup MIN 650 80 150 100 MAX 25 25 250 680 25 166 378 25 175 - UNITS ns ns ns ns ns ns ns ns ns ns Write t7 t8 t9 t10 Figure 6 – BC Read/Write Timing Aeroflex Circuit Technology 8 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 1553 BUS 50 200 ns CMD RTA P DATA P STAT 10.75±0.75µs RTA P BC START (41) INCMD (9) 330 700 ns 2µs 166µs HANDSHAKE (REQ, GRNT, ACK) 4µs 43.5±0.5µs 24±0.5µs MEM-READ (CS, OE, ADRINC ) MEM-WRITE (CS, WR, ADRINC ) D0 - D15 NODT (71) LWORD (29) STATERR (68) EOM (57) OUTPUTS CLT CMD DATA 7.5±0.5µs 5.5±0.5µs 5.5±0.5µs 5.5µs TYP 44±0.5µs LOOP STAT 7.5±0.5µs 120 166 ns 200 500 ns 166 332 ns 200ns CHA/CHB LATCHED Notes for Figures 7-9 T/R and HSFAIL are static at logic "1" in BC mode. All timing is typical unless otherwise noted. Figure 7 – BC Receive One Word Command Timing 9 Aeroflex Circuit Technology SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 1553 BUS 50 200 ns CMD RTA P 10.75±0.75µs STAT RTA P DATA P BC START (41) 330 700 ns INCMD (9) 166µs HANDSHAKE (REQ, GRNT, ACK) MEM-READ (CS, OE, ADRINC) MEM-WRITE (CS, WR, ADRINC) D0 - D15 NODT (71) LWORD (29) CLT CMD (a) 5.5±0.5µs 30±0.5µs 20±0.5µs 20±0.5µs LOOP 7.5±0.5µs (B) (a) STAT DATA (B) 150ns (NOM) 5±0.5µs STATERR (68) EOM (57) OUTPUTS 120 166 ns 200ns CHA/CHB LATCHED MESS ERR. EX: LOW WD COUNT 200 500 ns 100ns 40 160 ns Figure 8 – BC Transmit One Word Command Timing 1553 BUS CMD RTA RX P RTB TX P STAT RTB P DATA P STAT RTA P BC START (41) 330 700 ns INCMD (9) 2µs HANDSHAKE (REQ, GRNT, ACK) MEM-READ (CS, OE, ADRINC) MEM-WRITE (CS, WR, ADRINC) D0 - D15 NODT (71) LWORD (29) CTL CMD CMD LOOP 7.5±0.5µs 5.5±0.5µs 5±0.5µs STAT DATA 7.5±0.5µs 5.5±0.5µs 150ns (NOM) 5.5±0.5µs STAT 7.5±0.5µs STATERR (68) EOM (57) 200 500 ns 120 166 ns Figure 9 – BC RT - RT Transfer Timing 10 Aeroflex Circuit Technology SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 1553 BUS INCMD (9) BUSREQ (19) ADRINC (49) D0 - D15 LWORD (29) EOM (57) CTL CMD CMD RTA P STAT RTA P DATA LCMD P 70/80µs 900ns 80/166ns LOOP STAT 5.0±0.5µs LCMD 400/500ns Figure 10 – BC Mode Code Transmit Last Command (10010) Timing 1553 BUS INCMD (9) BUSREQ (19) ADRINC (49) D0 - D15 LWORD (29) EOM (57) CTL CMD CMD RTA P STAT RTA P 50/80µsec 900ns 80/166ns LOOP 40/60µsec STAT 400/500ns Notes: All timing is typical unless otherwise noted. Figure 11 – BC Mode Code Transmit Status Word (00010) Timing RTU Operation Each RTU is assigned a unique address on the 1553 bus. It processes commands issued by the BC to its address or through Broadcast commands. Upon receipt of a valid command in the RTU mode, the CT2565 will attempt to (1) transfer 1553 data received to the subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status information to 1553, or (4) set status conditions. All data block transfers are accompanied by a 1553 Status Word. Figure 12 details a RTU single message transfer. RTU Address RTU Address pins 33-34 and 72-74 and Address Parity pin (odd parity) should be programmed to a unique RTU (1553) address. These inputs have internal pull-ups and will default a high state if left unconnected. The CT2565 will not respond if odd parity is compromised (See Error Handling). RTU Initialization Initialize the CT2565 as an RTU per Table 2. Upon receipt of valid command word from the serial bus (RTU addressed or broadcast CMD), the CT2565 will pulse NBGRNT (New Bus Grant) pin 42 low. 11 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 Aeroflex Circuit Technology COMMAND WORD CMD WORD RECEIVED FROM 1553 NO WORD VALIDATION YES NO RT ADDR YES SSU BUSY NO STATUS TO 1553 DATA WORD(S) A RX CMD YES DATA FROM 1553 RT-RT TXFER YES STOP RT-RT WORD VALIDATION STOP STATUS TO 1553 WORD COUNT LATCHED T/R BIT LATCHED STATEN PULSED MODE CODE PULSE (MODE CODE ONLY) MORE DATA? HANDSHAKE (DMA) HS FAIL NO MEMORY WRITE DATA WORD TO SSIU YES CMD ILLEGALIZED ? NO HS FAIL YES HANDSHAKE (DMA) STATUS TO 1553 INCREMENT MEM ADDR OUTPUT MEMORY READ STATEN PULSED STOP STOP HANDSHAKE (DMA) DATA TO 1553 HS FAIL STATEN PULSED DATA WORD FROM SSIU MORE DATA? INCREMENT MEM ADDR OUTPUT NO STATUS TO 1553 YES SOM PULSED SHORT LOOP SHORT LOOP NO DATA EXPECTED ? YES A STOP END OF MESSAGE PULSED STOP Notes: (1) Steps marked with " _ _ _" indicates operation is transparent to user. (2) Steps marked with " ___" indicates user interaction required. Figure 12 – RTU Single Message Transfer Flow Diagram Aeroflex Circuit Technology 12 SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700 Mode Code Illegalization (Optional) The word count and TX/RX pins will be latched 800ns (typ) after the falling edge of NBGRNT (See Figure 13, RTU Command Word Handling). Table 5 lists the CT2565 pins associated with mode code illegalization. If the current command is a mode code, LMC (pin 55) will go high. Mode codes can be illegalized, using an external PROM (