M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
Features
Applications
• Three 2A common anode LED/laser drivers
• DLP/LCD/LCoS Projector Systems
• Integrated 12.5 Msps 10-bit current DACs with 6-bit programmable full scale
• Backlight illumination
• Real-time continuous and integrating optical power control
• DC-DC control circuitry
• Safety circuitry
• High speed 4 wire interface or I2C
The M08888 is a high efficiency integrated triple channel 2A LED/laser driver for LCD/LCoS/DLP projection
displays. It features automatic optical power control for consistent white balance across temperature variation and
light source aging. The M08888 allows for the control of an external DC-DC converter to generate optimal light
sources supply and improve overall system efficiency. An internal junction temperature monitor is also available.
The part can be programmed via I2C or high speed 4-wire SPI interface.
M08888 Block Diagram
Internal Temp
Sensor
M08888
PD
13bit
Target DAC
4 wire serial
and
dual I 2C
APC_IN0
Analog MUX
APC_IN1
SO/ADDR1
__
CS/ADDR0
SI/SDA_S
SCK/SCL_S
Serial Interface Controller
Current
Comparator
SerSel
CPC
VREF
APC
IPC
Current
scaling
APC_IN2
Register
table
C
I0_ON
I1_ON
I2_ON
Timers
6bit
Scale DAC
6bit
Scale DAC
________
LP_MODE
______
ALARM
CLK_IN
10bit DAC
_____ ________
CLK_IN/ALARM/LP_MODE
POR
10bit DAC
12.4kΩ
6bit
Scale DAC
References
10bit DAC
Vref
Internal
oscillator
Headroom
control
REGREF
2A Driver
DC-DC
Converter
Control
2A Driver
2A Driver
LED
Alarm
VLDD monitor
IOUT0
IOUT1
R/G/B
IOUT2
R/G/B
R/G/B
1
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
Ordering Information
Part Number
Package
Operating Temperature
M08888G-11 *
28 pin, 4.5 mm x 4.5 mm QFN
-40 °C to +85 °C
M08888-11EVM
Evaluation board with M08888-11
-40 °C to +85 °C
* The letter “G” designator in the part number indicates that the device is RoHS-compliant.
Revision History
Revision
Level
Date
Description
V4
Release
July 2015
Updated register references.
E (V3)
Release
September 2011
Updated Ordering Information
D (V2)
Release
August 2011
C (V1)
Release
June 2011
Update Product Specifications, Functional Descriptions and Register Descriptions
B (V1P)
Preliminary
October 2010
Update Product Specifications, Functional Description and Register Descriptions.
Add operating specifications at Tc=120°C in Tables 1-5, 1-6 and 1-8. Change pin24 from DIS to GND.
Swapped pinout of ADDR0 (pin 19) and ADDR1 (pin 18).
A (V1A)
Advance
June 2010
Initial
Conventions
Throughout this document, pins will be identified with italics (example IOUT1) while x or X means 0,1,2 to indicate
the different channels.
2
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
1.0 Product Specification
1.1
Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged.
Reliable operation at these extremes for any length of time is not implied.
Table 1-1.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
DVDD, ALVDD
1.8 V Digital and Analog Voltage at pins DVDD and ALVDD
1.98
V
DHVDD, AHVDD
3.3 V Digital and Analog Voltage at pins DVDD and ALVDD
3.63
V
IOUT0, IOUT1, IOUT2
Output pins for driving LED/Laser - maximum voltage
5.5
V
TJCTN
Junction Temperature
-40 to +125
°C
TSTG
Storage Temperature
-65 to +150
°C
SERSEL
Serial data format select input
-0.4 to 3.63
V
APC_IN0, APC_IN1, APC_IN2
RGB Photodiode Feedback Input Voltage
-0.4 to ALVDD + 0.4
V
IAPC_IN0, IAPC_IN1, IAPC_IN2
RGB Photodiode Feedback Input Current
-0.5 to 4
mA
I_VREF
Current into Reference Voltage Pin
-0.12 to +0.12
mA
I0_ON, I1_ON, I2_ON
Enable LED/Laser output
-0.4 to 3.63
V
CLK_IN, CS, SI, SCLK, SO
SPI inputs and output
-0.4 to 3.63
V
SCLK_S, SDA_S
I2C interface
-0.4 to 3.63
V
REGREF
External DC-DC converter control signal
-0.4 to DVDD +0.4
V
I_REGREF
Current into or out of REGREF
-0.12 to +0.12
mA
3
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.2
Rev V4
DC Characteristics
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD=1.8 V, ALVDD=1.8 V,
DHVDD =3.3 V, AHVDD =3.3 V unless otherwise noted.
Table 1-2.
Symbol
DC Characteristics
PARAMETER
CONDITIONS
Min
Typ
Max
Units
DVDD
1.8 V supply for digital circuitry
1.71
1.8
1.89
V
ALVDD
1.8 V supply for analog circuitry
1.71
1.8
1.89
V
DHVDD
3.3 V supply for digital circuitry
3.13
3.3
3.47
V
AHVDD
3.3 V supply for analog circuitry
3.13
3.3
3.47
V
ILVDD
1.8 V Supply Current
Open Loop
—
18.5
21.5
mA
(DVDD and ALVDD)1, 2
Closed Loop (IPC)
—
8.5
11
Closed Loop (CPC)
—
22
30
Open Loop
—
7.5
13
Closed Loop (IPC) additional to open loop current
—
—
0.05
Closed Loop (CPC)
—
2.5
3.2
1.8 V SET Threshold
For positive going supply
—
1.5
—
V
1.8 V RESET Threshold
For negative going supply
3.3 V SET Threshold
For positive going supply
—
V
3.3 V RESET Threshold
For negative going supply
Case Temp.
Measured on top of M08888 case
85
°C
3.3 V (DHVDD and AHVDD)
IHVDD
Standby Current - 3.3 V
LVPOR
HVPOR
Tc
1
mA
1.4
—
2.72
2.62
-40
—
NOTES:
1.
Excludes serial interface (SPI/I2C) current and LED current
2.
ILVDD will be increase by 0.5% of the Ix_OUT current when Ix_OUT is active. For the specified values inputs are toggling at 1 kHz at 50% of maximum
Ix_OUT current.
4
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.3
Rev V4
APC Input Characteristics (register 4Ah[4]=1b)
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-3.
APC Input Characteristics (photodiode cathode connected to pin APC_INX and photodiode
anode connected to ground)
Parameter
Conditions
Minimum
Typical
Maximum
Units
Full scale input
APC_IN0,1,2
3.1
3.25
3.4
mA
PD capacitance1
APC_IN0,1,2
—
—
80
pF
Input bias
APC_IN0,1,2
—
1.8
—
V
—
—
1.89
V
Maximum input voltage
NOTES:
1.
Care should be taken in routing of each PD input so that total capacitance on the pin including routing does not exceed 80 pF
1.4
APC Input Characteristics (register 4Ah[4]=0b)
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-4.
APC Input Characteristics (Current Sink Input)
Parameter
Minimum
Typical
Maximum
Units
APC_IN0,1,22
3.1
3.25
3.4
mA
PD capacitance
APC_IN0,1,2
2
—
—
300
pF
Min Input bias
APC_IN0,1,22
—
0.6
—
—
Full scale input
1
Conditions
Maximum input voltage
V
1.89
NOTES:
1.
Care should be taken in routing of each PD input so that total capacitance on the pin including routing does not exceed 300 pF
2.
Only a single channel can be used (broadband monitor photodetector). If multiple channel are used accuracy is not guaranteed.
5
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V
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.5
Rev V4
CPC Target DAC
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-5.
CPC Target DAC
Parameter
Minimum
Typical
Maximum
Units
Resolution
—
13
—
bits
Conversion rate
—
30
—
Msps
—
3.25
3.4
mA
Step size
—
350
515
nA
CPC Control Loop Accuracy1
-6
—
6
%
Full
scale
photodetector current
Conditions
monitor
NOTES:
1.
At Tc= 120 °C control loop accuracy is +/-7%
1.6
Integrating Power Control
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-6.
Integrating Power Control
Parameter
Conditions
Resolution
Minimum
Typical
Maximum
Units
—
10
—
bits
+35
%
+11
%
Count variation
Part to part
-35
Stability2
For targets > 200 µA and register 0x0B=50h
-11
—
NOTES:
1.
This will correspond to a total power (LED/MPD current?) variation: monotonicity will still be guaranteed by the architecture
2.
Variation of integration target over supply and temperature. At Tc= 120 °C accuracy is +/-14%
6
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.7
Rev V4
LED Drivers
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-7.
LED Drivers
Parameter
Headroom required1
Conditions
At 2A full scale
Maximum allowable voltage
headroom2
Rise/fall time3
20-80% Into 1 Ω electrical output, no snubber network
Minimum
Typical
Maximum
Units
—
—
0.3
V
—
—
5.5
V
—
—
200
ns
NOTES:
1.
Required headroom scales with output current, maximum output current requires maximum headroom (see Section 2.3).
2.
To prevent damage at output pins do not exceed this voltage. Also verify power sequencing and power dissipation.
3.
Guaranteed by design
Table 1-8.
Output Current DACs
Parameter
Conditions
Minimum
Typical
Maximum
Units
Resolution
—
10
—
bits
Conversion rate
—
12.5
—
Msps
Full scale IOUTX
Referred to the current output
—
2
—
A
IOUTX absolute accuracy
Referred to the current output1
-8
—
8
%
Minimum
Typical
Maximum
Units
—
6
—
bits
NOTES:
1.
For driver headroom > specified in Table 1-7. Measured at 1000 mA. At Tc= 120 °C accuracy is -8% to +10%
Table 1-9.
Scale DACs
Parameter
Conditions
Resolution
Minimum scale value
Referred to the current output, equivalent to code 000000b
180
200
220
mA
Maximum scale value
Referred to the current output, equivalent to code 111111b
1.775
2
2.2
A
Scale step
Referred to the current output
25
28.6
31
mA
7
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.8
Rev V4
DC-DC Converters Reference Generators
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-10.
DC-DC Converters Reference Generators
Parameter
Conditions
Minimum
Typical
Maximum
Units
Voltage compliance
0.5
1.2
1.3 V
V
DAC resolution
—
9
—
bits
DAC DNL
-1.3
—
1.3
LSB
DAC full scale
(regref_setup[1]=0b)
—
100
110
µA
DAC full scale
(regref_setup[1]=1b)
—
200
220
µA
-20
—
+20
mV
Minimum
Typical
Maximum
Units
Range
—
-40 to 125
—
°C
Temperature step
—
0.65
—
°C
Absolute accuracy1
-10
—
+10
°C
DC-DC Converter Headroom Configured as per Table 2-4 using a Texas Instruments TPS63020
Error
DC-DC converter and decimation set to 64.
1.9
Internal Temperature Sensor
Typical values: Tc=-40 °C to 100 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-11.
Internal Temperature Sensor
Parameter
Conditions
NOTES:
1.
After system calibration at room temperature (one point calibration).
8
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.10
Rev V4
Light Sources Alarm
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-12.
Light Sources Alarm
Parameter
Conditions
Minimum
Typical
Maximum
Units
Light sensor alarm thresholds1
50
—
200
mV
Threshold accuracy
—
+/-15
—
mV
Alarm response time
—
5
—
µs
NOTES:
1.
Threshold can be programmed through register alarm_setup0/1 to 50 mV, 100 mV, 150 mV, 200 mV.
1.11
CMOS Pins Characteristics
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD = +3.3 V
Table 1-13.
CMOS Pins Characteristics
Parameter
Minimum
Typical
Maximum
Units
VIH1
0.65 DVDD
—
3.63
V
VIL
0
—
0.35 DVDD
V
VOH
DVDD-0.4
—
DVDD
V
V0L
0
—
0.4
V
—
3
—
ns
Rise/fall time2
Conditions
Maximum load of 5 pF. SPI mode
NOTES:
1.
Digital pins are 3.3 V (+/-10%) tolerant
2.
In I2C mode, rise/fall time depends on load and pull up resistor.
9
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
Slave I2C Timing Specifications1,2
1.12
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Tc=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-14.
Slave I2C Timing Specifications1,2
Parameter
Symbol (refer to figure below)
Minimum
Typical
Maximum
Units
Clock Frequency, SCL_M
fSCL_MASTER
—
—
3.4
MHz
Clock Pulse Width Low
tLOW
160
—
—
ns
Clock Pulse Width High
tHIGH
60
—
—
ns
Clock Low to Data Out Valid
tAA
0
—
70
ns
Start Hold Time
tHDSTA
160
—
—
ns
Start Set-up Time
tSUSTA
160
—
—
ns
Data In Hold Time
tHDDAT
0
—
—
ns
Data In Set-up Time
tSUDAT
10
—
—
ns
Outputs (SDA_M, SCL_M, SDA_S and SCL_S) RPULL-UP
internal pull-up resistor value 3
—
250
—
kΩ
Stop Set-up Time
tSUSTO
160
—
—
ns
Data Out Hold Time
tDH
5
—
—
ns
NOTES:
1.
Guaranteed by design and characterization.
2.
Specified at recommended operating conditions.
3.
4.7 kΩ should be added externally.
Figure 1-1.
Slave I2C Timing
10
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.13
Rev V4
High Speed Serial Interface Timing Specifications
Min and Max values: Tc= -40 °C to 85 °C, DVDD=1.8 V+/-5%, ALVDD=1.8 V+/-5%, DHVDD=3.3 V+/-5%,
AHVDD =3.3 V+/-5% unless otherwise noted. Typical values: Ta=25 °C, DVDD, ALVDD=1.8 V, AHVDD =3.3 V
Table 1-15.
High speed serial interface timing specifications
Parameter
Symbol (refer to figure below)
Minimum
Typical
Maximum
Units
Clock Frequency
fclk=1/Tclk
—
—
3.4
MHz
Data in to clk hold time
Tdh
160
—
—
ns
Data in to clk set-up time
Tds
60
—
—
ns
Enable to clk set up time
Tcs
0
—
70
ns
Enable to clk hold time
Tch
160
—
—
ns
Read data output valid Tdd
following rising edge of SCLK
160
—
—
ns
SCLK duty cycle
45
—
55
%
NOTES:
1.
Maximum output capacitance of 30 pF.
Figure 1-2.
Serial Interface Sequential Write
1
2
3
9
10
11
12
13
18
19
20
21
26
27
28
SCLK
Tcs
xCS
Tds
Tdh
SI
1
0
address (A7 ...A0)
1st Data (D7 ...D0)
2nd data( D7...D0)
3rd data
SO
11
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Figure 1-3.
Rev V4
Serial Interface Random Write
1
2
3
9
10
11
12
13
14
15
16
17
18
19
20
SCLK
Tch
Tcs
Tcs
xCS
Tdh
SI
1
0
address (A7 ...A0)
Data (D7 ...D0)
SO
Figure 1-4.
Serial Interface Sequential Read
1
2
3
9
10
11
12
13
18
19
20
21
26
27
27
SCLK
Tcs
xCS
Tds
SI
8-bit address
SO
Figure 1-5.
2nd 8-bits MISO
1st 8-bits MISO
3rd 8-bits MISO (D7,D6 ....D0)
Serial Interface Random Read
1
2
3
9
10
11
12
13
14
15
16
17
18
D6
D5
D4
D3
D2
D1
19
20
SCLK
Tens
xCS
Tds
SI
8-bit address
Tdd
SO
D7
Tdd
D0
12
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.14
Rev V4
M08888 Pinout
The M08888 is packaged in a 4.5 x 4.5 mm 28-pin QFN package with 0.5 mm pin pitch.
22
28
AHVDD
DHVDD
______ _________
CLK/ALARM/LP_MODE
DIS
REGREF
IOUT2
IOUT2
M08888 Pinout
IOUT2
Figure 1-6.
1
21
SCLK/SCL_S
SI/SDA_S
IOUT1
IOUT1
SO/ADDR0
IOUT1
___
CS/ADDR1
IOUT0
IOUT0
I1_ON
15
7
ALVDD
VREF
APC_IN0
APC_IN1
14
APC_IN2
SERSEL
8
I2_ON
DVDD
IOUT0
I0_ON
GND, connect to
PCB ground
with an array of
> 9 vias.
4.5 mm x 4.5 mm
13
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 1-16.
Rev V4
Pin List and Descriptions
Pins
Name
Type
Function
1
AHVDD
Supply
3.3 V analog supply
2, 3, 4
IOUT1
Analog
Channel 1 output
5, 6, 7
IOUT0
Analog
Channel 0 output
8
SerSEL
CMOS (w/ pulldown)
9, 10, 11
APC_IN
Analog
Monitor PD inputs (assignable)
12
VREF
Analog
Current reference generator
13
ALVDD
Supply
1.8 V analog supply
14
DVDD
Supply
1.8 V digital supply
15
I2_ON
CMOS (w/ pulldown)
Turns on driver 2
16
I1_ON
CMOS (w/ pulldown)
Turns on driver 1
17
I0_ON
CMOS (w/ pulldown)
Turns on driver 0
18
CS/ADDR0
Open Drain (w/ pull-up)
Serial enable/I2C address0
19
SO/ADDR1
Open Drain (w/ pull-up)
Serial data out/I2C address1
20
SI/SDA_S
Open Drain (w/ pull-up)
Serial data in/I2C data slave
21
SCLK/SCL_S
Open Drain (w/ pull-up)
Serial clock/I2C clock slave
22
DHVDD
Supply
23
CLK_IN/ALARM/LP_MODE
CMOS (w/ pulldown)
24
DIS
CMOS
Disable Pin
25
REGREF
Analog
DC-DC converter control voltage
26, 27, 28
IOUT2
Analog
Channel 2 output
GND
Supply
Ground
Serial interface select (L=I2C,H=SPI)
3.3 V digital supply
CLK_IN pin or ALARM or LP_MODE pin
NOTES:
PD means pulled down, PU means pulled up.
4.7 µF + 100nF should be used on each of the M08888 supply.
14
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
1.15
Figure 1-7.
Rev V4
Package Information
Package Information
15
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
2.0 Functional Description
The M08888 is a highly integrated LED/laser driver for LCD/LCoS/DLP projection display applications. It provides
control and monitoring of up to three LEDs/lasers, a temperature sensor and control of external DC-DC converters
for optimal laser/led supply voltage.
Each Laser/LED output consists of a 10 bit DAC which controls a high efficiency driver. If the desired maximum
current is less than 2A the output resolution can by improved by a 6 bit independent scaling DAC.
The output stages require only 300 mV of headroom between the M08888 output and the Laser/LED cathode
when driving 2 amperes. The headroom requirement can be scaled proportionally lower for lower currents.
The M08888 also incorporates safety and alarm features and a temperature monitor with 8 bit resolution.
The M08888 internal registers are loaded from an external micro controller through a slave I2C interface or a 4-wire
high speed interface. The host micro controller can monitor the temperature sensor and read back the analog to
digital converter outputs and status registers using either serial interface.
2.1
Operating Modes
The M08888 can operate in 3 different optical power control modes. The power control modes are open loop (OL)
and 2 automatic power control (APC) modes: continuous power control (CPC) and integrating power control (IPC).
Different output channels can have different operating modes. Some channels may be configured as Open Loop
and some channels may be configured to use APC (either CPC or IPC).
Open Loop mode is the simplest mode of operation and the Laser/LED current is set by writing the desired current
to the output DAC.
The 2 automatic power control modes (APC) use monitor photodiode feedback to accurately adjust the Laser/LED
output power to make the current from a photodiode match a target current. With APC control temperature
compensation of the Laser/LED is automatic and color balance is simplified.
The user can select the polarity of the monitor photodetector if an APC mode is selected. By default the M08888
accepts a current source monitor photodetector (MPD) tied to the positive supply. It is possible to accept current
sink MPD by selecting ipc_setup[4]=1b.
Configuration of the M08888 timer settings and pin 23 configuration will also affect optical power control.
2.1.1
Open Loop Output Control
In open loop mode the current for each Laser/LED is stored in register (ioutx[9:0]). The M08888 will shift the
contents of ioutx[9:0] and ioutx_scale[5:0] registers to the output DAC when pin Ix_ON goes high and the output
will then sink the programmed current through the Laser/LED.
16
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
By changing the scale setting ioutx_scale the full 10 bits of settability can be retained even for low Laser/LED
currents. The scale can be changed on a frame by frame basis but when ioutx_scale is changed the rise time of the
output stage will be significantly slower during the first Ix_ON period in which the change in the scale is made. The
rise time will return to its normal value in subsequent Ix_ON periods if the scale is not changed.
The M08888 includes timers that can be used to delay, pulse width modulate or clock the Open Loop output signal.
See Section 2.4 for a description of how to use these features.
When pin 23 operates in LP_MODE (input_ctrl[6:5]=10b) the scale value of each channel can be different for the
different pin 23 states. These scales are set in ioutx_scale[5:0] (pin 23=H) and ioutx_scale_LP[5:0] (pin 23=L).
Table 2-1.
Name
Basic Register Configuration for Open Loop Control (when REGREF is not controlling a DCDC Converter)
Address
Recommend
Setting
Description
out_ctrlx
0x05[7],0x06[7],
0x07[7]
1b
Set outputs to Open Loop Control if Regref is not used to control a DC-DC converter at
this output.
pd_fe
0x0A[0]
1b
Power down photodiode amplifier (if all channels are under open loop control)
ioutx_msb
0x10[1:0], 0x14[1:0],
0x18[1:0]
xxb
Two most significant bits of output current setting
ioutx_lsb
0x11, 0x15,0x19
xxh
Eight least significant bits of output current setting
ioutx_scale
0x12, 0x16, 0x1A
11xxxxxb
Set the scaling of the output currents
ioutx_scale_lp
0x13, 0x17, 0x1B
11xxxxxb
Set the scaling of the output currents in Low Power mode
apc0_ch
0x34[1:0]
11b
Disable APC input for selected channel
apc1_ch
0x34[3:2]
apc2_ch
0x34[5:4]
2.1.2
Automatic Power Control
Automatic power control (APC) can keep the laser/led power constant and the color balanced by comparing the
monitor photodetector (RGB color sensor) currents to target values programmed into the 13-bit target DACs.
At power-up the APC can be enabled/disabled independently for each channel by setting apc_ctrl0[5:0]=11. For
channels with disabled APC the laser/led currents are controlled through the serial interface using bits ioutx[9:0].
It is possible to freeze the APC loop for each channel by using apcx_freeze[0]. In this case the M08888 will stop
updating the IOUTx currents independently of the state of Ix_ON pins.The photodiode (RGB sensor) target values
are programmed via the serial interface in registers target2[12:0], target1[12:0] and target0[12:0] respectively for
IOUT2, IOUT1 and IOUT0. When the corresponding color is turned on as signaled by the transition of I0_ON,
I1_ON or I2_ON from low to high the LED/Laser drive currents are automatically adjusted up or down to always
make the photodetector current (RGB sensor current) match the target current.
If desired, these target currents can be adjusted on a frame by frame basis to optimize contrast and save battery
power depending on the brightness required for a particular frame.
17
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
The target values are stored in registers target2[12:0], target1[12:0] and target0[12:0] respectively for IOUT2,
IOUT1 and IOUT0 before the corresponding color is turned on by the transition of I2_ON, I1_ON or I0_ON from low
to high. This allows for the control of the LED/laser power in real time on a frame by frame basis.
When one of the Ix_ON signals is enabled (low to high transition), the target DAC value for that input is activated
and the incoming monitor photodetector current is selected by the analog multiplexer from APC_IN0, APC_IN1 or
APC_IN2. The monitor photodetector input is assigned to an output using apc_ctrl[5:0].
Each Laser/LED can have its own photodetector or all the Lasers/LEDs can share a single broadband
photodetector. For example, if a single broadband photodetector is used and connected to APC_IN0 all the
apc_ctrl0[5:0] should be set to 00b. It should be noted that the index in the APC registers does not refer to the input
channel but to the Laser/LED output channel. If the monitor photodetector feedback for IOUT2 is tied to APC_IN0
then apc_ctrl[5:4]=00 and the settings for the monitor photodetector should be programmed in the APC registers
with index 2.
If more then one laser is turned on (2 or 3 of I0_ON, I1_ON or I2_ON are high at the same time) the M08888
freezes the update of the APC loop for as long as more then one of the Ix_ON signals are high. This prevents the
APC loop from using incorrect photodetector information in case a single photodetector is used. In the case of
multiple Ix_ON simultaneously the optical power tracked and adjusted is that of the channel corresponding to the
lastIx_ON transitioning high. It should be noted that 2 or more low to high transitions of any of the I0_ON, I1_ON or
I2_ON within 500 ns of each other would violate internal timing and will result in unpredictable operation. Care
should be taken to prevent damage to the part when multiple lasers are enabled. The power dissipation of the
M08888 should be kept below the level that, when multiplied by the thermal resistance of the package in the
system and added to the maximum ambient temperature, does not exceed 125 °C.
The maximum photodiode current supported by the M08888 is 3.25 mA. The full scale value of the target DAC is
3.25 mA with a resolution of 13 bits (390 nA step size). As an example, if the maximum current from the
photodiode is 200 µA then the possible target values are up to 512 decimal (200 µA/390 nA). In this example the
maximum target value for targetx[12:0] would be 200h.
Readback of the output current DAC of each channel is possible by strobing the DACs using strbalarm_ctrl[1] and
reading registers rb_ioutx[9:0]
When pin 23 is set to LP_MODE (input_ctrl[6:5]=10b) the target power value will be controlled by the state of pin
23. When pin 23 is high the Laser/LED current will be adjusted until the monitor photodiode current matches the
target in register targetx[12:0] and when pin 23 is low the Laser/LED current will be adjusted until the monitor
photodiode current matches the target in register targetx _LP[12:0].
The M08888 is capable of accepting also current sink type monitor photodetector typical of LCOS panels. This can
be done by setting register ipc_setup[4]=1b. When sink MPD is selected the mirror ratio can be selected between
1:1 and 4:1 by setting bit ipc_setup[5].
The MPD can have a maximum capacitance of up to 300 pF however in this case the M08888 will operate only
with a single broadband photodetector.
2.1.2.1
Continuous Power Control
In continuous power control (CPC) mode, the M08888 continuously compares the monitor photodetector current to
a target value and makes monitor photodiode current match the target value by adjusting the current in the laser/
LED.
For example, if the monitor photodetector current is below the target then the Laser/LED current is
increased. The sign of this operation can be inverted using input_ctrl[4] (but it should not be changed unless it is
certain that there is an inversion in the monitor photodiode signal).
18
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
The CPC loop is designed to settle to the desired output power in less than 50 µs. To achieve optimal settling time,
the CPC loop must be adjusted to the laser/monitor photodetector characteristics. This is done using the settings in
apcx_ctrl0, apcx_ctrl1 and apcx_ctrl2.
To further reduce the settling time the user can program the initial current from which the CPC loop will start. This
can be 0, the value programmed in ioutx[9:0] register or the value to which the CPC had converged during the
previous frame. The selection of the initial current is done using register iturnonx[1:0] (apcx_ctrl1[3:2]). Starting
from the previously determined value will substantially accelerate settling time since it is likely that it will be starting
at the proper level.
It is possible to “freeze” the APC loop for each channel by using apcx_ctrl0[0]. When apcx_ctrl0[0]=1b the M08888
will stop updating the IOUTx currents irregardless of the state of Ix_ON pins. It is possible also to delay operation
the CPC loop immediately following the light source turn-on. This will allow the DC-DC converter to settle to the
proper voltage before the APC starts adjusting the current. The CPC delay time can be programmed using register
apcx_ctrl0[2:1].
Table 2-2.
Basic Register Configuration for CPC Control
Recommend
Setting
Name
Address
out_ctrlx
0x05[7],0x06[7],
0x07[7]
1b
Set output to Closed Loop Control
loop select
0x34[6]
1b
Select CPC loop control
apc0_ch
0x34[1:0]
apc1_ch
0x34[3:2]
xxb
apc2_ch
0x34[5:4]
Select which photodiode (RGB sensor) input will control which output. Setting depends on
hardware connection to photodiode(s) and which channels will use APC control. See
Register description for details.
targetx_msb
0x35, 0x37, 0x39
000x xxxxb
targetx_lsb
0x36, 0x38, 0x3A
xxh
apc0_ctrl2
0x47
xxh
apc1_ctrl2
0x44
Set the length in clock counts of the initial, mid and min step intervals. Set the delay for the
clock divider. The decimation factor and clock divider will also affect interval lengths.
apc2_ctrl2
0x41
apc0_ctrl1
0x48
xxh
apc1_ctrl1
0x45
apc2_ctrl1
0x42
Set the step size of the change in LED drive current for the initial and mid intervals. Set the
initial LED current to be 0 mA, the ending value of the previous I_on period or the value set
in ioutx register. Set the clock divider.
apc0_ctrl0
0x49
xxx00xx0b
apc1_ctrl0
0x46
apc2_ctrl0
0x43
Set the decimation factor (mid and min count changes will occur at rate divided by the
decimation factor). Set the WAIT states (APC will not change LED current during WAIT
states).
2.1.2.2
Description
Set the target at desired level. The LED drive current will be adjusted up or down until the
photodiode current is equal to the target current for the channels that are controlled by CPC.
Integral Power Control
Integral power control (IPC) can be enabled by setting registers apc_ctrl[6]=0b.
The working principle of integral power control is to mimic the behavior of the human eye which integrates the
optical power over the frame period. This is achieved in the M08888 by charging a capacitor with the monitor
photodetector current.
19
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
When Ix_ON goes high the M08888 will drive the Laser/LED with a current defined by register ioutx[9:0]. The
monitor photodiode current will charge an internal capacitor until its voltage matches an internal reference voltage
(~0.8 V) at which time a counter is incremented and the capacitor is discharged. The monitor photodiode current
continues to charge the capacitor and increment the counter until the count matches the target set by the user in
registers targetx[9:0]. Once the counter reaches the value set by the user the M08888 stops driving the Laser/LED.
By adjusting the count higher or lower the brightness of a frame can be adjusted. The target counter has 10bits and
the M08888 can distinguish between 1024 different power levels. The target registers are the same of the CPC
target registers but the resolution in IPC mode is limited to 10 bits instead of 13 bits.
In order to maximize the dynamic range and be able to utilize the entire 10bits the user must select the proper
mirroring ratios for the monitor photodetector current (ipdx_sel[4:0]), the charging current (ichx_sel[4:0]) and the
value of the capacitance (capx_sel[3:0]). The settings of these bits will depend on the frame (or subframe) duration
and on the monitor photodetector current.
If it is desired to typically have the LED on for 1/2 the frame time then the registers should be configured such that:
1/2 x FR/512 = 0.8 V x Cch / Ich
where FR is the frame or subframe rate, Cch is the charging capacitors selected through capx_sel[3:0], and Ich is
the resulting charging current obtained by multiplying the monitor photodetector current by the ipdx_sel[4:0] and by
the ichx_sel[4:0] mirroring ratios. The factor of 512 is length of the 10 bit range.
Cch = 25 pF + N x 2.5 pF where N is the setting of capx_sel[3:0].
Ich = (IMPD / ipdx_sel[4:0]) x ichx_sel[4:0] where IMPD is the monitor photodiode current
Example:
Assume that the monitor photodiode current is 150 µA when the LED is on at the desired
amplitude, the Ix_ON time is 1 ms and it is desired that the LED be on approximately 50% of this
time. The mirroring ratio should be set to the 200 µA range ichx_sel[4:0] = 00001b, choose a Cch
= 25 pF with ichx_sel[4:0] = 00000b (any other value is also OK but using the default value means
this register never needs to be written), choose a mirroring ratio such that the Cch can be charged
to 0.8 V several hundred times in 0.5 ms. (if it is desired that it be charged ~250 times in 0.5 ms
then:
0.5 ms/250 =0.8 V x 25 pF /((150 µA / 200 µA) x ichx_sel[4:0])
0.002 ms = 26.67e-12 / ichx_sel[4:0]
ichx_sel[4:0] = 2.667e-5 / 2 which is between 10 µA and 20 µA so set ichx_sel[4:0] =00001b
As in CPC mode, when pin23 operates in LP_MODE (input_ctrl[6:5]=10b) the target power value can be changed
by toggling pin23. When pin 23 is high the Laser/LED current will be on until the monitor photodiode count
matches the target in register targetx[9:0] and when pin 23 is low the Laser/LED current will be on until the monitor
photodiode count matches the targetx _LP[9:0].
The monitor photodiode input can be changed from sinking to sourcing at ipc_setup[4] and an additional scaling
factor of 4:1 is available at ipc_setup[5].
20
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 2-3.
Rev V4
Basic Register Configuration for IPC Control
Name
Address
Recommend
Setting
ipc_setup[4]
0x4Ah[4]
0b or 1b
out_ctrlx
0x05[7],0x06[7],
0x07[7]
1b
Set output to Closed Loop Control
loop select
0x34[6]
0b
Select IPC loop control
apc0_ch
0x34[1:0]
apc1_ch
0x34[3:2]
xxb
apc2_ch
0x34[5:4]
Select which photodiode (RGB sensor) input will control which output. Setting depends on
hardware connection to photodiode(s) and which channels will use APC control. See
Register description for details.
targetx_msb
0x35, 0x37, 0x39
000xxxxxb
targetx_lsb
0x36, 0x38, 0x3A
xxh
ioutx_msb
0x10[1:0],
0x14[1:0], 0x18[1:0]
xxb
Two most significant bits of output current setting
ioutx_lsb
0x11, 0x15,0x19
xxh
Eight least significant bits of output current setting
ioutx_scale
0x12, 0x16, 0x1A
11xxxxxb
ipdx_sel
0x4C[4:0]
0x4F[4:0]
0x52[4:0]
x xxxxb
Select a setting that is greater than the peak current expected from the monitor photodiode.
Choosing a lower amplitude setting will give more resolution/accuracy in setting the IPC
target.
ichx_sel
0x4D[4:0]
0x50[4:0]
0x53[4:0]
x xxxxb
Select a current range that can charge the IPC capacitor several hundred (but 10 µs) when Ix_ON=L (blanking
period), opmode_ctrl1[7] should be set to 1. In this case during the blanking period the DAC current is set to 0 and
all the IOUTx signals are disconnected so that an external resistor divider network can be used to set the light
sources anode voltage. The impedance level at REGREF pin, defined by R1//R2//input impedance of the DC-DC
converter, should always be greater then 500 kΩ.
2.4
Timers
The M08888 features internal timers which allow an extra layer of control of the current by means of pulse width
modulation (PWM) and multi pulse generation (MPG).
The clock source for the internal timer circuitry can be either the internal 25 MHz oscillator or an external clock fed
through CLK_IN (pin 23).
With reference to the following diagram for channel 0 (I0_ON, IOUT0), PWM controls the “On delay time” while
MPG adjusts independently both the “Pulse on time” and “Pulse off time”.
Figure 2-1.
Example of PWM and MPG Timers
I0 _O N
M ulti pulse gen ration
(M P G )
P u lse w id th m od ula tio n
(P W M )
IO U T 0
O n delay tim e
P ulse on tim e
P ulse o ff tim e
C olor fram e/subfram e tim e
24
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
2.4.1
Rev V4
Pulse Width Modulation (PWM)
Activating pulse width modulation will allow the output current to be delayed with respect to the Ix_ON signal. This
may be useful if a blanking period is needed to allow the LCD or DLP to settle or it may be useful to save power if
a laser is used and the same optical output can be achieved with fewer coulombs if higher laser driver currents and
shorter durations are used (the coulombs will be less with higher current and shorter duration if the laser threshold
current is approximately the same with PWM activated at higher current as it is at lower current without PWM
activated).
PWM works in all optical power control modes: Open Loop, CPC and IPC.
The PWM delay is implemented with a 10 bit counter that counts the clock cycles of an internal 25 MHz oscillator.
At the rising edge of each Ix_ON the counter is decremented and the Laser/LED is turned on when the counter
reaches 0. The laser is turned off as usual on the falling edge of the corresponding Ix_ON signal. The maximum
delay achievable is ~41 µs (1023 times the 40 ns period of the internal oscillator). Additional delay can be achieved
by using the M08888 programmable divider of the internal clock. The internal clock can be divided down by a factor
of 1, 2, 4, 8, 16, 32, 64, and 128. This can be obtained by writing register clk_div_pwm[3:0]. The maximum delay is
therefore equal to ~5.24msec.
The values of the programmable counter are stored in register on_countx[9:0]. The rising edge of the Ix_ON signal
strobes the corresponding on_countx[9:0] value into the M08888 in the same fashion as other output current
settings such as registers targetx[12:0] and ioutx[9:0] registers. If the on_count register value is changed during
the on time for that color the effect of the register change will be available during the next Ix_ON cycle.
If the on_countx is programmed to 000h the PWM feature is disabled for IOUTx.
The internal ring oscillator clock will vary by as much as +/-15% over process, temperature and supply. If this
accuracy is not acceptable then pin 23 can be defined to be a clock input and a more accurate external clock signal
can be used. The PWM block is designed to operate with a maximum frequency of 25 MHz. The PWM generator
will work at the speed of the signal at CLK_IN (pin 23) when the external clock is selected with register clk_ctrl[2:1].
2.4.2
Figure 2-2.
Multi Pulse Generator (MPG)
Multi Pulse Generator Timing
I0_ON
IOUT0
On delay time
Pulse on time
Pulse off time
30% frame time
A less than 100% duty cycle pulsed waveform can be programmed into the M08888 using the Multi-Pulse
Generator (MPG).
25
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
The multi-pulse generator (MPG) operates in a similar manner of the PWM generator. For each of the Lasers/LED
outputs, two 10bit counters specify the number of 25 MHz internal clock cycles during which the output is on and
off. As with the PWM timer, the MPG timer can be controlled by an external clock signal at CLK_IN (pin 23).
The duty cycle of the pulsed waveform is resolved in 25 MHz clock periods or 40 ns steps. If both counters are
loaded with the maximum value (1023) the waveform driving the output will be a clock of period ~81 µs.
The clock can be divided down to lower rates by programming register clk_div_mpg[3:0].
MPG works in all optical power control modes: Open Loop, CPC and IPC. However if IPC or CPC power control is
employed, the minimum divider ratio at register clk_div_mpg[3:0] is 8. Care should be taken when MPG is used
while controlling the DC-DC converter as the slow response time of the DC-DC converter to variation in the light
source drop may create oscillation and instability. It is recommended that register opmode_ctrl0[5]=1 if analog
control mode is used to control the DC-DC converter. In this setting the DC-DC converter feedback will not be
driven while the LED current is off (pulse off time). To prevent the DC-DC converter from drifting away from the
optimal headroom operating point external resistive feedback R1/R2 should be added as shown in figure 1-2. The
effective resistance of R1/R2 should be 500 kΩ.
Because a 10 bit counter is used, the duty cycle resolution obtainable is 1/1023 or better then 0.1% assuming the
highest count value is used for one of the counters. The duty cycle accuracy is inversely proportional to the
maximum counter value.
The control for the IOUTx output on pulse is programmed in register pulse_onx[9:0]. The off pulse is programmed
in pulse_offx[9:0].
The rising edge of the Ix_ON signals strobe the corresponding pulse_on/offx[9:0] values into the M08888 timing
controller. If the pulse_on/pulse_off register values are changed during the on time for that output the MPG setting
will not be changed until the next Ix_ON cycle.
If either the pulse_on or pulse_off for a channel is programmed to 000h then the MPG function is disabled for that
channel.
2.5
Temperature Sensor
The M08888 features an internal temperature sensor which measures the internal junction temperature of the part.
The information is converted by the ADC and can be read through the serial interface at temp[7:0] register.
The ambient temperature of the system can be calculated from the part junction temperature, the part power
dissipation and the package thermal resistance (temperature measurements can vary dramatically at different
locations within a system and measurements are dependent on mechanical factors such as PCB area, material
and number of layers, airflow, heatsinking, etc.)
Absolute accuracy of the temperature sensor is +/-10 °C after calibration at room temperature. Its resolution is 8-bit
or 0.65 °C over the range of -40 °C to 125 °C.
2.6
26
Safety
Using this driver for LEDs or Lasers in the manner described in this data sheet does not ensure that the resulting
optical emissions comply with established standards such as IEC825. Designers must take the necessary
precautions to ensure that eye safety and other applicable standards are met. Note that determining and
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
implementing the level of fault tolerance required by the applications that this part is going into is the responsibility
of the projector designer and manufacturer since the application of this device cannot be controlled by MACOM.
A register alarm is available: the safety monitor block compares the output current of each Laser/LED with 3
thresholds (one for each of the lasers/LEDs) and an alarm is issued if the current is higher then the programmed
thresholds. The digital thresholds can be programmed in the following registers: alarm_thx[7:0], these represent
the MSB of the output current.
The alarm can be routed to the CLK_IN (pin 23) by setting input_ctrl[6:5]=00b. This signal can be used externally
to shut down power to the lasers/LEDs or it can be read back from register alarm_ctrl[7:2] by the micro controller. It
should be noticed that the alarm_ctrl[7:2] register is not self clearing: once an alarm has occurred, it must be
cleared by the user by writing 1 to clear_alarm (strbalrm_ctrl[0]).
The M08888 can also be programmed (opmode_ctrl1[3]) for automatic shutdown if the programmed threshold is
exceeded. In this case the output current for that output is automatically forced to 0 by forcing 0 to the DAC inputs.
This feature can be disabled via registers.
When configured as ALARM pin 23 is an open collector and can operate in status mode and interrupt mode. This
can be selected through opmode_ctrl0[3]. In status mode the alarm is provided directly to the pin. It should be
noticed that in status mode the alarm may be issued only for the duration of one clock cycle of the internal high
speed clock. Because of the high speed of the digital engine (12.5 MHz clock) a load which acts as a low pass
filter will prevent this signal from being recognized by external circuitry. Excess capacitance and high impedances
may act as low pass filters. In interrupt mode the M08888 will issue a positive going pulse on the alarm pin every
time the internal alarm changes state. The width of the generated pulse can be programmed at opmode_ctrl0[2:0].
The output stage can also be disabled by the user via register, through bits opmode_ctrl1[1].
2.7
Alarm
The M08888 is capable of detecting an open or a short at the driver outputs and it will issue an alarm if a voltage
lower then the programmed threshold is detected at the IOUTx outputs while the Laser/LED is not driven. Similarly,
while the Laser/LED is driven, an alarm is issued if the voltage at IOUTx decreases below a preprogrammed
threshold. This would indicate an open LED as the driver will force the IOUTx voltage to 0 if no LED is connected.
The LED alarms can be enabled and programmed independently for each channel using registers
alarm_setup0[7:0] and alarm_setup1[3:0].
If pin23 is configured as ALARM the alarm is issued at that pin but the alarm can also be read back at
alarm_iout[2:0]. Alarm _iout[2:0] is not self clearing.
To prevent false alarms caused by slow DC-DC converter settling the alarm signal can be delayed using
alarm_set1[5:4].
2.8
Programmable Serial Interface
The M08888 will not begin operation until the internal registers of the M08888 are loaded and the start bit is set
(0x61[0]=1b). It is not necessary to load values into a register if its default value is acceptable.
27
The M08888 can be configured to use a 4 wire high speed serial interface or I2C. This can be achieved by
connecting pin SERSEL high or low respectively.
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
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For further information and support please visit:
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
When the part is configured to use I2C, an external host µController can access the register and read-back ADC
from the slave I2C (SDA_S/SCL_S). The maximum SCL_S supported is 400 kHz. The slave address of the part
can be programmed using ADDR0/1 pin. The address of the M08888 will be set to 98h, 9Ah, 9Ch or 9Eh when
writing from the M08888 and 99h, 9Bh, 9Dh or 9Fh when reading to the M08888 when ADDR0/1 pin configured
respectively to 00b, 01b, 10b or 11b.
4.7 kΩ pull up resistors should be used.
The 4 wire high speed interface (SCLC/SI/SO/CS) supports up to 40 MHz serial clock speeds.
2.9
Power Sequencing
To obtain reliable operation from the M08888 the power-up and power-down sequencing described in the diagrams
below must be followed.
Figure 2-3.
Power-Up
DVDD, ALVDD, AHVDD
>10μsec
0V
Red, green and blue laser supply
0V
Figure 2-4.
Power-Down
DVDD, ALVDD, AHVDD
>1μsec
0V
Red, green and blue light supply
0V
28
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
2.10
Rev V4
Driving a String of LEDs from a High Voltage
Supply
An M08888 can be used to drive a string of LEDs as shown in Figure 2-5 below. The M08888 must be isolated
from the high voltage by an NFET transistor. The NFET should have a breakdown voltage greater than the high
voltage supply and should also have a very low on resistance at 2.5 V gate-source voltage. The Diodes Inc.
DMN2075U is an example of a suitable 20 V NFET.
Figure 2-5.
Driving a String of LEDs from a High Voltage Supply
High Voltage
String of LEDs
+3.3V
N-Channel, low Rds,
high Vbr
M08888
IOUTX
2.11
Layout Considerations
The center pad of the package is the electrical ground and the heat sinking path for the M08888. The center pad
should be connected to an internal ground plane through an array of 9 or more vias.
The accuracy of the internal DACs and the LED/laser drive amplitudes and timing depend on pin VREF being
noise-free. The resistor at this pin should be close to the M08888 and the via to ground from the resistor should be
nearby.
29
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
The external DC-DC converter will amplify any noise on the REGREF pin. Care should be taken in routing this pin
so it is not parallel to the laser/LED drive signals or clock signals.
Decoupling capacitors should be on the same side of the PCB as the M08888 and close to the pin they are
decoupling. Vias to ground and voltage supplies should not be shared by components or signals (crosstalk
between signals will occur).
30
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
3.0 Registers
Table 3-1.
Addr
M08888 Registers
Register name
d7
d6
d5
d4
d3
d2
d1
d0
Default
Type
01000000
R/W
00000000
R/W
General REGISTERS
00h
opmode_ctrl0
parallel
1. Enable
parallel
mode of
operation
0: Normal
mode of
operation
pd_target
regref_
DAC
mpg
Powers down
target DAC:
1: powers
down target
DAC
1: disconnect regref
control
during mpg
(Open loop control)
0: normal
operation
(APC Conrol)
01h
opmode_ctrl1
regref_
regref_edge
selfcal_hr
alrm_ctrl
1: enable self- Controls the behavior of the Alarm
cal of output
headroom for 1xxx: Status mode
all channels
0000: Interrupt mode with 1 cycle pulse width
(Recommended (1cycle=20 ns)
for control of
0. do not
0001: Interrupt mode with 2 cycle pulse width
external DC-DC
converter)
disconnect
0010: Interrupt mode with 4 cycle pulse width
refreg
….
during mpg 0: disable self 0111: Interrupt mode with 128 cycle pulse width
calibration
event
seq
RSVD
alarm_dis
RSVD
RSVD
Disable output on alarm:
RSVD
disable
RSVD
blank
1: When all
Ix_ON low
disconnects
IOUTx and
sends 0
code to
IDAC (controlled by rising edge)
Switch regref Color
sequence
output on:
selector in
1: Ix_ON fall- case of falling edge:
ing edge
0: Ix_ON rising edge
1: disable
output current on alarm
1: 2-1-0
0: 2-0-1
0: do not disable
Outputs
disabled
RSVD
1: IOUTx
disabled
0: IOUTx
enabled
0: Normal
operation
(01h[6] setting controls
regref)
31
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
d7
02h
input_ctrl
timer_clk
d6
Configuration register for
PIN23
11: RSVD
10: Pin 23 is LP_MODE
01: Pin 23 is CLK_IN
00: Pin 23 is ALARM
0: Normal
operation
(timers use
internal
oscillator)
04h
d5
pin23_def[1:0]
1: Use
CLK_IN as
clock for the
timers
(MPG/PWM)
03h
Rev V4
d4
d3
d2
d1
d0
Default
Type
RSVD
regref_pol
I2_ON_pol
I1_ON_pol
I0_ON_pol
00000000
R/W
Polarity of
I2_ON
Polarity of
I1_ON
Polarity of
I0_ON
1: Flipped
1b: Flip polar0: Normal
ity
1: Flipped
1: Flipped
0: Normal
0: Normal
00000000
R/W
00000000
R/W
10001100
R/W
RSVD
Flip regref
counter
polarity
0b: normal
polarity
clk_ctrl
clk_delay
RSVD
clkin_div[1:0]
duty_en
Input clock programmable delay:
0000 = nodelay
0001 = 500nsec
0010 = 1000nsec
…
1111 = 7500nsec
RSVD
Input clock divider:
00: 1
01: 2
10: 4
11: 3
1: enable duty
cycle control
RSVD
0: disable duty
cycle control
RSVD
RSVD
05h
out_ctrl2
feedONOff_iout2
feedBias_iout2[1:0]
RSVD
BiasOnOf_i
out2
1: Closed
loop IOUT2
output current control
Set the bias level of the
Regref2 loop:
RSVD
Increases
Regref2
bias current to
inprove
performance at
low currents
0: open loop
output current control
(Set to 1b in
all cases if
DC-DC converter is controlled by
Regref for
this output)
11: 1.8 V
10: 600 mV
01: 500 mV
00: 400 mV
(00 is recommended)
pd_iout2[1:0]
Power down control
11: Regref2 always on
regardless of Ix_ON signal
10: Fast power down
01: Deep sleep when
Ix_ON=L
00: Deep sleep when
Ix_ON=L
1: Enabled
0: Disabled
32
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
d7
06h
out_ctrl1
feedONOff_iout1
feedBias_iout1[1:0]
RSVD
BiasOnOf_i
out1
1: Closed
loop IOUT1
output current control
Set the bias level of the
Regref1 loop:
11: 1.8 V
10: 600 mV
01: 500 mV
00: 400 mV
RSVD
Increases
Regref1
bias current to
inprove
performance at
low currents
0: open loop
output current control
(Set to 1b in
all cases if
DC-DC converter is controlled by
Regref for
this output)
07h
out_ctrl0
tempsens_ctrl
d6
d5
d4
d3
d2
d0
pd_iout1[1:0]
Default
Type
10001100
R/W
10001100
R/W
01100000
R/W
Power down control
11: Output stage always on
regardless of Ix_ON signal
10: Fast power down
01: Deep sleep when
Ix_ON=L
00: Deep sleep when
Ix_ON=L
0: Disabled
feedBias_iout0[1:0]
RSVD
BiasOnOf_i
out0
1: Closed
loop IOUT0
output current control
Set the bias level of the
Regref0 loop:
11: 1.8 V
10: 600 mV
01: 500 mV
00: 400 mV
RSVD
Increases
Regref0
bias current to
inprove
performance at
low currents
1: Enabled
temptest_
sel
d1
1: Enabled
feedONOff_iout0
0: open loop
output current control
(Set to 1b in
all cases if
DC-DC converter is controlled by
Regref for
this output)
08h
Rev V4
pd_iout0[1:0]
Power down control
11: Output stage always on
regardless of Ix_ON signal
10: Fast power down
01: Deep sleep when
Ix_ON=L
00: Deep sleep when
Ix_ON=L
0: Disabled
pd_temp
1: Powers
down temp
sensor
temp_cal[3:0]
temp_gain[1:0]
Temperature sensor offset calibration
Calibrate temp sensor gain
0: Temp sensor enabled
33
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
d7
d6
09h
tia_ctrl
cpd_comp
cf_ctrl
cz_ctrl
rz_ctrl
Controls
value of TIA
Cf
Controls value of CZ: APC
compensation control:
11: 14 pF
10: 10 pF
01: 8 pF
00: 4 pF
Controls value of Rz: APC
compensation control:
1x: 2.5kOhms
01: 3.75kOhms
00: 5kOhms
Cpd compensation
1: 16 pF
0: 9 pF
0Ah
apc_fe_ctrl
1: 700fF
0: 500fF
d5
d4
d3
d2
d1
d0
Default
Type
rf_ctrl
00100110
R/W
Controls value of Rf: TIA
gain control:
11: 20kOhms
10/01: 40kOhms
00: 60kOhms
tia_ctrl_d
RSVD
Cpd_comp[1:0]
RSVD
pd_fe
RSVD
Photodiode compensation
for APC inputs
RSVD
APC photodiode amplifier
power down
00000001
R/W
00000000
R/W
00010001
R/W
1: power down
(no photodiode feedback
or color sensor)
0: normal
operation
(APC Control)
0Bh
bandgap
RSVD
bg_set
set to 0101b
RSVD
0Ch
alarm_setup0
led_alrm_rc1
led_alarm_thres1
LED alarm
time constant
LED alarm threshold for
channel 1
1: 5usec
0: 2usec
00: 200 mV
01: 150 mV
10: 100 mV
11: 50 mV
en_ledalarm1
led_alrm_rc0
led_alarm_thres0
LED alarm
LED alarm threshold for
Power down
channel 0
LED alarm for time constant
channel 1
00: 200 mV
1: power down 1: 5usec
01: 150 mV
0: enable
0: 2usec
10: 100 mV
11: 50 mV
en_ledalarm0
Power down
LED alarm for
channel 0
1: power down
0: enable
34
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
0Dh
alarm_setup1
d7
d6
d5
d4
11h
d3
d2
d1
d0
Default
Type
00110001
R/W
00000000
R/W
00000000
R/W
00111111
R/W
00111111
R/W
00000000
R/W
00000000
R/W
RSVD
turnon_alarm_delay
led_alrm_rc2
led_alarm_thres2
en_ledalarm2
RSVD
Delay alarm after channel
turn on
LED alarm
time constant
LED alarm threshold for
channel 2
Power down
LED alarm for
channel 2
1: 5usec
0: 2usec
00: 200 mV
01: 150 mV
10: 100 mV
11: 50 mV
11: 50usec
10: 100usec
01: 200usec
00: 500usec
10h
Rev V4
iout2_msb
1: power down
0: enable
RSVD
iout2[9:8]
RSVD
IOUT2 MSBs
iout2_lsb
iout2[7:0]
IOUT2 LSBs
12h
iout2_scale
RSVD
iout2_scale[5:0]
RSVD
Adjusts IOUT2 full scale
63d = 2A
...
28d = 1A
…
1d = 228.27
0d = 200 mA
13h
14h
15h
iout2_scale_LP
RSVD
iout2_scale[5:0]
RSVD
Adjusts IOUT2 full scale when LP_MODE pin is low
63d = 2A
…
1d = 228.27
0d = 200 mA
iout1_msb
iout1_lsb
RSVD
iout1[9:8]
RSVD
IOUT1 MSBs
iout1[7:0]
IOUT1 LSBs
35
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
16h
iout1_scale
17h
18h
19h
Rev V4
iout1_scale_LP
d7
d6
d5
d4
d3
d2
d1
d0
RSVD
iout1_scale[5:0]
RSVD
Adjusts IOUT1 full scale
63d = 2A
...
28d = 1A
…
1d = 228.27
0d = 200 mA
RSVD
iout1_scale[5:0]
RSVD
Adjusts IOUT1 full scale when LP_MODE pin is low
63d = 2A
…
1d = 228.27
0d = 200 mA
iout0_msb
iout0_lsb
RSVD
iout0[9:8]
RSVD
IOUT0 MSBs
iout0[7:0]
Default
Type
00111111
R/W
00111111
R/W
00000000
R/W
00000000
R/W
00111111
R/W
00111111
R/W
11111111
R/W
11111111
R/W
11111111
R/W
IOUT0 LSBs
1Ah
1Bh
1Ch
iout0_scale
iout0_scale_LP
RSVD
iout0_scale[5:0]
RSVD
Adjusts IOUT0 full scale
63d = 2A
…
1d = 228.27
0d = 200 mA
RSVD
iout0_scale[5:0]
RSVD
Adjusts IOUT0 full scale when LP_MODE pin is low
63d = 2A
…
1d = 228.27
0d = 200 mA
alarm_th2
alarm_th2[7:0]
Alarm threshold for IOUT2 (output DAC MSB)
1Dh
alarm_th1
alarm_th1[7:0]
Alarm threshold for IOUT1 (output DAC MSB)
1Eh
alarm_th0
alarm_th0[7:0]
Alarm threshold for IOUT0 (output DAC MSB)
36
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
1Fh
RSVD
d7
d6
d5
d4
d3
d2
d1
d0
RSVD
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00011100
R/W
00000000
R/W
00000000
R/W
RSVD
20h
RSVD
RSVD
RSVD
21h
RSVD
RSVD
RSVD
22h
RSVD
RSVD
RSVD
23h
RSVD
RSVD
RSVD
DC-DC converter Control REGISTERS
24h
regref_setup
extr_ctrl
regref_
res2
regref_
res1
regref_mode
1: Use external resistor
for DC-DC
converter
control
1: Cut resistor in half
1: Add
87 kΩ
resistor in
series to
13.7kOhms
resistor
DC-DC converter control
mode
0: Normal
operation
0: Normal
resistor
0: Normal
resistor
pd_dac
Must be set
to 0b if an
external DCDC is being
1: Analog con- controlled:
trol
1: DAC pow0: Digital con- ered down
trol
0: Normal
operation
pd_digapc
idac_current
dig_RC
Must be set
to 0b if
external
DC-DC is
being controlled:
1: Double
full scale
IDAC current to
200 µA
1: Add 1usec
RC filter to
IOUT voltage
when in digital control
mode
0: Normal
1: Compar- operation
(100 µA)
ator and
headroom
reference
powered
down
0: Normal
operation
0: Normal
operation
25h
26h
regref2_dac_MSB
regref2_dac
RSVD
regref2_dac[8]
RSVD
REGREF
DAC output
for IOUT2,
MSB
regref2_dac[7:0]
REGREF DAC output for IOUT2
37
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M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
27h
regref2_ctrl1
28h
regref2_ctrl0
d7
d6
d5
d4
2Ah
d3
d2
d1
d0
headroom2[4:0] (100 mV/Amp, 70 mV min)
regref2_dec[2:0]
Controls headroom for IOUT2
00000: 0 mV
00001:10 mV
00010:20 mV
00011:30 mV
….
11111:310 mV (recommended)
Select decimation factor for REGREF digital loop:
000: 1
001: 2
010: 4
011: 32
100: 64
101: 256
110: 512
111: 2048 (recommended)
update_rate2[2:0]
RSVD
rregrefDAC2_init[1:0]
regref_wait2[1:0]
DAC update rate (12.5 MHz clock cycles)
RSVD
Initial value of DAC output
for IOUT2
01b recommended
Wait states after I_ON
before enabling counting
(IDAC current is fixed to initial value - this is not
impacted by PWM or MPG)
000: No updates
001: 8
010: 512 (recommended)
011: 1024
100: 2048
101: 4096
110: 8192
111: 16374 (equiv. to 1.31 ms)
29h
Rev V4
00: 0
01: previous value
10: value contained in
regref2_dac[8:0]
11: 0
regref1_dac_MSB
regref1_dac
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00: no wait
01: ~20usec
10: ~100usec
11: ~200usec
RSVD
regref1_dac[8]
RSVD
REGREF
DAC output
for IOUT1,
MSB
regref1_dac[7:0]
REGREF DAC output for IOUT1
2Bh
regref1_ctrl1
headroom1[4:0]
regref1_dec[2:0]
Controls headroom for IOUT1
00000: 0 mV
00001:10 mV
00010:20 mV
00011:30 mV
….
11111:310 mV (recommended)
Select decimation factor for REGREF digital loop:
000: 1
001: 2
010: 4
011: 32
100: 64
101: 256
110: 512
111: 2048 (recommended)
38
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
2Ch
regref1_ctrl0
d7
d6
d5
d4
2Eh
d3
d2
d1
d0
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
update_rate1[2:0]
RSVD
rregrefDAC1_init[1:0]
regref_wait1[1:0]
DAC update rate (12.5 MHz clock cycles)
RSVD
Initial value of DAC output
for IOUT1
Wait states after I_ON
before enabling counting
(IDAC current is fixed to initial value - this is not
impacted by PWM or MPG)
000: No updates
001: 8
010: 512
011: 1024
100: 2048
101: 4096
110: 8192
111: 16374 (equiv. to 1.31 ms)
2Dh
Rev V4
00: 0
01: previous value
10: value contained in
regref1_dac[8:0]
11: 0
regref0_dac_MSB
regref0_dac
00: no wait
01: ~20usec
10: ~100usec
11: ~200usec
RSVD
regref0_dac[8]
RSVD
REGREF
DAC output
for IOUT0,
MSB
regref0_dac[7:0]
REGREF DAC output for IOUT0
2Fh
30h
regref0_ctrl1
regref0_ctrl0
headroom0[4:0]
regref0_dec[2:0]
Controls headroom for IOUT0
00000: 0 mV
00001:10 mV
00010:20 mV
00011:30 mV
….
11111:310 mV
Select decimation factor for REGREF digital loop:
000: 1
001: 2
010: 4
011: 32
100: 64
101: 256
110: 512
111: 2048 (recommended)
update_rate0[2:0]
RSVD
rregrefDAC0_init[1:0]
regref_wait0[1:0]
DAC update rate (12.5 MHz clock cycles)
RSVD
Initial value of DAC output
for channel 0
01b recommended
Wait states after I_ON
before enabling counting
(IDAC current is fixed to initial value - this is not
impacted by PWM or MPG)
000: No updates
001: 8
010: 512 (recommended)
011: 1024
100: 2048
101: 4096
110: 8192
111: 16374 (equiv. to 1.31 ms)
00: 0
01: previous value
10: value contained in
regref0_dac[8:0]
11: 0
00: no wait
01: ~20usec
10: ~100usec
11: ~200usec
39
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
31h
alarm_idac2
d7
d6
d5
d4
d3
d2
d1
d0
alarm_th2[7:0]
Default
Type
11111111
R/W
11111111
R/W
11111111
R/W
01111111
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
Alarm threshold for IOUT2 (output DAC MSB)
32h
alarm_idac1
alarm_th1[7:0]
Alarm threshold for IOUT1 (output DAC MSB)
33h
alarm_idac0
alarm_th0[7:0]
Alarm threshold for IOUT0 (output DAC MSB)
APC REGISTERS
34h
apc_ctrl
apc_clk
CPC clock
1: Use external clock
input
(CLK_IN)
0: use internal oscillator
35h
36h
target2_msb
loop_select
apc2_ch
apc1_ch
Selects APC Selects APC input for IOUT2
Selects APC input for
type:
IOUT1
00: APC_IN0
1: CPC
00: APC_IN0
01: APC_IN1
0: IPC
10: APC_IN2
01: APC_IN1
11: disable APC
10: APC_IN2
11: disable APC
apc0_ch
Selects APC input for
IOUT0
00: APC_IN0
01: APC_IN1
10: APC_IN2
11: disable APC
RSVD
target2[12:8]
RSVD
MSB target DAC for gain of IOUT2
target2_lsb
target2[7:0]
LSB target DAC for gain of IOUT2
37h
38h
target1_msb
RSVD
target1[12:8]
RSVD
MSB target DAC for gain of IOUT1
target1_lsb
target1[7:0]
LSB target DAC for gain of IOUT1
39h
3Ah
target0_msb
RSVD
target0[12:8]
RSVD
MSB target DAC for gain of IOUT0
target0_lsb
target0[7:0]
LSB target DAC for gain of IOUT0
3Bh
3Ch
target2_msb_LP
RSVD
target2_LP[12:8]
RSVD
MSB target DAC for gain of IOUT2 when LP_MODE=L
target2_lsb_LP
target2_LP[7:0]
LSB target DAC for gain of IOUT2 when LP_MODE=L
3Dh
3Eh
target1_msb_LP
target1_lsb_LP
RSVD
target1_LP[12:8]
RSVD
MSB target DAC for gain of IOUT1 when LP_MODE=L
target1_LP[7:0]
LSB target DAC for gain of IOUT1 when LP_MODE=L
40
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
3Fh
target0_msb_LP
40h
Rev V4
d7
d6
d5
d4
d3
d2
d1
d0
RSVD
target0_LP[12:8]
RSVD
MSB target DAC for gain of IOUT0 when LP_MODE=L
target0_lsb_LP
target0_LP[7:0]
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
LSB target DAC for gain of IOUT0 when LP_MODE=L
CPC REGISTERS
41h
42h
apc2_ctrl2
apc2_ctrl1
Tck_init2[1:0]
Tck_mid2[1:0]
Tck_min2[1:0]
Tck_div2[1:0]
Initial clock count for IOUT2
00: 0
01: 63
10: 127
11: 255
Mid clock count for IOUT2
00: 0
01: 31
10: 63
11: 127
Clock counts for IOUT2 at
min step
00: 0
01: 31
10: 63
11: 127
Clock counts to enable
clock divider for IOUT2
00: 0
01: 63
10: 127
11: 255
Step_init2[1:0]
Step_mid2[1:0]
iturnon2
ck_div2[1:0]
Initial step size in LSB of
IOUT2
00: 1
01: 8
10: 16
11: 32
43h
apc2_ctrl0
Mid step size in LSB of
IOUT2
00: 1/2 of Step_init
01: 1/4 of Step_init
10: reserved
11: reserved
44h
apc1_ctrl2
00: 1
01: 4
10: 8
11: 16
00: 0
01: previous value
10: value contained in bit
iout2[9:0]
11: 0
Dec2[2:0]
RSVD
line_mode2
Digital filter decimation factor for IOUT2:
RSVD
Line mode for
IOUT2
000: 1
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128
Clock divider for IOUT2
Initial value of IOUT2
1: OUT2 on
only during
CLK_IN=H
0: Ignore
CLK_IN
cpc_wait2[1:0]
apc2_freeze
1: freeze APC
Wait states before
enabling APC (current is for IOUT2
fixed to initial value)
0: normal
operation
00: no wait
01: ~20usec
10: ~100usec
11: ~200usec
Tck_init1[1:0]
Tck_mid1[1:0]
Tck_min1[1:0]
Tck_div1[1:0]
Initial clock count for IOUT1
00: 0
01: 63
10: 127
11: 255
Mid clock count for IOUT1
00: 0
01: 31
10: 63
11: 127
Clock counts for IOUT1 at
min step
00: 0
01: 31
10: 63
11: 127
Clock counts to enable
clock divider for IOUT1
00: 0
01: 63
10: 127
11: 255
41
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
45h
apc1_ctrl1
46h
47h
48h
Rev V4
d7
apc0_ctrl1
d5
d4
d3
d2
d1
d0
Step_init1[1:0]
Step_mid1[1:0]
iturnon1
ck_div1[1:0]
Initial step size in LSB of
IOUT1
00: 1
01: 8
10: 16
11: 32
Mid step size in LSB of
IOUT1
00: 1/2 of Step_init
01: 1/4 of Step_init
10: reserved
11: reserved
Initial value of IOUT1
00: 0
01: previous value
10: value contained in bit
iout1[9:0]
11: 0
Clock divider for IOUT1
00: 1
01: 4
10: 8
11: 16
apc1_ctrl0
apc0_ctrl2
d6
Dec1[2:0]
RSVD
line_mode1
Digital filter decimation factor for IOUT1:
000: 1
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128
RSVD
Line mode for
IOUT1
1: OUT1 on
only during
CLK_IN=H
0: Ignore
CLK_IN
cpc_wait1[1:0]
apc1_freeze
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
1: freeze APC
Wait states before
enabling APC (current is (both gain and
offset) for
fixed to initial value)
IOUT1
00: no wait
: normal oper01: ~20usec
ation
10: ~100usec
11: ~200usec
Tck_init0[1:0]
Tck_mid0[1:0]
Tck_min0[1:0]
Tck_div0[1:0]
Initial clock count for IOUT0
00: 0
01: 63
10: 127
11: 255
Mid clock count for IOUT0
00: 0
01: 31
10: 63
11: 127
Clock counts for IOUT0 at
min step
00: 0
01: 31
10: 63
11: 127
Clock counts to enable
clock divider for IOUT0
00: 0
01: 63
10: 127
11: 255
Step_init0[1:0]
Step_mid0[1:0]
iturnon0
ck_div0[1:0]
Initial step size in LSB of
IOUT0
00: 1
01: 8
10: 16
11: 32
Mid step size in LSB of
IOUT0
00: 1/2 of Step_init
01: 1/4 of Step_init
10: reserved
11: reserved
Initial value of IOUT0
00: 0
01: previous value
10: value contained in bit
iout0[9:0]
11: 0
Clock divider for IOUT0
00: 1
01: 4
10: 8
11: 16
42
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
49h
apc0_ctrl0
d7
d6
d5
d4
d3
d2
Dec0[2:0]
RSVD
line_mode0
Digital filter decimation factor for IOUT0:
000: 1
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128
RSVD
Line mode for
IOUT0
1: OUT0 on
only during
CLK_IN=H
0: Ignore
CLK_IN
d1
cpc_wait0[1:0]
d0
Default
Type
apc0_freeze
00000000
R/W
1: freeze APC
Wait states before
enabling APC (current is (both gain and
offset) for
fixed to initial value)
IOUT0
00: no wait
0: normal
01: ~20usec
operation
10: ~100usec
11: ~200usec
IPC REGISTERS
4Ah
ipc_setup
pfet_test
RSVD
mirror ratio
source_sink
1: Enable
test mode for
pfet mirror
RSVD
1: 1:1 mirroring ratio
1: Current
sinking MPD
(pfet input
stage)
0: Normal
MPD
0: 4x mirroring ratio
0: Normal
operation
4Bh
ipc2_ctrl2
pd_precharge1
pd_precharge0
pre_chrg
1: power
down precharge for
APC_IN2
1: power
down precharge for
APC_IN1
1: power
down precharge for
APC_IN0
1: always ON
0: Normal
operation
0: Normal
operation
0: Normal
operation
pd_comp
RSVD
pd_ihelp2
cap2_sel[3:0]
RSVD
1: Power
down comparator
0: Normal
operation
RSVD
Powers down
100 µA helper
current :
1: Power
down
IPC2 charging capacitor value selector
0000 := 25.0 pF
0001 := 27.5 pF
0010 := 30.0 pF
ipc2_ctrl1
00000000
0: Depends on
channel being
turned on
RSVD
0: Normal
operation
4Ch
pd_precharge2
00000001
R/W
00000000
R/W
.........
.........
1111 := 62.5 pF
RSVD
ipd2_sel[4:0]
RSVD
Peak amplitude monitor photodetector
00000 = 100 µA
00001 = 200 µA
….
11111 = 3.2 mA
43
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
4Dh
ipc2_ctrl0
4Eh
ipc1_ctrl2
d7
d6
50h
51h
ipc0_ctrl2
d3
d2
d1
RSVD
Peak current into IPC2 charging capacitor
00000 = 10 µA
00001 = 20 µA
….
11111 = 320 µA
pd_comp
RSVD
1: Power
down comparator
ipc1_ctrl0
d4
ich2_sel[4:0]
RSVD
ipc1_ctrl1
d5
RSVD
0: Normal
operation
4Fh
Rev V4
hs_sel
pd_ihelp1
cap1_sel[3:0]
1:Increase
comparator bias
current by
66%
Powers down
100 µA helper
current :
1: Power
down
IPC1 charging capacitor value selector
0000 := 25.0 pF
0001 := 27.5 pF
0010 := 30.0 pF
0: Normal
operation
0: Normal
operation
RSVD
Peak amplitude monitor photodetector
00000 = 100 µA
00001 = 200 µA
….
11111 = 3.2 mA
RSVD
ich1_sel[4:0]
RSVD
Peak current into IPC1 charging capacitor
00000 = 10 µA
00001 = 20 µA
….
11111 = 320 µA
RSVD
1: Power
down comparator
0: Normal
operation
Type
00000000
R/W
00000001
R/W
00000000
R/W
00000000
R/W
00000001
R/W
1111 := 62.5 pF
ipd1_sel[4:0]
pd_comp
Default
.........
.........
RSVD
RSVD
d0
hs_sel
pd_ihelp0
cap0_sel[3:0]
1:Increase
comparator bias
current by
66%
Powers down
100 µA helper
current :
1: Power
down
IPC0 charging capacitor value selector
0000 := 25.0 pF
0001 := 27.5 pF
0010 := 30.0 pF
0: Normal
operation
0: Normal
operation
.........
.........
1111 := 62.5 pF
44
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
M08888 Registers
Addr
Register name
52h
ipc0_ctrl1
53h
Rev V4
d7
d6
ipc0_ctrl0
d5
d4
d3
d2
d1
RSVD
ipd0_sel[4:0]
RSVD
Peak amplitude monitor photodetector
00000 = 100 µA
00001 = 200 µA
….
11111 = 3.2 mA
RSVD
ich0_sel[4:0]
RSVD
Peak current into IPC0 charging capacitor
00000 = 10 µA
00001 = 20 µA
….
11111 = 320 µA
d0
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
TIMER REGISTERS
54h
55h
56h
clk_div
pwm_msb
clk_div_pwm[3:0]
clk_div_mpg[3:0]
PWM clock divider
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
MPG clock divider
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
RSVD
on_count2[9:8]
on_count1[9:8]
on_count0[9:8]
RSVD
PWM IOUT2 (msb)
PWM IOUT1 (msb)
PWM IOUT0 (msb)
pwm2
on_count2[7:0]
PWM on count for IOUT2
57h
pwm1
on_count1[7:0]
PWM on count for IOUT1
58h
pwm0
on_count0[7:0]
PWM on count for IOUT0
59h
5Ah
mpg_off_msb
RSVD
pulse_off2[9:8]
pulse_off1[9:8]
pulse_off0[9:8]
RSVD
MPG off IOUT2 (msb)
MPG off IOUT1 (msb)
MPG off IOUT0 (msb)
mpg_off2
pulse_off2[7:0]
MPG pulse off for IOUT2
5Bh
mpg_off1
pulse_off1[7:0]
MPG pulse off for IOUT1
45
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
5Ch
mpg_off0
d7
d6
d5
d4
d3
d2
d1
d0
pulse_off0[7:0]
Default
Type
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00000000
R/W
00h
R/W
00000000
R
00001100
R
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
MPG pulse off for IOUT0
5Dh
5Eh
mpg_on_msb
RSVD
pulse_on2[9:8]
pulse_on1[9:8]
pulse_on0[9:8]
RSVD
MPG on IOUT2 (msb)
MPG on IOUT1 (msb)
MPG on IOUT0 (msb)
mpg_on2
pulse_on2[7:0]
MPG pulse on for IOUT2
5Fh
mpg_on1
pulse_on1[7:0]
MPG pulse on for IOUT1
60h
mpg_on0
pulse_on0[7:0]
MPG pulse on for IOUT0
61h
start_op
RSVD
start_op
RSVD
1b: Start operation
0b: Not operational
Note: M08888
will not be operational until 1b is
written
62h
soft_reset
Soft reset
Writing AA causes a 16 refclk cycles to reset (self clear after reset)
63h
64h
chip_id
Revision identification:
Chip identification
0000
1100
temp
temp[7:0]
Temperature readback
65h
66h
rb_iout2_msb
RSVD
rb_iout2[9:8]
RSVD
Readback IOUT2 DAC MSB
rb_iout2_lsb
rb_iout2[7:0]
Readback IOUT2 DAC LSB
67h
68h
rb_regrefdac2_MSB
rb_regrefdac2
RSVD
rb_regrefdac2[8]
RSVD
Readback of
IOUT2 DAC
rb_regrefdac2[7:0]
Readback of IOUT2 DAC.
69h
rb_iout1_msb
RSVD
rb_iout1[9:8]
RSVD
Readback IOUT1 DAC MSB
46
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
6Ah
rb_iout1_lsb
d7
d6
d5
d4
d3
d2
d1
d0
rb_iout1[7:0]
Default
Type
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
00000000
R
Readback IOUT1 DAC LSB
6Bh
6Ch
rb_regrefdac1_MSB
RSVD
rb_regrefdac1[8]
RSVD
Readback of
IOUT1 DAC
rb_regrefdac1
rb_regrefdac1[7:0]
Readback of IOUT1 DAC.
6Dh
6Eh
rb_iout0_msb
RSVD
rb_iout0[9:8]
RSVD
Readback IOUT0 DAC MSB
rb_iout0_lsb
rb_iout0[7:0]
Readback IOUT0 DAC LSB
6Fh
70h
rb_regrefdac0_MSB
RSVD
rb_regrefdac0[8]
RSVD
Readback of
IOUT0 DAC
rb_regrefdac0
rb_regrefdac0[7:0]
Readback of IOUT0 DAC.
71h
72h
alarm_ctrl
alarm_iout
alarm2
alarm1
alarm0
alarm_IDAC2
alarm_IDAC1
alarm_IDAC0
N/A
N/A
CPC alarm
for IOUT2
Alarm for
IOUT1
Alarm for
IOUT0
Alarm for
IDAC2
Alarm for
IDAC1
Alarm for
IDAC0
N/A
N/A
IPC_overshoot
RSVD
alarm_iout
2
alarm_iout
1
alarm_iout0
Alarm for
high MPD
current
RSVD
Alarm for
open or
short on
IOUT2
Alarm for
open or
short on
IOUT1
Alarm for open
or short on
IOUT0
47
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
73h
RSVD
d7
d6
d5
d4
d3
RSVD
d2
d1
d0
Default
Type
00000000
R/W
00000000
R/W
RSVD
74h
RSVD
RSVD
RSVD
48
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Table 3-1.
Rev V4
M08888 Registers
Addr
Register name
75h
strbalrm_ctrl
d7
d6
d5
d4
d3
d2
RSVD
reg_spl_dis
RSVD
RSVD
Disables register sampling:
RSVD
1: Disable register sampling
(cannot read/
write to any
register
except 68h)
d1
d0
Default
Type
strb_iout
clear_alarm
00000000
R/W
11111111
R/W
1: strobes 1: Clear alam
iout current before 0: Normal
readback
0: Normal
0: Normal
operation (all
registers are
accessible)
80h
alarm_iout_mask
alarm_iout_mask
When 1 masks to 0 alarm bits in alarm_iout
49
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M08888-11
High Performance RGB Driver for DLP/LCD/LCoS Projectors
Rev V4
M/A-COM Technology Solutions Inc. All rights reserved.
Information in this document is provided in connection with M/A-COM Technology Solutions Inc ("MACOM")
products. These materials are provided by MACOM as a service to its customers and may be used for
informational purposes only. Except as provided in MACOM's Terms and Conditions of Sale for such products or
in any separate agreement related to this document, MACOM assumes no liability whatsoever. MACOM assumes
no responsibility for errors or omissions in these materials. MACOM may make changes to specifications and
product descriptions at any time, without notice. MACOM makes no commitment to update the information and
shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its
specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any
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THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, RELATING TO SALE AND/OR USE OF MACOM PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL
DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
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MATERIALS. MACOM SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR
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WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
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using or selling MACOM products for use in such applications do so at their own risk and agree to fully indemnify
MACOM for any damages resulting from such improper use or sale.
50
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support