UT28F256T-40PCC

Standard Products UT28F256 Radiation-Hardened 32K x 8 PROM Data Sheet December 2002 FEATURES q Programmable, read-only, asynchronous, radiationhardened, 32K x 8 memory - Supported by industry standard programmer q 45ns and 40ns maximum address access time (-55 oC to +125 oC) q TTL compatible input and TTL/CMOS compatible output levels q Three-state data bus q Low operating and standby current - Operating: 125mA maximum @25MHz • Derating: 3mA/MHz - Standby: 2mA maximum (post-rad) q Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019 Total dose: 1E6 rad(Si) LETTH (0.25) ~ 100 MeV-cm2/mg SEL Immune >128 MeV-cm 2/mg - Saturated Cross Section cm2 per bit, 1.0E-11 - 1.2E-8 errors/device-day, Adams 90% geosynchronous heavy ion Memory cell LET threshold: >128 MeV-cm 2/mg q QML Q & V compliant part - AC and DC testing at factory q Packaging options: - 28-lead 50-mil center flatpack (0.490 x 0.74) - 28-lead 100-mil center DIP (0.600 x 1.4) - contact factory q V DD : 5.0 volts + 10% q Standard Microcircuit Drawing 5962-96891 PRODUCT DESCRIPTION The UT28F256 amorphous silicon anti-fuse PROM is a high performance, asynchronous, radiation-hardened, 32K x 8 programmable memory device. The UT28F256 PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F256. The combination of radiation-hardness, fast access time, and low power consumption make the UT28F256 ideal for high speed systems designed for operation in radiation environments. A(14:0) DECODER MEMORY ARRAY SENSE AMPLIFIER CE PE OE PROGRAMMING CONTROL LOGIC DQ(7:0) Figure 1. PROM Block Diagram 1 DEVICE OPERATION The UT28F256 has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); fifteen address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. AssertingCE causes I DD to rise to its active value and decodes the fifteen address inputs to select one of 32,768 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs. PIN CONFIGURATION PIN NAMES A(14:0) CE OE PE DQ(7:0) Address Chip Enable Output Enable Program Enable Data Input/Data Output Table 1. Device Operation Truth Table 1 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V DD PE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Notes: 1. “X” is defined as a “don’t care” condition. 2. Device active; outputs disabled. OE X 0 1 1 PE 1 1 0 1 CE 1 0 0 0 I/O MODE Three-state Data Out Data In Three-state MODE Standby Read Program Read 2 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS ) SYMBOL V DD VI/O T STG PD TJ ΘJC II PARAMETER DC supply voltage Voltage on any pin Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case 2 DC input current LIMITS -0.3 to 7.0 -0.5 to (VDD + 0.5) -65 to +150 1.5 +175 3.3 UNITS V V °C W °C °C/W mA ±10 Notes: 1 . Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 . Test per MIL-STD-883, Method 1012, infinite heat sink. 2 RECOMMENDED OPERATING CONDITIONS SYMBOL V DD TC V IN PARAMETER Positive supply voltage Case temperature range DC input voltage LIMITS 4.5 to 5.5 -55 to +125 0 to V DD UNITS V °C V DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V ±10%; -55°C < TC < +125 ° C) SYMBOL V IH VIL V OL1 V OL2 V OH1 V OH2 CIN 1 CIO 1, 4 IIN I OZ PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance (TTL) (TTL) IOL = 4.0mA, V DD = 4.5V (TTL) IOL = 200 µ A, V DD = 4.5V (CMOS) IOH = -200µ A, VDD = 4.5V (CMOS) IOH = -2.0mA, V DD = 4.5V (TTL) ƒ = 1MHz, V DD = 5.0V VIN = 0V ƒ = 1MHz, V DD = 5 .0V VOUT = 0 V Input leakage current Three-state output leakage current VIN = 0V to VDD VO = 0V to V DD VDD = 5.5V OE = 5 .5V VDD = 5.5V, VO = V DD VDD = 5.5V, VO = 0 V TTL inputs levels (IOUT = 0), V IL = 0.2V VDD , PE = 5.5V CMOS input levels VIL = VSS +0.25V CE = VDD - 0.25 VIH = VDD - 0.25V -5 -10 5 10 µA µA VDD -0.1 2.4 15 CONDITION MINIMUM 2.4 0.8 0.4 V SS + 0.10 MAXIMUM UNIT V V V V V V pF Bidirectional I/O capacitance 15 pF IOS 2,3 I DD1 (OP)5 Short-circuit output current 90 -90 mA mA Supply current operating @25.0MHz (40ns product) @22.2MHz (45ns product) Supply current standby 125 117 2 mA mA mA I DD2 (SB) post-rad Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si). 1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. Functional test. 5. Derates at 3.0mA/MHz. 3 READ CYCLE A combination of PE greater than V IH (min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. An address access read is initiated by a change in address inputs while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time. AC CHARACTERISTICS READ CYCLE (Post-Radiation)* (VDD = 5.0V ±10%; -55°C < TC < +125 ° C) SYMBOL tAVAV 1 tAVQV tAXQX 2 tGLQX 2 tGLQV tGHQZ tELQX2 tELQV tEHQZ PARAMETER Read cycle time Read access time Output hold time OE-controlled output enable time OE-controlled access time OE -controlled output three-state time CE -controlled output enable time CE -controlled access time CE-controlled output three-state time The chip enable-controlled access is initiated by CE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A(14:0) appears at the data outputs DQ(7:0). Output enable-controlled access is initiated by OE going active while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or t ELQV have not been satisfied. 28F256-45 MIN MAX 45 45 0 0 15 15 0 45 15 28F256-40 MIN MAX 40 40 0 0 15 15 0 40 15 UNIT ns ns ns ns ns ns ns ns ns Notes: * Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019 at 1E6 rads(Si). 1. Functional test. 2. Three-state is defined as a 400mV change from steady-state output voltage. 4 tAVAV A(14:0) CE tELQX t ELQV OE tGLQV DQ(7:0) t GLQX tAVQV tAXQX tGHQZ t AVQV tEHQZ Figure 2. PROM Read Cycle RADIATION HARDNESS The UT28F256 PROM incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while RADIATION HARDNESS DESIGN SPECIFICATIONS 1 Total Dose Latchup LET Threshold Memory Cell LET Threshold Transient Upset LET Threshold Transient Upset Device Cross Section @ LET=128 MeV-cm2/mg maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. 1E6 >128 >128 54 1E-6 rad(Si) MeV-cm2/mg MeV-cm2/mg MeV-cm2/mg cm 2 Note: 1 . The PROM will not latchup during radiation exposure under recommended operating conditions. 5 330 ohms V REF =1.73V 50pF TTL 3.0V 0V 10% 90% 90% 10% < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (TTL input = 1.5V). < 5ns Figure 3. AC Test Loads and Input Waveforms 6 k 0.015 0.008 PIN NO. 1 ID. 6 k 0.015 0.008 26 PLACES 0.050 BSC e -A- -B- D 0.740 MAX S1 (4) PLACES 0.000 MIN. b 0.022 7 0.015 28 PLACES 0.010 MH A-B SD S 5 E1 0.550 MAX 0.036 MH A-B SD S 5 TOP VIEW E 0.520 0.460 -D7 A 0.115 0.045 c 0.009 0.004 0.040 -CQ 0.045 0.026 L 0.370 0.250 E2 0.180 MIN E3 0.030 MIN -H- Notes: 1. All exposed metalized areas to be plated per MIL-PRF-38535. 2. The lid is connected to V SS . 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Dimension letters refer to MIL-STD-1835. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option. 7. With solder, increase maximum by 0.003. 8. Total weight is approximately 2.4 grams. END VIEW Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74) 7 ORDERING INFORMATION 256K PROM: SMD 5962 * 96891 * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (Y) = 28-pin DIP (contact factory) (X) = 28-lead Flatpack Class Designator: (Q) = Class Q (V) = Class V Device Type (03) = 45ns Access Time, TTL inputs, CMOS/TTL compatible outputs (04) = 40ns Access Time, TTL inputs, CMOS/TTL compatible outputs Drawing Number: 96891 Total Dose: (F) = 3E5 (G) = 5E5 (H) = 1E6 (R) = 1E5 rads(Si) rads(Si) rads(Si) rads(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 4. Check factory for availability of 45ns part. 5. Lead finish: Factory programming either solder or gold. Field programming gold only. 8 256K PROM UT **** *** - * * **** Total Dose: ( ) = Total dose characteristics neither tested nor guaranteed Lead (A) (C) (X) Finish: = Solder = Gold = Optional Screening: (C) = Mil Temp (P) = Prototype Package Type: (P) = 28-lead DIP (contact factory) (U) = 28-lead Flatpack Access Time: (40) = 40ns access time, TTL compatible inputs, CMOS/TTL compatible outputs (45) = 45ns access time, TTL compatible inputs, CMOS/TTL compatible outputs Device Type Modifier: (T) = TTL compatible inputs and CMOS/TTL compatible outputs Device Type: (28F256) = 32Kx8 One Time Programmable PROM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (g old). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. Prototype flow per UTMC Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed and may not be specified. 5. Check factory for availability of 45ns part. 6. Lead finish: Factory programming either solder or gold. Field programming gold only. 9 Notes 10 Notes 11