UT7C139C55WPA

Standard Products UT7C138/139 4Kx8/9 Radiation-Hardened Dual-Port Static RAM with Busy Flag Data Sheet January 2002 FEATURES q 45ns and 55ns maximum address access time q Asynchronous operation for compatibility with industrystandard 4K x 8/9 dual-port static RAM q CMOS compatible inputs, TTL/CMOS compatible output levels q Three-state bidirectional data bus q Low operating and standby current q Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 1.0E6 rads(Si) - Memory Cell LET threshold: 85 MeV-cm2 /mg q q - Latchup immune (LET >100 MeV-cm2 /mg) QML Q and QML V compliant part Packaging options: - 68-lead Flatpack - 68-pin PGA 5-volt operation Standard Microcircuit Drawing 5962-96845 INTRODUCTION The UT7C138 and UT7C139 are high-speed radiationhardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Arbitration schemes are included on the UT7C138/139 to handle situations when multiple processors access the same memory location. Two ports provide independent, asynchronous access for reads and writes to any location in memory. The UT7C138/139 can be utilized as a stand-alone 32/36-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/ slave dual-port static RAM. For applications that require depth expansion, the BUSY pin is open-collector allowing for wired OR circuit configuration. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications, and status buffering. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable ( OE ). BUSY signals that the port is trying to access the same location currently being accessed by the other port. R/W R CE R OER q q R/W L CE L OEL A 11L A 10L I/O 8L ( 7C139) I/O 7L I/O 0L BUSY L A 9L ROW SELECT MEMORY ARRAY ROW SELECT A 11R A 10R I/O8R ( 7C139) COL SEL COLUMN I/O COLUMN I/O COL SEL I/O7R I/O0R BUSY R A 9R A 0L M/S ARBITRATION A 0R Figure 1. Logic Block Diagram N C (2 ) OE R/WL I/O1L I/O0L A10L NC A11L NC CE L NC NC V DD A9L A8L 63 A7L 62 9 8 7 6 5 4 3 2 1 68 67 66 65 64 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VDD GND I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 61 A6L 60 59 58 57 56 55 54 A5L A4L A3L A2L A1L A0L NC BUSYL GND M/S BUSYR NC A0R A1R A2R A3R A4R 7C138/139 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 R/WR I/ O 7 R ( 1) GND Figure 2a. DPRAM Pinout (68-Flatpack) (top view) Notes: 1. I/O8R on the7C139 2. I/O8L on the 7C139 2 A10R A 9R A 8R A 7R A 6R A 5R NC A11R OER CER NC NC NC NC 35 36 37 38 39 40 41 42 43 11 10 9 8 7 6 5 4 3 2 1 B11 A5L A10 B10 A7L A6L A9 B9 A9L A8L A8 B8 A11L A10L A7 B7 VDD NC A6 B6 NC NC A5 B5 NC CEL A4 B4 OEL R/WL A3 B3 I/O0L NC(2) A2 B2 I/O1L I/O2L B1 I/O3L C11 A4L C10 A3L D11 A2L D10 A1L E11 A0L E10 NC F11 BUSYL F10 GND G11 M/S G10 BUSYR H11 NC H10 A0R 7C138/139 C2 I/O4L C1 I/O5L D2 GND D1 I/O6L E2 I/O7L E1 VDD F2 GND F1 I/O0R G2 I/O1R G1 I/O2R K11 A3R K10 A4R K9 A7R K8 A9R K7 A11R K6 GND K5 NC K4 NC K3 OER H2 J2 K2 VDD I/O4R I/O7R H1 J1 K1 I/O3R I/O5R I/O6R J11 A1R J10 A2R L10 A5R L9 A6R L8 A8R L7 A10R L6 NC L5 NC L4 CER L3 R/WR L2 NC(1) A Notes: 1. I/O8R on the7C139 2. I/O8L on the 7C139 B C D E F G H J K L Figure 2b: DPRAM Pinout (68 PGA) (top view) PIN NAMES LEFT PORT I/O0L-7L(8L) A0L-11L CEL OEL R/WL BUSYL M/S VDD GND RIGHT PORT I/O0R-7R(8R) A0R-11R CER OER R/WR BUSYR Data Bus Input/Output Address Lines Chip Enable Output Enable Read/Write Enable Busy Flag Input/Output Master or Slave Select Power Ground DESCRIPTION 3 The UT7C138/139 consists of an array of 4K words of 8 or 9 bits of dual-port SRAM cells, I/O and address lines, and control signals (CE, OE, R/W ). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. With the M/S pin, the UT7C138/139 can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). Each port is provided with its own output enable control (OE), which allows data to be read from the device. WRITE CYCLE A combination of R/W less than VIL (max), and CE less than VIL (max), defines a write cycle. The state of OE is a “don’t care” for a write cycle. The outputs are placed in the highimpedance state when either OE is greater than V IH (min), or when R/W is less than V IL (max). WRITE OPERATION Write Cycle 1, the Write Enable-controlled Access shown in figure 4a, is defined by a write terminated by R/W going high with CE active. The write pulse width is defined by t PWE when the write is initiated by R/W , and by tSCE when the write is initiated by CE going active. Unless the outputs have been previously placed in the high-impedance state by OE, the user must wait tHZOE before applying data to the eight/nine bidirectional pins I/O(0:7/0:8) to avoid bus contention. Write Cycle 2, the Chip Enable-controlled Access shown in figure 4b, is defined by a write terminated byCE going inactive. The write pulse width is defined by tPWE when the write is initiated by R/W , and by tSCE when the write is initiated by CE going active. For the R/W initiated write, unless the outputs have been previously placed in the high-impedance state by OE, the user must wait tHZWE before applying data to the eight/nine bidirectional pins I/O(0:7/0:8) to avoid bus contention. If a location is being written by one port and the opposite port attempts to read that location, a port-to-port flow through delay must be met before the data is read on the output. Data will be valid on the port wishing to read the location (tBZA + t BDD ) after the data is written on the other port (see figure 5a). READ OPERATION When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted (see figures 3a and 3b). MASTER/SLAVE A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation. When presented as a HIGH input, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. When presented as a LOW input, the M/S pin allows the device to be used as a slave, and, therefore, the BUSY pin is an input. Table 1. Non-Contending Read/Write INPUTS CE H X L L L R/W X X H L X OE X H L X X OUTPUTS I/O0-7 High Z High Z Data Out Data In --OPERATION Power Down I/O Lines Disabled Read Write Illegal Condition RADIATION HARDNESS The UT7C138/139 incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. Table 2. Radiation Hardness Design Specifications 1 Total Dose LET Threshold Neutron Fluence2 Memory Device Cross Section @ LET = 120MeV-cm 2/mg 1.0E6 85 3.0E14 < 1.376E -2 (4Kx8) < 1.548E -2 (4Kx9) rads(Si) MeV-cm 2/mg n/cm 2 cm2 Notes: 1. The DPRAM will not latchup during radiation exposure under recommended operating conditions. 2. Not tested for CMOS technology. 4 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS ) SYMBOL V DD V I/O TSTG PD TJ ΘJC II PARAMETER DC supply voltage Voltage on any pin Storage temperature Maximum power dissipation Maximum junction temperature2 Thermal resistance, junction-to-case3 DC input current LIMITS -0.5 to 7.0V -0.5 to (VDD + 0.3)V -65 to +150 ° C 2.0W +150°C 3.3° C/W ±10 mA Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012, infinite heat sink. RECOMMENDED OPERATING CONDITIONS SYMBOL V DD TC V IN PARAMETER Positive supply voltage Case temperature range DC input voltage LIMITS 4.5 to 5.5V -55 to +125° C 0V to V DD 5 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V ±10%; -55°C < TC < +125 ° C) SYMBOL V IH VIL VOL VOL V OH V OH CIN 1 CIO 1 IIN I OZ PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional I/O capacitance Input leakage current Three-state output leakage current (CMOS) (CMOS) IOL = 8mA, V DD = 4.5V (TTL) IOL = 200 µ A, V DD = 4.5V (CMOS) IOH = -4mA, V DD = 4.5V (TTL) IOH = -200µ A, VDD = 4.5V (CMOS) ƒ = 1MHz @ 0V ƒ = 1MHz @ 0V VIN = V DD and VSS VO = VDD and VSS VDD = 5.5V G = 5 .5V IOS 2,3 Short-circuit output current VDD = 5.5V, VO = V DD VDD = 5.5V, VO = 0 V I DD(OP) 4,5 Supply current operating (both ports) @ 22.2MHz I DD(OP) 4,6 Supply current operating (single port) @ 22.2 MHz I DD(OP) 4,5 Supply current operating (both ports) @ 18.2MHz I DD(OP) 4,6 Supply current operating (single port) @ 18.2 MHz I DD (SB)4 Supply current standby CMOS inputs (IOUT = 0 ) VDD = 5.5V CMOS inputs (IOUT = 0 ) VDD = 5.5V CMOS inputs (IOUT = 0 ) VDD = 5.5V CMOS inputs (IOUT = 0 ) VDD = 5.5V CMOS inputs (IOUT = 0 ) CE = VDD - 0 .5, VDD = 5.5V Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. VIH = 5.5V, V IL = 0 V. 5. IDD (OP) derates at 6.4mA/MHz. 6. IDD (OP) derates at 3.4mA/MHz. CONDITION MIN 0.7VDD MAX UNIT V 0.3VDD 0.4 0.05 2.4 4.45 25 25 -10 -10 10 10 V V V V V pF pF µA µA 90 -90 300 mA mA mA 150 mA 275 mA 138 mA 1 mA 6 AC CHARACTERISTICS READ CYCLE 1,2 (VDD = 5.0V±10%) SYMBOL PARAMETER 7C138 - 45 7C139 - 45 MIN MAX 7C138 - 55 7C139 - 55 MIN MAX UNIT tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE Read cycle time Address to data valid2 Output hold from address change CE LOW to data valid2 OE LOW to data valid2 OE LOW to low Z OE HIGH to high Z CE LOW to low Z CE HIGH to high Z 45 45 5 45 20 0 20 0 20 55 55 5 55 20 0 20 0 20 ns ns ns ns ns ns ns ns ns Notes: 1 . Test conditions assume signal transition time of 5ns or less, timing reference levels of V DD /2, input pulse levels of 0.5V to VDD-0.5V, and output loading of the specified IO L/I OH a nd 50-pF load capacitance. 2. AC test conditions use VOH/V OL=V DD/2 + 5 00mV. 7 tRC Address t AA Data Out tOHA Previous Data Valid Assumptions: 1.R/W is HIGH for read cycle 2.Device is continuously selected CE =LOW and OE=LOW Data Valid Figure 3a. Read Cycle 1 CE t ACE t HZCE t DOE tLZOE Data Out t LZCE t HZOE OE Assumptions: 1. Address valid prior to or coincident with CE t ransition LOW 2. R/W is HIGH for read cycle Figure 3b. Read Cycle 2 Address R/WR tWC MATCH tPWE tS D VALID MATCH tHD DataINR AddressL DATAOUTL Assumptions: 1. BUSY = H IGH for the writing port 2. CE L = C ER = LOW tDDD VALID t WDD Figure 3c. Read Timing with Port-to-Port Delay 8 AC CHARACTERISTICS WRITE CYCLE 1 (VDD = 5.0V±10%) SYMBOL PARAMETER 7C138 - 45 7C139 - 45 MIN MAX 7C138 - 55 7C139 - 55 MIN MAX UNIT tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tWDD tDDD tWHWL Write cycle time CE LOW to write end Address set-up to write end Address hold from write end Address set-up to write start Write pulse width Data set-up to write end Data hold from write end R/W LOW to high Z R/W HIGH to low Z Write pulse to data delay Write data valid to read data valid Write disable time 45 40 40 0 0 40 40 0 20 0 95 95 5 55 50 50 0 0 50 50 0 20 0 105 105 5 ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. For information on part-to-part delay through DPRAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform (see figure 3c). 9 tWC Address CE tSCE tAW tHA t PWE t SA t SD DATA V ALID R/ W t HD Data in OE Data out t HZOE HIGH IMPE DANCE tLZOE Assumptions: 1. The internal write time of memory is defined by the overlap of CE LOW and R/W L OW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 2. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (t HZWE + tSD ) to allow the I/O drivers to turn off and data to be placed on the bus for the required t SD . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE . 3. R/W m ust be HIGH during all address transactions. Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port) 10 tWC Address t SCE tAW R/ W tS A tPWE tHA CE t WHWL t SD Data in DATA V ALID t HD tHZWE Data out tLZWE HIGH IMPEDANCE Assumptions: 1. The internal write time of memory is defined by the overlap of C E LOW and R/ W LOW. Both signals must be LOW to initialize a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 2. R/W m ust be HIGH during all address transactions. 3. Data I/O pins enter high impedance even if OE i s held LOW during write. Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port) 11 AC CHARACTERISTICS BUSY CYCLE 1 (VDD = 5.0V±10%) SYMBOL PARAMETER 7C138 - 45 7C139 - 45 MIN MAX 7C138 - 55 7C139 - 55 MIN MAX UNIT tBLA tBZA tBLC tBZC tPS 2,3 tWB tWH tBDD BUSY LOW from address match BUSY HIGH-Z from address mismatch BUSY LOW from CE L OW BUSY HIGH from CE HIGH Port set-up for priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to data valid 5 0 40 25 25 25 25 5 0 50 45 30 30 30 30 ns ns ns ns ns ns ns 55 ns Notes: 1 . Test conditions assume signal transition time of 5ns or less, timing reference levels of V DD /2, input pulse levels of 0.5V to VDD-0.5V, and output loading of the specified IO L/I OH a nd 50-pF load capacitance. 2. Violation of t PS (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy. 3. When violating tPS, the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts. 12 tWC Address R MATCH R/WR tPWE tHD tS D Data InR tPS Address L tBLA BUSYL MATCH VALID tBZA tBDD t DDD DataOUTL Assumptions: 1. CE L = CE R = L OW VALID t WDD Figure 5a. Read Timing with BUSY (M/S=HIGH) R/W tPWE BUSY tWB tWH Figure 5b. Write Timing with BUSY (M/S=LOW) 13 CE L Valid First: AddressL,R ADDRESS MATCH CEL t PS CER BUSYR tBLC t BZC CE R Valid First: AddressL,R ADDRESS MATCH CER CEL t PS BUSYL tBLC tBZC Assumptions: 1. If tPS is violated, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY w ill be asserted. Figure 5c. BUSY Timing Diagram No. 1 (CE Arbitration) 14 Left Address Valid First: t RC or tWC Address L ADDRESS MATCH ADDRESS MISMATCH tPS AddressR t BLA BUSYR tBZA Right Address Valid First: tRC or t WC AddressR ADDRESS MATCH ADDRESS MISMATCH t PS AddressL tBLA t BZA BUSYL Assumptions: 1. If tPS is violated, the BUSY s ignal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. Figure 5d. BUSY Timing Diagram No. 2 (Address Arbitration) 15 DATA RETENTION CHARACTERISTICS (Pre-Radiation) (TC = 25° C) SYMBOL PARAMETER MINIMUM MAXIMUM VDD @ 2.5V -400 UNIT V DR I DDR1 tEFR 1,2 tR1,2 VDD for data retention Data retention current Chip deselect to data retention time Operation recovery time 2.5 -0 tWC or tRC V µA ns ns Notes: 1. CE e quals V DR, a ll other inputs equal V DR o r VSS. 2. Guaranteed but not tested. DATA RETENTION MODE VDR 2.5V 4.5V t EFR 4.5V tR VDD V IN < 1 .5V CMOS VDR CE Figure 6. Low VDD Data Retention Waveform CMOS 460 ohms V DD/2 0.5V 50pF < 5ns Input Pulses < 5ns V DD-0.5V 90% 10% Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (CMOS input = V DD/2). Figure 7. AC Test Loads and Input Waveforms 16 Notes: 1. All package finishes are per MIL-PRF-38535. 2. Letter designations are for cross-reference to MIL-STD-1835. 3. All leads increase max limit by 0.003 measured at the center of the flat, when lead finish A (solder) is applied. 4. ID mark: Configuration is optional. 5. Lettering is not subject to marking criteria. 6. Total weight is approximately 4.5 grams. Figure 8. 68-lead Flatpack 17 L K J H G F E D C B A 11 10 9 8 7 6 5 4 3 2 1 L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 Notes: 1. All packages finishes are per MIL-PRF-38535. 2. True position applies at base plane (Datum C). 3. True position applies at pin tips. 4. Letter designations are for cross-reference to MIL-STD-1835. 5. Total weight is approximately 7.0 grams. Figure 9. 68-pin PGA 18 ORDERING INFORMATION UT7C138/UT7C139 Dual-Port SRAM: SMD 5962 * 96845 * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (X) = 68-pin PGA (Y) = 68-lead Flatpack Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 4Kx8, CMOS Compatible Inputs, 45ns (02) = 4Kx9, CMOS Compatible Inputs, 45ns (03) = 4Kx8, CMOS Compatible Inputs, 55ns (04) = 4Kx9, CMOS Compatible Inputs, 55ns Drawing Number: 96845 Total Dose: (H) = 1E6 rads(Si) (G) = 5E5 rads(Si) (F) = 3E5 rads(Si) (R) = 1E5 rads(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 19 UT7C138/UT7C139 Dual-Port SRAM UT **** *** - * * **** Total Dose: () = None Lead Finish: (A) = Solder (C) = Gold (X) = Optional Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (G) = 68-lead PGA (W) = 68-lead Flatpack Access Time: (45) = 45ns access time (55) = 55ns access time Device Type Modifier: (C) = CMOS-compatible Inputs, 5.0V operation Device Type: (7C138) = 4Kx8 Dual-Port SRAM (7C139) = 4Kx9 Dual-Port SRAM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. Prototypes are produced to UTMC’s prototype flow and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed. Lead finish is GOLD only. 20 UTMC Main Office 4350 Centennial Blvd. Colorado Springs, CO 80907-3486 800-MIL-UTMC 800-645-8862 http://www.utmc.com European Sales Office 1+719-594-8166 1+719-594-8468 FAX http://www.utmc.com Boston Sales Office 40 Mall Road, Suite 203 Burlington, MA 01830 781-221-4122 Melbourne Sales Office 1901 S. Harbor City Blvd., Suite 802 Melbourne, FL 32901 407-951-4164 South LA Sales Office 101 Columbia Street, Suite 130 Aliso Viejo, CA 92656 714-362-2260 UTMC Microelectronic Systems Inc. (UTMC) reserves the right to make changes to any products and services herein at any time without notice. Consult UTMC or an authorized sales representative to verify that the information in this data sheet is current before using this product. UTMC does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by UTMC; nor does the purchase, lease, or use of a product or service from UTMC convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of UTMC or of third parties. Copyright 1996 & 1997 by UTMC Microelectronic Systems Inc. DUALPORT-2-12-97 All rights reserved