UT7R995-XPX

Standard Products UT7R995 & UT7R995C RadClockTM RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer Datasheet February, 2007 FEATURES: +3.3V Core Power Supply +2.5V or +3.3V Clock Output Power Supply - Independent Clock Output Bank Power Supplies Output frequency range: 6 MHz to 200 MHz Bank pair output-output skew < 100 ps Cycle-cycle jitter < 50 ps 50% ± 2% maximum output duty cycle at 100MHz Eight LVTTL outputs with selectable drive strength Selectable positive- or negative-edge synchronization Selectable phase-locked loop (PLL) frequency range and lock indicator Phase adjustments in 625 to 1300 ps steps up to ± 7.8 ns (1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios Compatible with Spread-Spectrum reference clocks Power-down mode Selectable reference input divider Radiation performance - Total-dose tolerance: 100 krad (Si) - SEL Immune to a LET of 109 MeV-cm2/mg - SEU Immune to a LET of 109 MeV-cm2/mg Military temperature range: -55oC to +125oC Extended industrial temp: -40oC to +125oC Packaging options: - 48-Lead Ceramic Flatpack Standard Microcircuit Drawing: 5962-05214 - QML-Q and QML-V compliant part The devices also feature split output bank power supplies that enable banks 1 & 2, bank 3, and bank 4 to operate at a different power supply levels. The ternary PE/HD pin controls the synchronization of output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers. The UT7R995 and UT7R995C both interface to a digital clock while the UT7R995C will also interface to a quartz crystal. INTRODUCTION: The UT7R995/UT7R995C is a low-voltage, low-power, eightoutput, 6-to-200 MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance microprocessor and communication systems. The user programs both the frequency and the phase of the output banks through nF[1:0] and DS[1:0] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Connect any one of the outputs to the feedback input to achieve different reference frequency multiplication and division ratios. 4F0 4F1 sOE PD/DIV PE/HD VDD VDDQ3 3Q1 3Q0 VSS VSS VDD FB VDD VSS VSS 2Q1 2Q0 VDDQ1 LOCK VSS DS0 DS1 1F0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 UT7R995 & UT7R995C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3F1 3F0 FS VSS VSS VDDQ4 4Q1 4Q0 VSS VSS VDD XTAL1 NC/XTAL2 VDD VSS VSS 1Q1 1Q0 VDDQ1 VSS TEST 2F1 2F0 1F1 Figure 1. 48-Lead Ceramic Flatpack Pin Description 1 TEST PE/HD FS VDDQ1 PD/DIV XTAL1 3 3 /R 3 3 LOCK NC/XTAL2 PLL /N 3 DS[1:0] 3 1F[1:0] 3 3 FB 1Q0 Phase Select 1Q1 3 2F[1:0] 3 Phase Select 2Q0 2Q1 3 3F[1:0] 3 Phase Select and /K 3Q0 3Q1 VDDQ3 3 4F[1:0] 3 Phase Select and /M 4Q0 4Q1 VDDQ4 Figure 2. UT7R995 & UT7R995C Block Diagram sOE 2 1.0 DEVICE CONFIGURATION: The outputs of the UT7R995/C can be configured to run at frequencies ranging from 6 MHz to 200 MHz. Each output bank has the ability to run at separate frequencies and with various phase skews. Furthermore, numerous clock division and multiplication options exist. The following discussion and list of tables will summarize the available configuration options for the UT7R995/C. Tables 1 through 12, are relevant to the following configuration discussions. Table 1. Feedback Divider Settings (N-factor) Table 2. Reference Divider Settings (R-Factor) Table 3. Output Divider Settings - Bank 3 (K-factor) Table 4. Output Divider Settings - Bank 4 (M-Factor) Table 5. Frequency Divider Summary Table 6. Calculating Output Frequency Settings Table 7. Frequency Range Select Table 8. Multiplication Factor (MF) Calculation Table 9. Signal Propagation Delays in Various Media Table 10: Output Skew Settings Table 11. PE/HD Settings Table 12. Power Supply Constraints 1.1 Divider Configuration Settings: The feedback input divider is controlled by the 3-level DS[1:0] pins as indicated in Table 1 and the reference input divider is controlled by the 3-level PD/DIV pin as indicated in Table 2. Although the Reference divider will continue to operate when the UT7R995/C is in the standard TEST mode of operation, the Feedback Divider will not be available. Table 1: Feedback Divider Settings (N-factor) DS[1:0] LL LM LH ML MM MH HL HM HH Table 2: Reference Divider Settings (R-factor) PD/DIV LOW 1 MID HIGH Operating Mode Powered Down Normal Operation Normal Operation Reference Input Divider - (R) Not Applicable 2 1 Notes: 1. When PD/DIV = LOW, the device enters power-down mode. In addition to the reference and feedback dividers, the UT7R995/C includes output dividers on Bank 3 and Bank 4, which are controlled by 3F[1:0] and 4F[1:0] as indicated in Tables 3 and 4, respectively. Table 3: Output Divider Settings - Bank 3 (K-factor) 3F(1:0) LL HH Other 1 Bank 3 Output Divider - (K) 2 4 1 Notes: 1. These states are used to program the phase of the respective banks. Please see Equation 1 along with Tables 8 and 10. Table 4: Output Divider Settings - Bank 4 (M-factor) 4F[1:0] LL Other 1 Bank 4 Output Divider (M) 2 1 Feedback Input Divider - (N) 2 3 4 5 1 6 8 10 12 Permitted Output Divider (K or M) Connected to FB 1 or 2 1 1, 2, or 4 1 or 2 1, 2, or 4 1 or 2 1 or 2 Notes: 1. These states are used to program the phase of the respective banks. Please see Equation 1 along with Tables 8 and 10. Each of the four divider options and their respective settings are summarized in Table 5. By applying the divider options in Table 5 to the calculations shown in Table 6, the user determines the proper clock frequency for every output bank. Table 5: Frequency Divider Summary Division Factors N Available Divider Settings 1, 2, 3, 4, 5, 6, 8, 10, 12 1, 2 1, 2, 4 1, 2 1 R 1 K M 3 Table 6: Calculating Output Frequency Settings Configuration Clock Output Connected to FB 1Qn or 2Qn 3Qn 4Qn Output Frequency 1Q[1:0] 1 and 2Q[1:0] 1 3Q[1:0] 4Q[1:0] (N/R) * fXTAL (N/R) * K * fXTAL (N/R) * M * fXTAL (N/R) * (1/K) * fXTAL (N/R) * fXTAL (N/R) * (M/K) * fXTAL (N/R) * (1/M) * fXTAL (N/R) * (K/M) * fXTAL (N/R) * fXTAL Notes: 1. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the nominal VCO operating frequency (fNOM) at a given reference frequency (fXTAL) and the divider and feedback configuration. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Please see Table 7. 1.2 Frequency Range and Skew Selection: The PLL in the UT7R995/C operates within three nominal frequency ranges. Depending upon the desired PLL operating frequency, the user must define the state of the ternary FS control pin. Table 7 defines the required FS selections based upon the nominal PLL operating frequency ranges. Because the clock outputs on Bank 1 and Bank 2 do not include a divider option, they will always reflect the current frequency of the PLL. Reference the first column of equations in Table 6 to calculate the value of fNOM for any given feedback clock. Table 7: Frequency Range Select FS L M H After calculating the time unit (tU) based on the nominal PLL frequency (fNOM) and multiplication factor (MF), the circuit designer plans routing requirements of each clock output and its respective destination receiver. With an understanding of signal propagation delays through a conductive medium (see Table 9), the designer specifies trace lengths which ensure a signal propagation delay that is equal to one of the tU multiples show in Table 10. For each output bank, the tU skew factors are selected with the tri-level, bank-specific, nF[1:0] pins. Table 8: MF Calculation FS L M H MF 32 16 8 Nominal PLL Frequency Range (fNOM) 24 to 50 MHz 48 to 100MHz 96 to 200 MHz fNOM examples that result in a tU of 1.0ns 31.25 MHz 62.5 MHz 125 MHz Selectable output skew is in discrete increments of time unit (tU). The value of tU is determined by the FS setting and the PLL’s operating frequency (fNOM). Use the following equation to calculate the time unit (tU): Equation 1. t = 1 (f NOM * MF) Table 9: Signal Propagation Delays in Various Media Medium Air (Radio Waves) Coax. Cable (75% Velocity) Coax. Cable (66% Velocity) FR4 PCB, Outer Trace FR4 PCB, Inner Trace Alumina PCB, Inner Trace Propagation Dielectric Delay (ps/inch) Constant 85 113 129 140 - 180 180 240 - 270 1.0 1.8 2.3 2.8 - 4.5 4.5 8 - 10 u The fNOM term, which is calculated with the help of Table 6, must be compatible with the nominal frequency range selected by the FS signal as defined in Table 7. The multiplication factor (MF), also determined by FS, is shown in Table 8. The UT7R995/C output skew steps have a typical accuracy of +/15% of the calculated time unit (tU). 4 Table 10: Output Skew Settings4 nF[1:0] LL 1, 2 LM LH ML MM MH HL HM HH 2 Skew 1Q[1:0], 2Q[1:0] -4tU -3tU -2tU -1tU Zero Skew +1tU +2tU +3tU +4tU Skew 3Q[1:0] Divide by 2 -6tU -4tU -2tU Zero Skew +2tU +4tU +6tU Divide by 4 Skew 4Q[1:0] Divide by 2 -6tU -4tU -2tU Zero Skew +2tU +4tU +6tU Inverted 3 A graphical summary of Table 10 is shown in Figure 3. The drawing assumes that the FB input is driven by a clock output programmed with zero skew. Depending upon the state of the nF[1:0] pins the respective clocks will be skewed, divided, or inverted relative to the fedback output as shown in Figure 3. 1.3 Output Drive, Synchronization, and Power Supplies: The UT7R995/C employs flexible output buffers providing the user with selectable drive strengths, independent power supplies, and synchronization to either edge of the reference input. Using the 3-level PE/HD pin, the user selects the reference edge synchronization and the output drive strength for all clock outputs. The options for edge synchronization and output drive strength selected by the PE/HD pin are listed in Table 11. Table 11: PE/HD Settings PE/HD Synchronization Output Drive Strength 1 L M H Negative Positive Positive Low Drive High Drive Low Drive Notes: 1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH. 2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversionoptions function as defined in Table 9. 3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these outputs HIGH when PE/HD = HIGH or MID, sOE disables them LOW when PE/HD = LOW. 4. Skew accuracy is within +/- 15% of n*tU where "n" is the selected number of skew steps. Supplied as a design limit, but not tested or guaranteed. Notes: 1. Please refer to "DC Parameters" section for IOH/IOL specifications. XTAL1 Input FB Input 1F[1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) (N/A) 2F[1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) (N/A) 3F[1:0] LM LH (N/A) ML (N/A) MM (N/A) MH (N/A) HL HM LL/HH (N/A) 4F[1:0] LM LH (N/A) ML (N/A) MM (N/A) MH (N/A) HL HM LL HH -6tU -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU +6tU DIVIDED INVERTED Figure 3. Typical Outputs with FB Connected to a Zero-Skewed Output 5 t0 - 5tU t0 - 4tU t0 - 3tU t0 - 2tU t0 - 1tU t0 t0 + 1tU t0 + 2tU t0 + 3tU t0 + 4tU t0 + 5tU t0 + 6tU t0 - 6tU When the outputs are configured for low drive operation, they will provide a minimum 12mA of drive current regardless of the selected output power supply. If the outputs are configured for high drive operation, they will provide a minimum 24mA of drive current under a 3.3V power supply and 20mA when powered from a 2.5V supply. The UT7R995/C features split power supply buses for Banks 1 and 2, Bank 3, and Bank 4. These independent power supplies enable the user to obtain both 3.3V and 2.5V output signals from one UT7R995/C device. The core power supply (VDD) must run from a 3.3V power supply. Table 12 summarizes the various power supply options available with the UT7R995/C. Table 12: Power Supply Constraints 1 VDD 3.3V UT7R995C XTAL1 XTAL2 R1 Rdc Y1 L1 VDDQ1 3.3V or 2.5V VDDQ3 3.3V or 2.5V VDDQ4 3.3V or 2.5V C2 C1 Cdc Notes: 1. VDDQ1/3/4 must not be set at a level higher than that of VDD. Fundamental Frequency Pierce Crystal Oscillator Rdc = ~10MΩ; L1 = Not Used; Cdc = Not Used C2 is used to tune the circuit for stable oscillation. Typical values for C2 range from 30pF to 50pF. R1 and C1 are selected to create a time constant that facilitates the fundamental frequency (fF) of the quartz crystal as defined in equation 2. 1.4 Reference Clock Interfaces When an external, LVCMOS/LVTTL, digital clock is used to drive the UT7R995 and UT7R995C, the reference clock signal should drive the XTAL1 input of the RadClock, while the XTAL2 output should be left unconnected (see Figure 4). Note, for the UT7R995 only, the XTAL2 pin is defined as a noconnect. N/C External Digital Oscillator NC/XTAL2 Equation 2. fF = 1 (2π * R1* C1) As an example, selecting a value of 100Ω for R1 and 80pF for C1 would facilitate the reliable operation of a 20MHz, AT-cut, quartz crystal. Higher Frequency Pierce Crystal Oscillator Rdc = ~10MΩ; Cdc = ~1.5nF; C2 = Tuning capacitor similar to prior example XTAL1 R1 and C1 are selected to create a time constant that facilitates the overtone frequency (fOT) of the quartz crystal as shown in equation 3. VSS Equation 3. f OT = (2π * R1* C1) 1 Figure 4. External Digital Clock Oscillator Interface In addition to a digital clock reference, the UT7R995C can interface to a quartz crystal. When interfacing to a quartz crystal, XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier within the RadClock. This inverting amplifier provides the initial 180o phase shift of the reference clock whose frequency, and subsequent 180o phase shift, is set by the quartz crystal and its surrounding RLC network. Figure 5 shows a typical pierce-oscillator with tank-circuit that will support reliable startup of fundamental and odd-harmonic, ATcut, quartz crystals. Additionally, L1 is selected such that its relationship with C1 facilitates a frequency falling between the fundamental frequency (fF) and the specified overtone frequency (fOT) of the quartz crystal as shown in equation 4. Equation 4. fM = (2π * 1 L1* C1 ) As an example, selecting the following component values will result in a 50MHz Pierce Crystal Oscillator based upon an 3rd overtone, AT-cut, quartz crystal having a fundamental frequency of 16.6666MHz. Rdc = 10MΩ; R1 = 50Ω; fF = 16.6666MHz; Cdc = 1.5nF; C1 = 55pF; fOT = 50MHz C2 = 30pF; L1 = 300nH Figure 5. Pierce Crystal Oscillator with Tank Circuit 6 2.0 RADIATION HARDNESS Table 13: Radiation Hardness Design Specifications Parameter Total Ionizing Dose (TID) Single Event Latchup (SEL) 1, 2 Onset Single Event Upset (SEU) LET Threshold 3, 4 Onset Single Event Transient (SET) LET Threshold (@ 50MHz; FS=L)5 Neutron Fluence Limit >1E6 >109 >109 >74 1.0E14 Units rads(Si) MeV-cm2/mg MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. The UT7R995/C are latchup immune to particle LETs >109 MeV-cm2/mg. 2. Worst case temperature and voltage of TC = +125oC, VDD = 3.6V, VDDQ1/Q3/Q4 = 3.6V for SEL. 3. Worst case temperature and voltage of TC = +25oC, VDD = 3.0V, VDDQ1/Q3/Q4 = 3.0V for SEU. 4. All SEU data specified in this datasheet is based on the storage elements used in the UT7R995/C. 5. For characterization data on the UT7R995/C SET performance over allowable operating ranges, please contact the factory. 3.0 PIN DESCRIPTION Flatpack Pin No. Name I/O Type Description Primary reference clock input. When interfacing a single-ended reference clock to the UT7R995 or UT7R995C, this input must be driven by an LVTTL/LVCMOS clock source. 37 XTAL1 I LVTTL If a quartz crystal is used as the reference clock source (UT7R995C only), the second pin on the crystal must be connected to XTAL2. If a singled ended reference clock is supplied to this pin, then XTAL2 should be left unconnected. N/C 36 XTAL2 -- -- No Connect. UT7R995 Only. Feedback output from the on-board crystal oscillator. When a crystal is used to supply the reference clock for the UT7R995C, this pin must be connected to the second terminal of the quartz crystal. If a single-ended reference clock is supplied to XTAL1, then this output should be left unconnected. Feedback input for the PLL. When FB is not driven by an active clock output the PLL will run to its maximum frequency, unless the device is placed in power-down. O N/A 13 FB TEST 1 I LVTTL 28 I Built-in test control signal. When Test is set to the MID or HIGH level, it disables 3-Level the PLL and the XTAL1 reference frequency is driven to all outputs (except for the conditions described in note 1). Set Test LOW for normal operation. 7 Flatpack Pin No. Name I/O Type Description Synchronous Output Enable. The sOE input is used to synchronously enable/ disable the output clocks. Each clock output that is controlled by the sOE pin is synchronously enabled/disabled by the individual output clock. When HIGH, sOE disables all clocks except 2Q0 and 2Q1. When disabled, 1Q0, 1Q1, 3Q0, and 3Q1 will always enter a LOW state when PE/HD is MID or HIGH, and they will disable into a HIGH state when PE/HD is LOW. The disabled state of 4Q0 and 4Q1 is dependent upon the state of PE/HD and 4F[1:0]. The following table illustrates the disabled state of bank 4 outputs as they are controlled by the state of PE/HD and 4F[1:0]. PE/HD 4F[1:0]* 4Q0 4Q1 LOW HH LOW LOW MID HH HIGH HIGH HIGH HH HIGH HIGH *All other combinations of 4F[1:0] will result in 4Q0 and 4Q1 disabling into a LOW state when PE/HD is MID or HIGH, and they will disable into a HIGH state when PE/HD is LOW. 3 sOE I LVTTL When TEST is held at the MID level and sOE is HIGH, the nF[1:0] pins act as individual output enable/disable controls for each output bank, excluding bank 2. Setting both nF[1:0] signals LOW disables the corresponding output bank. Set sOE LOW to place the UT7R995/C RadClockTM outputs into their normal operating modes. 1, 2, 24, 25, 26, 27, 47, 48 46 8, 9, 17, 18, 31, 32, 41, 42 22, 23 nF[1:0] I Output divider and phase skew selection for each output bank. 3-Level Please see Tables 3, 4, 5, 6, and 9 for a complete explanation of the nF[1:0] control functions and their effects on output frequency and skew. FS I 3-Level VCO operating frequency range selection. Please see Tables 7 and 8. Four clock banks of two outputs each. Please see Table 6 for frequency settings and Table 9 for skew settings. Feedback input divider selection. Please see Table 1 for a summary of the feedback input divider settings. Positive/negative edge control and high/low output drive strength selection. The PE portion of this pin controls which edge of the reference input synchronizes the clock outputs. The HD portion of this pin controls the drive strength of the output clock buffers. The following table summarizes the effects of the PE/HD pin during normal operation. nQ[1:0] O LVTTL DS[1:0] I 3-Level 5 PE/HD I 3-Level PE/HD LOW MID HIGH Synchronization Negative Edge Positive Edge Positive Edge Output Drive Strength Low Drive High Drive Low Drive Low drive strength outputs provide 12mA of drive strength while the high drive condition results in 24mA of current drive. Output banks operating from a 2.5V power supply guarantee a high drive of 20mA. 8 Flatpack Pin No. Name I/O Type Description Power down and reference divider control. This dual function pin controls the power down operation and selects the input reference divider. Holding the pin low during power up ensures clean RadClock startup that is independent of the behavior of the reference clock. The pin may also be driven low at any time to force a reset to the PLL. The following table summarizes the operating states controlled by the PD/DIV pin. PD/DIV LOW MID HIGH Operating Mode Powered Down Normal Operation Normal Operation Input Reference Divider N/A ÷2 4 PD/DIV I 3-Level ÷1 PLL lock indication signal. A HIGH state indicates that the PLL is in a locked condition. A LOW state indicates that the PLL is not locked and the outputs may not be synchronized to the input. As the following table indicates, the level of phase alignment between XTAL1 and FB that will cause the LOCK pin to change states is dependent upon the frequency range selected by the FS input. FS L M H LOCK Resolution 1.6ns typical 1.6ns typical 800ps typical 20 LOCK O LVTTL ** Note: The LOCK pin can only be considered as a valid output when the RadClock is in a normal mode of operation (e.g. PD/DIV != LOW, TEST = LOW, and a valid reference clock is supplied to the XTAL1 input). Until these conditions are met, RadClock is not in a normal operating mode and the LOCK pin may be HIGH or LOW and therefore should not be used in making any logical decisions until the device is in a normal operating mode. Reference the tLOCK parameter in the AC timing specification to determine the delay for the LOCK pin to become valid HIGH following a stable input reference clock and the application of a clock to the FB input. 43 7 19, 30 6, 12, 14, 35, 38 10, 11, 15, 16, 21, 29, 33, 34, 39, 40, 44, 45 VDDQ4 2 VDDQ3 2 VDDQ1 2 VDD 2 PWR PWR PWR PWR Power Power Power Power Power supply for Bank 4 output buffers. Please see Table 12 for supply level constraints. Power supply for Bank 3 output buffers. Please see Table 12 for supply level constraints. Power supply for Bank 1 and Bank 2 output buffers. Please see Table 12 for supply level constraints. Power supply for internal circuitry. Please see Table 12 for supply level constraints. VSS PWR Power Ground Notes: 1. When TEST = MID and sOE = HIGH, the PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 2. A bypass capacitor (0.1μF) should be placed as close as possible to each positive power pin (