FW802BF

Data Sheet January 2005 ™ FW802BF Low-Power PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Distinguishing Features Compliant with IEEE® Standard 1394a-2000, IEEE Standard for a High Performance Serial Bus Amendment 1. Low power consumption during powerdown or microlow-power sleep mode. Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders. While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port. Does not require external filter capacitors for PLL. Does not require a separate 5 V supply for 5 V link controller interoperability. Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies. Interoperable with 1394 link-layer controllers using 5 V supplies. 1394a-2000 compliant common mode noise filter on incoming TPBIAS. Powerdown features to conserve energy in batterypowered applications include the following: — Device powerdown ball. — Link interface disable using LPS. — Inactive ports power down. — Automatic microlow-power sleep mode during suspend. Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation. ™ Supports PHY pinging and remote PHY access packets. Fully supports suspend/resume. Supports PHY-link interface initialization and reset. Supports 1394a-2000 register set. Supports LPS/link-on as a part of PHY-link interface. Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus. Fully interoperable with FireWire ® and i.LINK ® implementations of IEEE 1394-1995. Reports cable power fail interrupt when voltage at CPS ball falls below 7.5 V. Provides separate cable bias and driver termination voltage supply for each port. Other Features 48-ball VTFSBGAC package. Single 3.3 V supply operation. Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s. 25 MHz crystal oscillator and PLL provide a 50 MHz link-layer controller clock as well as transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. Multiple separate package signals provided for analog and digital supplies and grounds. Description Features Provides two fully compliant cable ports at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. Fully supports 1394 Open HCI requirements. Supports arbitrated short bus reset to improve utilization of the bus. Supports ack-accelerated arbitration and fly-by concatenation. Supports connection debounce. Supports multispeed packet concatenation. The Agere Systems FW802BF device provides the analog physical layer functions needed to implement a two-port node in a cable-based IEEE 13941995 and IEEE 1394a-2000 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PHY is designed to interface with a linklayer controller (LLC). FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Table of Contents Contents Data Sheet January 2005 Page Distinguishing Features ............................................................................................................................................ 1 Features ................................................................................................................................................................... 1 Other Features .........................................................................................................................................................1 Description ................................................................................................................................................................ 1 Ball Information ........................................................................................................................................................ 6 Signal Information ..................................................................................................................................................... 7 Application Information ........................................................................................................................................... 11 Crystal Selection Considerations ............................................................................................................................ 12 Load Capacitance ............................................................................................................................................ 13 Adjustment to Crystal Loading ......................................................................................................................... 13 Crystal/Board Layout ....................................................................................................................................... 13 Absolute Maximum Ratings .................................................................................................................................... 14 Electrical Characteristics ........................................................................................................................................ 15 Timing Characteristics ............................................................................................................................................ 18 Timing Waveforms .................................................................................................................................................. 19 Internal Register Configuration ............................................................................................................................... 20 Outline Diagrams .................................................................................................................................................... 25 48-Ball TFSBGAC ............................................................................................................................................ 25 Ordering Information ............................................................................................................................................... 25 List of Figures Figures Page Figure 1. Block Diagram ........................................................................................................................................... 5 Figure 2. FW802BF Ball Diagram (48-Ball TFSBGAC) Top View ............................................................................ 6 Figure 3. Typical External Component Connections .............................................................................................. 11 Figure 4. Typical Port Termination Network .......................................................................................................... 12 Figure 5. Crystal Circuitry ....................................................................................................................................... 13 Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ............................................................. 19 Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms....................................................................... 19 List of Tables Tables Page Table 1. FW802BF (48-Ball TFSBGAC) Ball Coordination Table ............................................................................ 6 Table 2. Signal Descriptions..................................................................................................................................... 7 Table 3. Absolute Maximum Ratings ...................................................................................................................... 14 Table 4. Analog Characteristics .............................................................................................................................. 15 Table 5. Driver Characteristics ............................................................................................................................... 16 Table 6. Device Characteristics .............................................................................................................................. 17 Table 7. Switching Characteristics ......................................................................................................................... 18 Table 8. Clock Characteristics ............................................................................................................................... 18 Table 9. PHY Register Map for the Cable Environment ........................................................................................ 20 Table 10. PHY Register Fields for the Cable Environment .................................................................................... 20 Table 11. PHY Register Page 0: Port Status Page ............................................................................................... 22 Table 12. . PHY Register Port Status Page Fields ................................................................................................ 23 Table 13. PHY Register Page 1: Vendor Identification Page ............................................................................... 24 Table 14. PHY Register Vendor Identification Page Fields ................................................................................... 24 2 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device tion to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. This monitor is called bias-detect. The TPBIAS circuit monitors the value of incoming TPA pair common-mode voltage when local TPBIAS is inactive. Because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. This monitor is called connect-detect. Both the TPB bias-detect monitor and TPBIAS connect-detect monitor are used in suspend/resume signaling and cable connection detection. The PHY provides a 1.86 V nominal bias voltage for driver load termination. When seen through a cable by a remote receiver, this bias voltage indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 V or 3 V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 µF. The transmitter circuitry, the receiver circuitry, and the twisted-pair bias voltage circuity are all disabled with a powerdown condition. The powerdown condition occurs when the PD input is high. The port transmitter circuitry, the receiver circuitry, and the TPBIAS output are also disabled when the port is disabled, suspended, or disconnected. The line drivers in the PHY operate in a high-impedance current mode and are designed to work with external 112 Ω line-termination resistor networks. One network is provided at each end of each twisted-pair cable. Each network is composed of a pair of seriesconnected 56 Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A (TPA) signals is connected to the TPBIAS voltage signal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB) signals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 kΩ and 220 pF, respectively. The value of the external resistors are specified to meet the IEEE 1394 standard specifications when connected in parallel with the internal receiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between the R0 and R1 signals and has a value of 2.49 kΩ ± 1%. Description (continued) The PHY requires either an external 24.576 MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL) that generates the required 393.216 MHz reference signal. The 393.216 MHz reference signal is internally divided to provide the 49.152 MHz, 98.304 MHz, and 196.608 MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152 MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The powerdown function, when enabled by the PD signal high, stops operation of the PLL and disables all circuitry except the cable-not-active (CNA) signal circuitry. The PHY supports an isolation barrier between itself and its LLC. When ISON is tied high, the link interface outputs behave normally. When ISON is tied low, internal differentiating logic is enabled, and the outputs become short pulses that can be coupled through a capacitor or transformer as described in the IEEE 1394-1995 Annex J. To operate with bus-keeper isolation, the ISON ball of the FW802BF must be tied high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPA and TPB cable pair(s). During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled and the receivers for that port are enabled. The encoded data information is received on the TPA and TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two (for S100), four (for S200), or eight (for S400) parallel streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitraAgere Systems Inc. 3 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. Note: All gap counts on all nodes of a 1394 bus must be identical. The software accomplishes this by issuing PHY configuration packets (see Section 4.3.4.3 of the IEEE 1394a-2000 standard) or by issuing two bus resets, which resets the gap counts to the maximum level (3Fh). The link power status (LPS) signal works with the C_LKON signal to manage the LLC power usage of the node. The LPS signal indicates that the LLC of the node is powered up or powered down. If LPS is inactive for more than 1.2 ms and less than 25 ms, the PHY/link interface is reset. If LPS is inactive for greater than 25 ms, the PHY will disable the PHY/link interface to save power. FW802BF continues its repeater function even when the PHY/link interface is disabled. If the PHY then receives a link-on packet, the C_LKON signal is activated to output a 6.114 MHz signal that can be used by the LLC to power itself up. Once the LLC is powered up, the LPS signal communicates this to the PHY and the PHY/link interface is enabled. The C_LKON signal is turned off when LPS is active or when a bus reset occurs, provided the interrupt that caused C_LKON is not present. When the PHY/link interface is in the disabled state, the FW802BF will automatically enter a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the FW802BF disables its PLL and also disables parts of its reference circuitry depending on the state of the ports (some reference circuitry must remain active in order to detect incoming TP bias). The lowest power consumption (the microlow-power sleep mode) is attained when all ports are either disconnected or disabled with the ports interrupt enable bit (see Table 12) cleared. The FW802BF will exit the low-power mode when the LPS input is asserted high or when a port event occurs that requires the FW802BF to become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias or disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). When the FW802BF is in the low-power mode, the SYSCLK output will become active (and the PHY/link interface will be initialized and become operative) within 3 ms after LPS is asserted high. Two of the FW802BF’s signals are used to set up various test conditions used only during the device manufacturing process. These signals (SE and SM) should be connected to VSS for normal operation. Description (continued) The FW802BF supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows an FW802BF port to be put into a suspended state. In this state, a port is unable to transmit or receive data packets, however, it remains capable of detecting connection status changes and detecting incoming TPBias. When all ports of the FW802BF are suspended, all circuits except the bias voltage reference generator, and bias detection circuits are powered down, resulting in significant power savings. The use of suspend/resume is recommended. As an input, the C_LKON signal indicates whether a node is a contender for bus manager. When the C_LKON signal is asserted, it means the node is a contender for bus manager. When the signal is not asserted, it means that the node is not a contender. The C bit corresponds to bit 20 in the self-ID packet (see Section 4.3.4.1 of the IEEE 1394a-2000 standard for additional details). The power-class (Pwr_class) bits of the self-ID packet have a default value of 0, i.e., power-class 000. These bits can be read and modified through the LLC using Figure 5B-1 (PHY Register Map) and Section 4.3.4.1 of the IEEE 1394a-2000 standard. See Table 9 of this document for the address space of the Pwr_class register. A powerdown signal (PD) is provided to allow a powerdown mode where most of the PHY circuits are powered down to conserve energy in battery-powered applications. The internal logic in FW802BF is reset as long as the powerdown signal is asserted. A cable status signal (CNA) provides a high output when none of the twisted-pair cable ports are receiving incoming bias voltage. This output is not debounced. The CNA output can be used to determine when to power the PHY down or up. In the powerdown mode, all circuitry is disabled except the CNA circuitry. It should be noted that when the device is powered down, it does not act in a repeater mode. When the power supply of the PHY is removed while the twisted-pair cables are connected, the PHY transmitter and receiver circuitry is designed to present a high impedance to the cable in order to not load the TPBIAS signal voltage on the other end of the cable. Whenever the TBA±/TPB± signals are wired to a connector, they must be terminated using the normal termination network (See Figure 4.). This is required for reliable operation. For those applications, when one of the FW802BF’s ports is not wired to a connector, those unused ports may be left unconnected 4 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Description (continued) CPS LPS ISON CNA SYSCLK LREQ CTL[0] CTL[1] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] LINK INTERFACE I/O TPA[0] TPAN[0] ARBITRATION AND CONTROL STATE MACHINE LOGIC RECEIVED DATA DECODER/ RETIMER BIAS VOLTAGE AND CURRENT GENERATOR R[0] R[1] TPBIAS[0] CABLE PORT 0 TPB[0] TPBN[0] C_LKON SE SM PD TPA[1] TPAN[1] TPBIAS[1] TPB[1] TPBN[1] RESETN TRANSMIT DATA ENCODER CABLE PORT 1 CRYSTAL OSCILLATOR, PLL SYSTEM, AND CLOCK GENERATOR XI XO 5-5459.f (F) r.3 Figure 1. Block Diagram Agere Systems Inc. 5 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Ball Information A1 BALL PAD CORNER 1 A B C D E F G H 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 A B C D E F G H Note: Refer to the outline drawing on page 25 for a bottom view. 5-8117 Figure 2. FW802BF Ball Diagram (48-Ball TFSBGAC) Top View Table 1. FW802BF (48-Ball TFSBGAC) Ball Coordination Table Ball Number A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 Ball Name CTL[0] LREQ SYSCLK XO XI VSS R[0] TPBIAS[1] CTL[1] RESETN VSSPLL VDDPLL Ball Number B5 B6 B7 B8 C1 C2 C7 C8 D1 D2 D7 D8 Ball Name VDD R[1] VSSA TPA[1] D[1] D[0] VDDA TPAN[1] D[2] VDD TPBIAS[0] TPB[1] Ball Number E1 E2 E7 E8 F1 F2 F7 F8 G1 G2 G3 G4 Ball Name D[5] D[3] SE TPBN[1] D[7] D[4] VSSA TPA[0] LPS D[6] VSS C_LKON Ball Number G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 Ball Name VSS VSS VDDA TPAN[0] CNA VDD PD ISON CPS SM TPB[0] TPBN[0] 6 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Signal Information Table 2. Signal Descriptions Ball Number G4 Signal* C_LKON Type I/O Name/Description Bus Manager Capable Input and Link-On Output. On hardware reset (RESETN), this ball is used to set the default value of the contender status indicated during self-ID. The bit value programming is done by tying the signal through a 10 kΩ resistor to VDD (high, bus manager capable) or to GND (low, not bus manager capable). Using either the pull-up or pulldown resistor allows the link-on output to override the input value when necessary. After hardware reset, this ball is set as an output. If the LPS is inactive, C_LKON indicates one of the following events by asserting a 6.114 MHz signal. 1. FW802BF receives a link-on packet addressed to this node. 2. Port_event register bit is 1. 3. Any of the Timeout, Pwr_fail, or Loop register bits are 1 and the Watchdog register bit is also 1. 4. Once activated, the C_LKON output will continue active until the LPS becomes active. The PHY also deasserts the C_LKON output when a 1394 bus reset occurs, if the C_LKON is active due solely to the reception of a link-on packet. Note: If an interrupt condition exists which would otherwise cause the C_LKON output to be activated if the LPS were inactive, the C_LKON output will be activated when the LPS subsequently becomes inactive. H1 CNA O Cable-Not-Active Output. CNA is asserted high when none of the PHY ports are receiving an incoming bias voltage. This circuit remains active during the powerdown mode. Cable Power Status. CPS is normally connected to the cable power through a 400 kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in one internal register and is available to the LLC by way of a register read (see Table 9, address register 00002, bit 7/PS). In applications that do not sink or source 1394 power (VP), this ball can be tied to ground. Note: When this ball is grounded, the Pwr_fail bit in PHY register 01012 will be set. A1 B1 C1, C2, D1, E1, E2, F1, F2, G2 CTL[0] CTL[1] D[0:7] I/O I/O Control I/O. The CTLn signals are bidirectional communications control signals between the PHY and the LLC. These signals control the passage of information between the two devices. Bus-keeper circuitry is built into these terminals. Data I/O. The Dn signals are bidirectional and pass data between the PHY and the LLC. Bus-keeper circuitry is built into these terminals. H5 CPS I * Active-low signals are indicated by “N” at the end of signal names, within this document. Agere Systems Inc. 7 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Signal Information (continued) Table 2. Signal Descriptions (continued) Ball Number H4 Signal* ISON Type I Name/Description Link Interface Isolation Disable Input (Active-Low). ISON controls the operation of an internal pulse differentiating function used on the PHY-LLC interface signals, CTLn and Dn, when they operate as outputs. When ISON is asserted low, the isolation barrier is implemented between PHY and its LLC (as described in Annex J of IEEE 1394-1995). ISON is normally tied high to disable isolation differentiation. Bus-keepers are enabled when ISON is high (inactive) on CTLn, Dn, and LREQ. When ISON is low (active), the bus-keepers are disabled. Please refer to Agere’s application note, 1394 Isolation (AP05-014CMPR), for more information. Link Power Status. LPS is connected to either the VDD supplying the LLC or to a pulsed output that is active when the LLC is powered for the purpose of monitoring the LLC power status. If LPS is inactive for more than 1.2 µs and less than 25 µs, the PHY-link interface is reset. If LPS is inactive for greater than 25 µs, the PHY will disable the PHY/link interface to save power. FW802BF continues its repeater function. Link Request. LREQ is an output from the LLC that requests the PHY to perform some service. Bus-keeper circuitry is built into this terminal. Powerdown. When asserted high, PD turns off all internal circuitry except the bias-detect circuits that drive the CNA signal. Internal FW802BF logic is kept in the reset state as long as PD is asserted. The PD terminal is provided for backward compatibility. It is recommended that the FW802BF be allowed to manage its own power consumption using suspend/resume in conjunction with LPS. C_LKON features are defined in the IEEE 1394a2000 specification. Power for PLL Circuit. VDDPLL supplies power to the PLL circuitry portion of the device. Ground for PLL Circuit. VSSPLL is tied to a low-impedance ground plane. Current Setting Resistor. An internal reference voltage is applied to a resistor connected between R0 and R1 to set the operating current and the cable driver output current. A low temperature-coefficient resistor (TCR) with a value of 2.49 kΩ ± 1% should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. Reset (Active-Low). When RESETN is asserted low (active), a 1394 bus reset condition is set on the active cable ports and the FW802BF is reset to the reset start state. To guarantee that the PHY will reset, this ball must be held low for at least 2 ms. An internal pull-up resistor connected to VDD is provided so that only an external delay capacitor (0.1 µF) and resistor (510 kΩ) in parallel, are required to connect this ball to ground. This circuitry will ensure that the capacitor will be discharged when PHY power is removed. The input is a standard logic buffer and can also be driven by an open-drain logic output buffer. Do not leave this ball unconnected. Test Mode Control. SE is used during Agere’s manufacturing test and should be tied to VSS for normal operation. G1 LPS I A2 H3 LREQ PD I I B4 B3 A7 B6 B2 VDDPLL VSSPLL R[0] R[1] RESETN — — I I E7 SE I * Active-low signals are indicated by “N” at the end of signal names, within this document. 8 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Signal Information (continued) Table 2. Signal Descriptions (continued) Ball Number H6 A3 F8 G8 Signal* SM SYSCLK TPA[0] TPAN[0] Type I O Name/Description Test Mode Control. SM is used during Agere’s manufacturing test and should be tied to VSS for normal operation. System Clock. SYSCLK provides a 49.152 MHz clock signal, which is synchronized with the data transfers to the LLC. Analog I/O Port0, Port Cable Pair A. TPA0± is the port A connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. When the FW802BF’s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog I/O Port1, Port Cable Pair A. TPA1± is the port A connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. When the FW802BF’s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog I/O Port0, Port Cable Pair B. TPB0± is the port B connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. When the FW802BF’s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog I/O Port1, Port Cable Pair B. TPB1± is the port B connection to the twistedpair cable. Board traces from each pair of positive and negative differential signal balls should be kept as short as possible and matched to the external load resistors and to the cable connector. When the FW802BF’s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog I/O Portn, Twisted-Pair Bias. (Where n refers to the port number) TPBIAS provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW802BF’s 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. — Digital Power. VDD supplies power to the digital portion of the device. B8 C8 TPA[1] TPAN[1] H7 H8 TPB[0] TPBN[0] D8 E8 TPB[1] TPBN[1] D7 A8 TPBIAS[0] TPBIAS[1] B5, D2, H2 VDD * Active-low signals are indicated by “N” at the end of signal names, within this document. Agere Systems Inc. 9 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Signal Information (continued) Table 2. Signal Descriptions (continued) Ball Number C7, G7 A6, G3, G5, G6 B7, F7 A5 Signal* VDDA VSS VSSA XI Type — — — — Name/Description Analog Circuit Power. VDDA supplies power to the analog portion of the device. Digital Ground. All VSS signals should be tied to the low-impedance ground plane. Analog Circuit Ground. All VSSA signals should be tied together to a lowimpedance ground plane. Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant fundamental mode crystal. Although, when a 24.576 MHz clock source is used, it can be connected to XI with XO left unconnected. The optimum values for the external load capacitors and resistor are dependent on the specifications of the crystal used. It is necessary to add an external series resistor (RL) to the XO pin (see Figures 3 and 5). For more details, refer to the Crystal Selection Considerations section in this data sheet. Note that it is very important to place the crystal as close as possible to the XO and XI pins, i.e., within 0.5 in./1.27 cm. A4 XO * Active-low signals are indicated by “N” at the end of signal names, within this document. 10 10 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Application Information 24.576 MHz 0.1 µF 510 kΩ CL CL 2.49 kΩ LLC LLC RL A1 BALL PAD CORNER CTL[0] LREQ SYSCL XO XI VSS R[0] TPBIAS[1] CTL[1 RESET VSSPLL VDDPLL VDD R[1] VSSA TPA[1] D[1] LLC LLC D[2] LLC D[5] LLC D[7] LLC D[0] VDDA TPAN[1] PORT 1* VDD TPBIAS[0] TPB[1] PORT 0* AGERE FW802BF D[3] SE TPBN[1] D[4] VSS TPA[0] LCC PULSE OR VDD LPS D[6] VSS C_LKON VSS VSS VDDA TPAN[0] PORT 0* CNA VDD PD ISON CPS SM TPB[0] TPBN[0] 400 kΩ * See Figure 4 for typical port termination network. Figure 3. Typical External Component Connections Agere Systems Inc. CABLE POWER PORT 0* 11 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Application Information (continued) A8 B8 C8 D8 E8 D7 F8 TPBIAS[1] TPA[1] TPAN[1] USE SAME PORT TERMINATION NETWORK AS ILLUSTRATED BELOW. TPB[1] TPBN[1] TPBIAS[0] 0.33 µF TPBIAS[1] 56 Ω TPA[0] TPAN[0] 56 Ω G8 5 6 IEEE 1394-1995 STANDARD CONNECTOR 3 56 Ω 5 kΩ 4 H7 TPB[0] TPBN[0] H8 56 Ω 220 pF 1 2 VP CABLE POWER VG 5-6930 (F) Figure 4. Typical Port Termination Network Crystal Selection Considerations The FW802BF is designed to use an external 24.576 MHz parallel resonant fundamental mode crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394a-2000 standard requires that FW802BF have less than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm. 12 12 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Crystal Selection Considerations (continued) Load Capacitance The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also capacitances from the FW802BF board traces and capacitances of the other FW802BF connected components. The values for load capacitors (CA and CB) should be calculated using this formula: CA = CB = (CL – Cstray) × 2 CA XI RL XO A CB Where: CL = load capacitance specified by the crystal manufacturer. Cstray = capacitance of the board and the FW802BF, typically 2 pF—3 pF. RL = load resistance; the value of RL is dependent on the specific crystal used. Please refer to your crystal manufacturer’s data sheet and application notes to determine an appropriate value. Figure 5. Crystal Circuitry Adjustment to Crystal Loading The resistor (RL) in Figure 5 is recommended for fine-tuning the crystal circuit. The value for this resistor is dependent on the specific crystal used. Please refer to your crystal manufacturer’s data sheet and application notes to determine an appropriate value for RL. A more precise value for this resistor can be obtained by placing different values of RL on a production board and using an oscilloscope to view the resultant clock waveform at node A for each resistor value. The desired waveform should have the following characteristics: the waveform should be sinusoidal, with an amplitude as large as possible, but not greater than 3.3 V or less than 0 volts. Crystal/Board Layout The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing noise introduced into the FW802BF PLL. The crystal and two load capacitors (CA + CB) should be considered as a unit during layout. They should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals. 1394 Application Support Contact Information E-mail: support1394@agere.com Agere Systems Inc. 13 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 3. Absolute Maximum Ratings Parameter Supply Voltage Range Input Voltage Range* Output Voltage Range at Any Output Operating Free Air Temperature Storage Temperature Range Symbol VDD VI VO TA Tstg Min 3.0 –0.5 –0.5 0 –65 Max 3.6 VDD + 0.5 VDD + 0.5 70 150 Unit V V V °C °C * Except for 5 V tolerant I/O (CTL0, CTL1, D0—D7, and LREQ) where VI max = 5.5 V. 14 14 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Electrical Characteristics Table 4. Analog Characteristics Parameter Supply Voltage Differential Input Voltage Test Conditions Source power node Cable inputs, 100 Mbits/s operation Cable inputs, 200 Mbits/s operation Cable inputs, 400 Mbits/s operation Cable inputs, during arbitration TPB cable inputs, speed signaling off TPB cable inputs, S100 speed signaling on TPB cable inputs, S200 speed signaling on TPB cable inputs, S400 speed signaling on TPB cable inputs, speed signaling off TPB cable inputs, S100 speed signaling on TPB cable inputs, S200 speed signaling on TPB cable inputs, S400 speed signaling on TPA, TPB cable inputs, 100 Mbits/s operation TPA, TPB cable inputs, 200 Mbits/s operation TPA, TPB cable inputs, 400 Mbits/s operation Between TPA and TPB cable inputs, 100 Mbits/s operation Between TPA and TPB cable inputs, 200 Mbits/s operation Between TPA and TPB cable inputs, 400 Mbits/s operation — Symbol VDD—SP VID—100 VID—200 VID—400 VID—ARB VCM VCM—SP—100 VCM—SP—200 VCM—SP—400 VCM VCM—NSP—100 VCM—NSP—200 VCM—NSP—400 — — — — — — VTH+ Min 3.0 142 132 100 168 1.165 1.165 0.935 0.532 1.165 1.165 0.935 0.532 — — — — — — 89 Typ 3.3 — — — — — — — — — — — — — — — — — — — Max 3.6 260 260 260 265 2.515 2.515 2.515 2.515 2.015 2.015 2.015 2.015 1.08 0.5 0.315 0.8 0.55 0.5 168 Unit V mV mV mV mV V V V V V V V V ns ns ns ns ns ns mV Common-mode Voltage Source Power Mode Common-mode Voltage Nonsource Power Mode* Receive Input Jitter Receive Input Skew Positive Arbitration Comparator Input Threshold Voltage Negative Arbitration Comparator Input Threshold Voltage Speed Signal Input Threshold Voltage Output Current TPBIAS Output Voltage Current Source for Connect Detect Circuit — VTH− –168 — –89 mV 200 Mbits/s 400 Mbits/s TPBIAS outputs At rated I/O current — VTH—S200 VTH—S400 IO VO ICD 45 266 –5 1.665 — — — — — — 139 445 2.5 2.015 76 mV mV mA V µA * For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard). Agere Systems Inc. 15 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Electrical Characteristics (continued) Table 5. Driver Characteristics Parameter Differential Output Voltage Off-state Common-mode Voltage Driver Differential Current, TPA, TPAN, TPB, TPBN Common-mode Speed Signaling Current, TPB, TPBN Test Conditions 56 Ω load Drivers disabled Driver enabled, speed signaling off* 200 Mbits/s speed signaling enabled† 400 Mbits/s speed signaling enabled† Symbol VOD VOFF IDIFF ISP ISP Min 172 — −1.05 −2.53 −8.1 Typ — — — — — Max 265 20 1.05 −4.84 −12.4 Unit mV mV mA mA mA * Limits are defined as the algebraic sum of TPA and TPAN driver currents. Limits also apply to TPB and TPBN as the algebraic sum of driver currents. † Limits are defined as the absolute limit of each of TPB and TPBN driver currents. 16 16 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Electrical Characteristics (continued) Table 6. Device Characteristics Parameter Supply Current: One Port Active All Ports Active No Ports Active, (Microlowpower Sleep Mode) LPS = 0 PD = 1 High-level Output Voltage Low-level Output Voltage High-level Input Voltage Low-level Input Voltage Pull-up Current, RESETN Input Powerup Reset Time, RESETN Input Rising Input Threshold Voltage RESETN Input Output Current Test Conditions VDD = 3.3 V IDD IDD IDD IDD IOH max, VDD = min IOL min, VDD = max CMOS inputs CMOS inputs VI = 0 V VI = 0 V — SYSCLK Control, data CNA C_LKON Input Current, LREQ, LPS, PD, SE, SM, PC[0:2] Inputs Off-state Output Current, CTL[0:1], D[0:7], C_LKON I/Os Power Status Input Threshold Voltage, CPS Input Rising Input Threshold Voltage*, LREQ, CTLn, Dn Falling Input Threshold Voltage*, LREQ, CTLn, Dn Bus Holding Current, LREQ, CTLn, Dn Rising Input Threshold Voltage LPS Falling Input Threshold Voltage LPS VI = VDD or 0 V VOH VOL VIH VIL II — VIRST IOL/IOH @ TTL IOL/IOH @ CMOS IOL/IOH IOL/IOH II — — — — VDD – 0.4 — 0.7 VDD — 11 2 1.1 –16 –12 –16 –2 — 54 74 50 50 — — — — — — — — — — — — — — — — — 0.4 — 0.2 VDD 32 — 1.4 16 12 16 2 °±1 mA mA µA µA V V V V µA ms V mA mA mA mA µA Symbol Min Typ Max Unit VO = VDD or 0 V 400 kΩ resistor — — VI = 1/2(VDD) — — IOZ VTH VIT+ VIT− — VLIH VLIL — 7.5 VDD/2 + 0.3 VDD/2 – 0.8 250 — 0.24 VDD + 0.2 — — — — — — — °±5 8.5 VDD/2 + 0.8 VDD/2 – 0.3 550 0.24 VDD + 1 — µA V V V µA V V * Device is capable of both differentiated and undifferentiated operation. Agere Systems Inc. 17 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Timing Characteristics Table 7. Switching Characteristics Symbol — — tr tf tsu th td Parameter Jitter, Transmit Transmit Skew Rise Time, Transmit (TPA/TPB) Fall Time, Transmit (TPA/TPB) Setup Time, Dn, CTLn, LREQ↑↓ to SYSCLK↑ Hold Time, Dn, CTLn, LREQ↑↓ from SYSCLK↑ Delay Time, SYSCLK↑ to Dn, CTLn↑↓ Measured TPA, TPB Between TPA and TPB 10% to 90% 90% to 10% 50% to 50% 50% to 50% 50% to 50% Test Conditions — — R I = 56 Ω , CI = 10 pF R I = 56 Ω , CI = 10 pF See Figure 6. See Figure 6. See Figure 7. Min — — — — 6 0 1 Typ — — — — — — — Max 0.15 ±0.1 1.2 1.2 — — 6 Unit ns ns ns ns ns ns ns Table 8. Clock Characteristics Parameter External Clock Source Frequency Symbol f Min 24.5735 Typ 24.5760 Max 24.5785 Unit MHz 18 18 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Timing Waveforms SYSCLK th tsu Dn, CTLn, LREQ 5-6017.a (F) Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms SYSCLK td Dn, CTLn 5-6018.a (F) Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms Agere Systems Inc. 19 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Internal Register Configuration The PHY register map is shown below in Table 9. (Refer to IEEE 1394a-2000, 5B.1 for more information.) Table 9. PHY Register Map for the Cable Environment Address Bit 0 00002 00012 00102 00112 01002 01012 01102 01112 10002 LCtrl Watchdog RHB IBR Extended (7) Max_speed Contender ISBR Loop Bit 1 Bit 2 Contents Bit 3 Bit 4 Bit 5 Bit 6 R Gap_count Bit 7 PS Physical_ID XXXXX XXXXX Jitter Pwr_fail Timeout Total_ports Delay Pwr_class Port_event Enab_accel Enab_multi XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX Page_select Port_select XXXXX Register 0 Page_select 11112 Register 7 Page_select REQUIRED XXXXX RESERVED The meanings of the register fields within the PHY register map are defined by Table 10 below. Power reset values not specified are resolved by the operation of the PHY state machines subsequent to a power reset. Table 10. PHY Register Fields for the Cable Environment Field Physical_ID Size Type 6 r Power Reset Value 000000 Description The address of this node determined during self-identification. A value of 63 indicates a malconfigured bus; the link will not transmit any packets. When set to one, indicates that this node is the root. Cable power active. Root hold-off bit. When set to one, the force_root variable is TRUE, which instructs the PHY to attempt to become the root during the next tree identify process. Initiate bus reset. When set to one, instructs the PHY to set ibr TRUE and reset_time to RESET_TIME. These values in turn cause the PHY to initiate a bus reset without arbitration; the reset signal is asserted for 166 µs. This bit is self-clearing. Used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. See Section 4.3.6 of IEEE Standard 1394a-2000 for the encoding of this field. This field has a constant value of seven, which indicates the extended PHY register map. Agere Systems Inc. R PS RHB 1 1 1 r r rw 0 — 0 IBR 1 rw 0 Gap_count 6 rw 3F16 Extended 20 20 3 r 111 Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Internal Register Configuration (continued) Table 10. PHY Register Fields for the Cable Environment (continued) Field Total_ports Max_speed Size Type Power Reset Value 4 3 r r 0010 010 Description The number of ports implemented by this PHY. This count reflects the number. Indicates the speed(s) this PHY supports: 0002 = 98.304 Mbits/s 0012 = 98.304 and 196.608 Mbits/s 0102 = 98.304, 196.608, and 393.216 Mbits/s 0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s 1002 = 98.304, 196.608, 393.216, 786.432, and 1,572.864 Mbits/s 1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 Mbits/s All other values are reserved for future definition. Worst-case repeater delay, expressed as 144 + (delay * 20) ns. Link active. Cleared or set by software to control the value of the L bit transmitted in the node’s self-ID packet 0, which will be the logical AND of this bit and LPS active. Cleared or set by software to control the value of the C bit transmitted in the self-ID packet. Powerup reset value is set by C_LKON ball. The difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. Power class. Controls the value of the pwr field transmitted in the self-ID packet. See Section 4.3.4.1 of IEEE Standard 1394a-2000 for the encoding of this field. When set to one, the PHY will set Port_event to one if resume operations commence for any port. Initiate short (arbitrated) bus reset. A write of one to this bit instructs the PHY to set ISBR true and reset_time to SHORT_RESET_TIME. These values in turn cause the PHY to arbitrate and issue a short bus reset. This bit is self-clearing. Loop detect. A write of one to this bit clears it to zero. Cable power failure detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. Arbitration state machine timeout. A write of one to this bit clears it to zero (see MAX_ARB_STATE_TIME). Port event detect. The PHY sets this bit to one if any of connected, bias, disabled, or fault change for a port whose Int_enable bit is one. The PHY also sets this bit to one if resume operations commence for any port and Watchdog is one. A write of one to this bit clears it to zero. Delay LCtrl 4 1 r rw 0000 1 Contender 1 rw See description. Jitter Pwr_class 3 3 r rw 000 000 Watchdog ISBR 1 1 rw rw 0 0 Loop Pwr_fail Timeout Port_event 1 1 1 1 rw rw rw rw 0 1 0 0 Agere Systems Inc. 21 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Internal Register Configuration (continued) Table 10. PHY Register Fields for the Cable Environment (continued) Field Enab_accel Size Type 1 rw Power Reset Value 0 Description Enable arbitration acceleration. When set to one, the PHY will use the enhancements specified in Section 4.4 of 1394a-2000 specification. PHY behavior is unspecified if the value of Enab_accel is changed while a bus request is pending. Enable multispeed packet concatenation. When set to one, the link will signal the speed of all packets to the PHY. Selects which of eight possible PHY register pages are accessible through the window at PHY register addresses 10002 through 11112, inclusive. If the page selected by Page_select presents per-port information, this field selects which port’s registers are accessible through the window at PHY register addresses 10002 through 11112, inclusive. Ports are numbered monotonically starting at zero, p0. Enab_multi Page_select 1 3 rw rw 0 000 Port_select 4 rw 0000 The port status page is used to access configuration and status information for each of the PHY’s ports. The port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address 01112. The format of the port status page is illustrated by Table 11 below; reserved fields are shown shaded. The meanings of the register fields with the port status page are defined by Table 12. Table 11. PHY Register Page 0: Port Status Page Address Bit 0 10002 10012 10102 10112 11002 11012 11102 11112 AStat Negotiated_speed Bit 1 Bit 2 BStat Int_enable Contents Bit 3 Bit 4 Child Fault Bit 5 Connected Bit 6 Bias Bit 7 Disabled XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX REQUIRED XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX RESERVED XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX 22 22 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Internal Register Configuration (continued) the meanings of the register fields with the port status page are defined by Table 12 below. Table 12. PHY Register Port Status Page Fields Field AStat Size Type 2 r Power Reset Value — Description TPA line state for the port: 002 = invalid 012 = 1 102 = 0 112 = Z TPB line state for the port (same encoding as AStat). If equal to one, the port is a child; otherwise, a parent. The meaning of this bit is undefined from the time a bus reset is detected until the PHY transitions to state T1: Child Handshake during the tree identify process (see Section 4.4.2.2 in IEEE Standard 1394-1995). If equal to one, the port is connected. If equal to one, incoming TPBIAS is detected. If equal to one, the port is disabled. Indicates the maximum speed negotiated between this PHY port and its immediately connected port; the encoding is the same as for they PHY register Max_speed field. Enable port event interrupts. When set to one, the PHY will set Port_event to one if any of connected, bias, disabled, or fault (for this port) change state. Set to one if an error is detected during a suspend or resume operation. A write of one to this bit clears it to zero. BStat Child 2 1 r r — 0 Connected Bias Disabled Negotiated_speed 1 1 1 3 r r rw r 0 0 0 000 Int_enable 1 rw 0 Fault 1 rw 0 Agere Systems Inc. 23 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Data Sheet January 2005 Internal Register Configuration (continued) The vendor identification page is used to identify the PHY’s vendor and compliance level. The page is selected by writing one to Page_select in the PHY register at address 01112. The format of the vendor identification page is shown in Table 13; reserved fields are shown shaded. Table 13. PHY Register Page 1: Vendor Identification Page Address Bit 0 10002 10012 10102 10112 11002 11012 11102 11112 Product_ID Vendor_ID Bit 1 Bit 2 Contents Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Compliance_level XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX REQUIRED XXXXX RESERVED The meanings of the register fields within the vendor identification page are defined by Table 14. Table 14. PHY Register Vendor Identification Page Fields Field Compliance_level Size Type 8 r Description Standard to which the PHY implementation complies: 0 = not specified 1 = IEEE 1394a-2000 Agere’s FW802BF compliance level is 1. All other values reserved for future standardization. The company ID or organizationally unique identifier (OUI) of the manufacturer of the PHY. Agere’s vendor ID is 00601D16. This number is obtained from the IEEE registration authority committee (RAC). The most significant byte of Vendor_ID appears at PHY register location 10102 and the least significant at 11002. The meaning of this number is determined by the company or organization that has been granted Vendor_ID. Agere’s FW802BF product ID is 08020116. The most significant byte of Product_ID appears at PHY register location 11012 and the least significant at 11112. Vendor_ID 24 r Product_ID 24 r The vendor-dependent page provides access to information used in manufacturing test of the FW802BF. 24 Agere Systems Inc. Data Sheet January 2005 FW802BF PHY 1394a-2000 Two-Cable Transceiver/Arbiter Device Outline Diagrams 48-Ball VTFSBGAC Dimensions are in millimeters. TOP VIEW BOTTOM VIEW PKG TYPE FSBGA TFSBGA DETAIL A VTFSBGA A B C 0.36 REF 0.70 ± 0.05 1.28 ± 0.18 0.21 REF 0.70 ± 0.05 1.13 ± 0.13 0.21 REf 0.45 ± 0.03 0.88 ± 0.10 Note: 1. GLOBAL PLANE IS BEST FIT PLANE AS DETERMINED BY COPLANARITY MEASUREMENT EQUIPMENT. 2. THIS PACKAGE CONFIGURATION HAS SOLDER MASK DEFINED BGA PADS (SMD). FOR DETAILS SEE INDIVIDUAL SUBSTRATE DRAWINGS (BOTTOM VIEW). 3. THE SOLDER BALL DIAMETER BEFORE REFLOW = 0.30 mm +0.10/-0.05 mm. Ordering Information Device Code FW802BF-09-DB Package 48-ball VTFSBGAC Comcode 700050786 Agere Systems Inc. 25 The i.LINK logo is a trademark and i.LINK is a registered trademark of Sony Corporation. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. The FireWire logo is a trademark and FireWire is a registered trademark of Apple Computer, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6741-9855, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. All Rights Reserved January 2005 DS05-046CMPR (Replaces DS03-081CMPR-2)