T8110L

Data Sheet February 2004 Ambassador ® T8110L H.100/H.110 Switch 1 Introduction The T8110L is the newest addition to the Ambassador series of TDM switching and backlane interconnect standard products. The T8110L can switch 4096 simultaneous time slots with 32 bidirectional local streams and 32 bidirectional H.100/H.110 streams. The T8110L has all the features of the T810X devices. Additionally, the T8110L has more robust clocking fallback abilities and is pin compatible with the T8110. (The full version of the T8110 has a PCI and minbridge interface.) ! ! ! ! ! ! Eight independently programmed framing signals Four local clocks T1/E1 rate adaptation Two clock-fallback modes Stratum 4/4E and AT&T ® 62411 MTIE compliant Incorporates 38 H.100 and 34 H.110 termination resistors Subrate switching of 4 bits, 2 bits, or 1 bit Backward compatible to all T810x devices Pin compatible with T8110 JTAG/boundary-scan testing support BSDL files available Assists H.110 hot swap Single 3.3 V supply with 5 V tolerant inputs and TTL compatible outputs 272 PBGA package Evaluation boards available ! ! ! 1.1 Features ! ! ! ! ! ! 4,096-connection unified switch Full H.100/H.110 support (32 data lines, all clock modes) 32 local I/O lines (2, 4, 8, or 16 Mbits/s) Microprocessor interface: Motorola ®/Intel ® modes Interrupt controller with external inputs Eight independent general-purpose I/O lines ! ! ! ! ! ! Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Table of Contents Contents 1 2 Page 3 4 5 6 Introduction ......................................................................................................................................................... 1 1.1 Features....................................................................................................................................................1 Pin Description ..................................................................................................................................................10 2.1 Interface Signals .....................................................................................................................................10 2.2 T8110L Pinout Information .....................................................................................................................12 2.3 Special Buffer Requirements ..................................................................................................................20 2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down ..............................................................................20 2.3.2 Local Bus Signal Internal Pull-Up ...............................................................................................20 Main Architectural Features ..............................................................................................................................21 3.1 T8110L Architecture ...............................................................................................................................21 Microprocessor Interface ..................................................................................................................................22 4.1 Intel/Motorola Protocol Selector..............................................................................................................22 4.2 Word/Byte Addressing Selector..............................................................................................................22 4.3 Access Via the Microprocessor Bus .......................................................................................................23 4.3.1 Microprocessor Interface Register Map ......................................................................................24 4.3.2 Register Space Access ...............................................................................................................28 4.3.3 Connection Memory Space Access ............................................................................................28 4.3.4 Data Memory Space Access.......................................................................................................29 Operating Control and Status ...........................................................................................................................30 5.1 Control Registers ....................................................................................................................................30 5.1.1 Reset Registers ..........................................................................................................................30 5.1.2 Master Output Enable Register...................................................................................................31 5.1.3 Connection Control—Data Memory Selector Register ...............................................................32 5.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register ................................33 5.1.5 Phase Alignment Select Register ...............................................................................................33 5.1.6 Fallback Control Register............................................................................................................33 5.1.7 Fallback Type Select Register ....................................................................................................34 5.1.8 Fallback Trigger Registers ..........................................................................................................35 5.1.9 Watchdog Select, C8, and NETREF Registers...........................................................................36 5.1.10 Watchdog EN Register ...............................................................................................................37 5.1.11 Failsafe Control Registers...........................................................................................................38 5.2 Error and Status Registers .....................................................................................................................39 5.2.1 Clock Errors ................................................................................................................................40 5.2.1.1 Transient Clock Errors Registers.................................................................................40 5.2.1.2 Latched Clock Error Register ......................................................................................41 5.2.2 System Status .............................................................................................................................42 5.2.2.1 Clock Fallback Status Register....................................................................................42 5.2.2.2 Device Identification Registers ....................................................................................43 5.2.2.3 System Device Errors..................................................................................................43 Clock Architecture .............................................................................................................................................44 6.1 Clock Input Control Registers .................................................................................................................45 6.1.1 Main Input Selector Register.......................................................................................................45 6.1.2 Main Divider Register..................................................................................................................46 6.1.3 Analog PLL1 (APLL1) Input Selector Register............................................................................46 6.1.4 APLL1 Rate Register ..................................................................................................................47 6.1.5 Main Inversion Select Register ...................................................................................................47 6.1.6 Resource Divider Register ..........................................................................................................48 6.1.7 Analog PLL2 (APLL2) Rate Register ..........................................................................................48 6.1.8 LREF Input Select Registers.......................................................................................................49 6.1.9 DPLL1 Input Selector ..................................................................................................................50 Agere Systems Inc. 2 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Table of Contents (continued) Contents Page 7 8 6.1.9.1 DPLL1 Rate Register...................................................................................................50 6.1.10 DPLL2 Input Selector ..................................................................................................................50 6.1.10.1 DPLL2 Rate Register...................................................................................................51 6.1.11 NETREF1 Registers....................................................................................................................51 6.1.12 NETREF2 Registers....................................................................................................................52 6.2 Clock Output Control Registers ..............................................................................................................53 6.2.1 Master Output Enables Register .................................................................................................53 6.2.2 Clock Output Format Registers...................................................................................................54 6.2.3 TCLK and L_SCx Select Registers .............................................................................................55 6.3 Clock Register Access............................................................................................................................57 6.4 Clock Circuit Operation—APLL1 ............................................................................................................57 6.4.1 Main Clock Selection, Bit Clock, and Frame ...............................................................................57 6.4.1.1 Watchdog Timers ........................................................................................................58 6.4.1.2 Frame Center Sampling ..............................................................................................59 6.4.1.3 LREF Pair Polarity Configuration.................................................................................60 6.4.2 Main and Resource Dividers .......................................................................................................61 6.4.3 DPLL1 .........................................................................................................................................61 6.4.4 Reference Selector .....................................................................................................................61 6.4.5 Internal Clock Generation ...........................................................................................................61 6.4.5.1 Phase Alignment .........................................................................................................62 6.5 Clock Circuit Operation, APLL2 ..............................................................................................................63 6.5.1 DPLL2 .........................................................................................................................................63 6.6 Clock Circuit Operation, CT_NETREF Generation.................................................................................63 6.6.1 NETREF Source Select ..............................................................................................................63 6.6.2 NETREF Divider..........................................................................................................................63 6.7 Clock Circuit Operation—Fallback and Failsafe .....................................................................................64 6.7.1 Clock Fallback.............................................................................................................................64 6.7.1.1 Fallback Events ...........................................................................................................64 6.7.1.2 Fallback Scenarios—Fixed vs. Rotating Secondary....................................................65 6.7.1.3 H-Bus Clock Enable/Disable on Fallback ....................................................................68 6.7.2 Clock Failsafe .............................................................................................................................70 6.7.2.1 Failsafe Events ............................................................................................................70 Frame Group and FG I/O ..................................................................................................................................72 7.1 Frame Group Control Registers..............................................................................................................72 7.1.1 FGx Lower and Upper Start Registers ........................................................................................72 7.1.2 FGx Width Registers ...................................................................................................................73 7.1.3 FGx Rate Registers ....................................................................................................................73 7.2 FG7 Timer Option ...................................................................................................................................74 7.2.1 FG7 Counter (Low and High Byte) Registers..............................................................................74 7.3 FGIO Control Registers ..........................................................................................................................75 7.3.1 FGIO Data Register ....................................................................................................................75 7.3.2 FGIO Read Mask Register..........................................................................................................75 7.3.3 FGIO R/W Register .....................................................................................................................76 7.4 FG Circuit Operation...............................................................................................................................77 7.4.1 Frame Group 8 kHz Reference Generation ................................................................................78 7.4.2 FGIO General-Purpose Bits ........................................................................................................79 7.4.3 Programmable Timer (FG7 Only)................................................................................................79 7.4.4 FG External Interrupts.................................................................................................................79 7.4.5 FG Diagnostic Test Point Observation........................................................................................79 General-Purpose I/O .........................................................................................................................................80 8.1 GPIO Control Registers ..........................................................................................................................80 3 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Table of Contents (continued) Contents Page 8.1.1 GPIO Data Register ....................................................................................................................80 8.1.2 GPIO Read Mask Register .........................................................................................................81 8.1.3 GPIO R/W Register.....................................................................................................................81 8.1.4 GPIO Override Register ..............................................................................................................82 8.2 GP Circuit Operation...............................................................................................................................82 8.2.1 GPIO General-Purpose Bits........................................................................................................83 8.2.2 GP Dual-Purpose Bits GPIO (Override)...................................................................................... 83 8.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) ..................................................83 8.2.3 GP External Interrupts ................................................................................................................83 8.2.4 GP Diagnostic Test Point Observation .......................................................................................83 9 Stream Rate Control .........................................................................................................................................84 9.1 H-Bus Stream Rate Control Registers....................................................................................................85 9.1.1 H-Bus Rate Registers .................................................................................................................85 9.2 L-Bus Stream Rate Control Registers ....................................................................................................85 9.2.1 L-Bus Rate Registers ..................................................................................................................85 9.2.2 L-Bus 16.384 Mbits/s Operation .................................................................................................86 9.2.3 16.384 Mbits/s Local I/O Superrate ............................................................................................88 9.2.4 16.384 Mbits/s Local I/O Superrate ............................................................................................89 10 Error Reporting and Interrupt Control ...............................................................................................................90 10.1 Interrupt Control Registers......................................................................................................................90 10.1.1 Interrupts Via External FG[7:0] Registers ...................................................................................90 10.1.1.1 FGIO Interrupt Pending Register.................................................................................90 10.1.2 Interrupts Via External GP[7:0] ...................................................................................................92 10.1.2.1 GPIO Interrupt Pending Register.................................................................................92 10.1.2.2 GPIO Edge/Level and GPIO Polarity Registers ..........................................................93 10.1.3 Interrupts Via Internal System Errors ..........................................................................................93 10.1.4 System Interrupt Pending High/Low Registers ...........................................................................94 10.1.5 System Interrupt Enable High/Low Registers .............................................................................95 10.1.6 Interrupts Via Internal Clock Errors .............................................................................................96 10.1.7 Clock Interrupt Pending High/Low Registers ..............................................................................97 10.1.8 Clock Interrupt Enable High/Low Registers ................................................................................98 10.1.9 Interrupt Servicing Registers.......................................................................................................99 10.1.9.1 Arbitration Control Register .........................................................................................99 10.1.9.2 SYSERR and CLKERR Output Select Register ..........................................................99 10.1.9.3 Interrupt In-Service Registers....................................................................................101 10.2 Error Reporting and Interrupt Controller Circuit Operation ...................................................................103 10.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] ..................................................................104 10.2.2 Internally Sourced System Error Interrupts ...............................................................................104 10.2.3 Internally Sourced Clock Error Interrupts ..................................................................................104 10.2.4 Arbitration of Pending Interrupts ...............................................................................................104 10.2.4.1 Arbitration Off ............................................................................................................104 10.2.4.2 Flat Arbitration ...........................................................................................................104 10.2.4.3 Tier Arbitration ...........................................................................................................104 10.2.4.4 Pre-Empting Disabled................................................................................................105 10.2.4.5 Pre-Empting Enabled ................................................................................................105 10.2.5 CLKERR Output........................................................................................................................105 10.2.6 SYSERR Output .......................................................................................................................105 10.2.7 System Handling of Interrupts...................................................................................................105 11 Test and Diagnostics ......................................................................................................................................106 11.1 Diagnostics Control Registers ..............................................................................................................106 11.1.1 FG Testpoint Enable Register...................................................................................................106 4 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Table of Contents (continued) Contents Page 11.1.2 GP Testpoint Enable Register ..................................................................................................108 11.1.3 State Counter Modes Registers ................................................................................................110 11.1.4 Miscellaneous Diagnostics Low Register..................................................................................110 11.1.5 Miscellaneous Diagnostic Registers .........................................................................................111 11.2 Diagnostic Circuit Operation .................................................................................................................112 12 Connection Control .........................................................................................................................................113 12.1 Programming Interface .........................................................................................................................113 12.1.1 Connection Memory Programming ...........................................................................................113 12.2 Switching Operation..............................................................................................................................115 12.2.1 Memory Architecture and Configuration....................................................................................115 12.2.1.1 Connection Memory ..................................................................................................115 12.2.1.2 Data Memory .............................................................................................................116 12.2.2 Standard Switching ...................................................................................................................117 12.2.2.1 Constant Delay and Minimum Delay Connections ....................................................117 12.2.2.2 Pattern Mode .............................................................................................................117 12.2.2.3 Subrate ......................................................................................................................117 13 Electrical Characteristics.................................................................................................................................124 13.1 Absolute Maximum Ratings ..................................................................................................................124 13.1.1 Handling Precautions ................................................................................................................124 13.2 Crystal Specifications ...........................................................................................................................124 13.2.1 XTAL1 Crystal ...........................................................................................................................124 13.2.2 XTAL2 Crystal ...........................................................................................................................125 13.2.3 Reset Pulse...............................................................................................................................126 13.3 Thermal Parameters (Definitions and Values)......................................................................................126 13.4 Reliability ..............................................................................................................................................127 13.5 dc Electrical Characteristics..................................................................................................................128 13.5.1 Electrical Drive Specifications, CT_C8 and /CT_FRAME .........................................................128 13.5.2 All Other Pins ............................................................................................................................129 13.6 H-Bus Timing ........................................................................................................................................129 13.6.1 Timing Diagrams .......................................................................................................................129 13.7 ac Electrical Characteristics..................................................................................................................130 13.7.1 Skew Timing, H-Bus..................................................................................................................130 13.8 Hot Swap ..............................................................................................................................................131 13.8.1 LPUE (Local Pull-Up Enable)....................................................................................................131 13.9 Decoupling............................................................................................................................................131 13.10 APLL VDD Filter ....................................................................................................................................132 13.11 PC Board PBGA Considerations ..........................................................................................................133 13.12 Unused Pins .........................................................................................................................................133 13.13 External Pull-Up Pins............................................................................................................................133 13.14 T8110L Evaluation Kits.........................................................................................................................133 13.15 T8110L Ordering Information................................................................................................................133 14 JTAG/Boundary Scan .....................................................................................................................................137 14.1 The Principle of Boundary-Scan Architecture.......................................................................................137 14.1.1 Instruction Register ...................................................................................................................138 14.2 Boundary-Scan Register.......................................................................................................................138 A Constant and Minimum Delay Connections ....................................................................................................139 A.1 Connection Definitions..........................................................................................................................139 A.2 Delay Type Definitions..........................................................................................................................139 B Register Bit Field Mnemonic Summary...........................................................................................................142 Significant Changes Between the June 2003 and November 2003 Release ........................................................163 Agere Systems Inc. 5 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 List of Figures Figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Page T8110L Pull-Up/Pull-Down Arrangement for H1x0 Pins ....................................................................... 20 T8110L Architecture Block Diagram ..................................................................................................... 21 Microprocessor Access Timing, Intel Protocol ...................................................................................... 26 Microprocessor Access Timing, Motorola Protocol ............................................................................... 27 T8110L Main Clocking Paths ................................................................................................................ 44 T8110L NETREF Paths ........................................................................................................................ 44 T8110L Required Frame Pulse and Bit Clock with Polarities ............................................................... 60 T8110L Phase Alignment, SNAP and SLIDE ....................................................................................... 62 Fallback—Fixed vs. Rotating Secondary .............................................................................................. 65 T8110L Clock Fallback States .............................................................................................................. 66 T8110L H-Bus Clock Enable States ..................................................................................................... 68 T8110L Clock Failsafe States ............................................................................................................... 70 FG[7:0] Functional Paths ...................................................................................................................... 77 Frame Group 8 kHz Reference Timing ................................................................................................. 78 GP[7:0] Functional Paths ...................................................................................................................... 82 Local Stream 16.384 Mbits/s Timing..................................................................................................... 86 Local Stream 16.384 Mbits/s Circuit ..................................................................................................... 87 Superrate I/O Configuration .................................................................................................................. 88 Relationship Between 8.192 Mbits/s and 16.384 Mbits/s Time Slots ................................................... 89 Interrupt Controller .............................................................................................................................. 103 Microprocessor Programming—Reset Page Command ..................................................................... 114 Microprocessor Programming—Make/Break/Query Telephony Connections..................................... 114 T8110L Data Memory Map and Configurations .................................................................................. 116 TDM Data Stream Bit Rates ............................................................................................................... 118 Subrate Switching Example, Byte Packing ......................................................................................... 121 Subrate Switching Example, Byte Unpacking ..................................................................................... 123 Clock Alignment .................................................................................................................................. 129 Frame Timing Diagram ....................................................................................................................... 130 Detailed Clock Skew Timing Diagram................................................................................................. 130 APLL VDD Filtering .............................................................................................................................. 132 T8110L Pins by Functional Group ...................................................................................................... 134 IEEE® 1149.1 Boundary-Scan Architecture ........................................................................................ 137 Constant Delay Connection Latency................................................................................................... 140 Minimum Delay Connection Latency .................................................................................................. 141 6 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch List of Tables Table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Page Microprocessor Interface Signals ..........................................................................................................10 H-Bus (H.100/H.110 Interface) Signals .................................................................................................10 L-Bus (Local) Interface Signals .............................................................................................................10 Clock Circuit Interface Signals ..............................................................................................................11 GPIO Interface Signals..........................................................................................................................11 Miscellaneous Interface Signals ............................................................................................................11 JTAG Signals ........................................................................................................................................11 T8110L Pinouts .....................................................................................................................................13 Intel/Motorola Protocol Selector ............................................................................................................22 T8110L Memory Mapping to Microprocessor Space.............................................................................23 Microprocessor Interface Register Map ................................................................................................24 Register Space Access Timing .............................................................................................................28 Connection Memory Space Access Timing...........................................................................................28 Data Memory Space Access Timing .....................................................................................................29 Control Register Map ............................................................................................................................30 Reset Registers .....................................................................................................................................31 Master Output Enable Register .............................................................................................................32 Data Memory Mode Select Register .....................................................................................................32 Clock Register Access Select Register .................................................................................................33 Phase Alignment Select Register ..........................................................................................................33 Fallback Control Register ......................................................................................................................34 Fallback Type Select Register...............................................................................................................35 Fallback Trigger Registers ....................................................................................................................35 Watchdog Select, C8, NETREF Registers ............................................................................................36 Watchdog EN Registers ........................................................................................................................37 Failsafe Control Register .......................................................................................................................38 Error and Status Register Map ..............................................................................................................39 Clock Error Registers ............................................................................................................................40 Latched Clock Error Registers ..............................................................................................................41 Fallback and Failsafe Status Register ...................................................................................................42 System Errors Registers .......................................................................................................................43 Device Identification Registers ..............................................................................................................43 Clock Input Control Register Map .........................................................................................................45 Main Input Selector Register .................................................................................................................45 Main Divider Register ............................................................................................................................46 APLL1 Input Selector Register ..............................................................................................................46 APLL1 Rate Register.............................................................................................................................47 Main Inversion Select Register..............................................................................................................47 Resource Divider Register ....................................................................................................................48 APLL2 Rate Register.............................................................................................................................48 LREF Input/Inversion Select Registers .................................................................................................49 DPLL1 Input Selector Registers ............................................................................................................50 DPLL2 Register .....................................................................................................................................51 NETREF1 Registers ..............................................................................................................................51 NETREF2 Registers ..............................................................................................................................52 Clock Output Control Register Map.......................................................................................................53 Master Output Enables Registers .........................................................................................................54 Clock Output Format Registers .............................................................................................................55 TCLK Select and L_SCx Select Registers ............................................................................................56 Bit Clock and Frame ..............................................................................................................................57 7 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 List of Tables (continued) Table Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Page Watchdog Timer Description .................................................................................................................58 Frame Center Sampling ........................................................................................................................59 Legacy Mode Fallback Event Triggers ..................................................................................................65 Clock Fallback State Description...........................................................................................................67 H-Bus Clock Enable State Description..................................................................................................69 Clock Failsafe State Descriptions..........................................................................................................71 Frame Group and FG I/O Register Map................................................................................................72 FGx Lower and Upper Start Registers ..................................................................................................72 FGx Width Registers .............................................................................................................................73 FGx Rate Registers ...............................................................................................................................73 FG7 Counter (Low and High Byte) Registers ........................................................................................74 FGIO Data Register...............................................................................................................................75 FGIO Read Mask Register ....................................................................................................................75 FGIO R/W Register ...............................................................................................................................76 GPIO Register .......................................................................................................................................80 GPIO Data Register ..............................................................................................................................80 GPIO Read Mask Register....................................................................................................................81 GPIO R/W Register ...............................................................................................................................81 GPIO Override Register ........................................................................................................................82 T8110L Serial Stream Groupings..........................................................................................................84 H-Bus Rate Registers............................................................................................................................85 L-Bus Rate Registers ............................................................................................................................85 Interrupt Control Register Map ..............................................................................................................90 FGIO Interrupt Pending Registers.........................................................................................................90 FGIO Edge/Level and Polarity Registers ..............................................................................................91 GPIO Interrupt Pending Register ..........................................................................................................92 GPIO Edge/Level and GPIO Polarity Registers ....................................................................................93 System Error Interrupt Assignments .....................................................................................................93 System Interrupt Pending High/Low Registers......................................................................................94 System Interrupt Enable High/Low Registers........................................................................................95 Clock Error Interrupt Assignments ........................................................................................................96 Clock Interrupt Pending High/Low Registers.........................................................................................97 Clock Interrupt Enable High/Low Registers...........................................................................................98 Arbitration Control Register ...................................................................................................................99 SYSERR Output Select Registers.......................................................................................................100 Interrupt In-Service Register ...............................................................................................................101 Diagnostics Control Register Map.......................................................................................................106 FG Testpoint Enable Registers ...........................................................................................................106 FG[7:0] Internal Testpoint Assignments ..............................................................................................107 Testpoint Enable Registers .................................................................................................................108 GP[7:0] Internal Testpoint Assignments..............................................................................................109 State Counter Modes Registers ..........................................................................................................110 Miscellaneous Diagnostics Low Register ............................................................................................110 Miscellaneous Diagnostic Registers....................................................................................................111 Microprocessor Programming, Connection Memory Access ..............................................................113 TDM Data Stream ...............................................................................................................................118 Subrate Switching, Data Propagation Rate vs. Channel Capacity ......................................................119 Subrate Switching, Connection Memory Programming Setup ............................................................120 Absolute Maximum Ratings.................................................................................................................124 XTAL1 Specifications ..........................................................................................................................124 8 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch List of Tables (continued) Table Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Page 16.384 MHz Oscillator Requirements..................................................................................................125 XTAL2 Specifications ..........................................................................................................................125 6.176 MHz/12.352 MHz Oscillator Requirements ...............................................................................125 Reset Pulse .........................................................................................................................................126 Thermal Parameter Values..................................................................................................................127 Reliability Data.....................................................................................................................................127 Electrical Drive Specifications, CT_C8 and /CT_FRAME....................................................................128 dc Electrical Characteristics, All Other Pins ........................................................................................129 Skew Timing, H-Bus ............................................................................................................................130 L_SC[3:0] and Frame Group Rise and Fall Time ................................................................................131 T8110L Ordering Information ..............................................................................................................133 Instruction Register..............................................................................................................................138 Special Cases (Exceptions).................................................................................................................141 Mnemonic Summary, Sorted by Name................................................................................................143 Mnemonic Summary, Sorted by Register............................................................................................153 Changes ..............................................................................................................................................163 Agere Systems Inc. 9 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 2 Pin Description 2.1 Interface Signals Table 1. Microprocessor Interface Signals Signal A D RD# (DS#) WR# (R/W#) CSN WB_SEL RDY (DTACK#) IM_SEL I/O I I/O I I I I Out I Width 20 16 1 1 1 1 1 1 Microprocessor Interface Function Address[19:0] in. Data bus in/out. RDn(DSn) in. WRn(R/Wn) in. CSn in. Word/byte select in. RDY(DTACKn) out. Intel/Motorola select in. Table 2. H-Bus (H.100/H.110 Interface) Signals Signal VPRECHARGE H110_ENABLE H100_ENABLE CT_D CT_C8_A /CT_FRAME_A CT_C8_B /CT_FRAME_B CT_NETREF1 CT_NETREF2 /C16+ /C16– /C4 C2 SCLK /SCLKx2 /FR_COMP I/O In In In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Width 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 Function Precharge voltage for pull-downs, H.110 bus signals: CT_D, CT_NETREF1, CT_NETREF2. Pull-down enable for H.110 bus signals: CT_D, CT_NETREF1, CT_NETREF2. Pull-up enable for H.100 bus signals: CT_D, CT_NETREF1, CT_NETREF2, CT_C8_A, CT_C8_B, /CT_FRAME_A, /CT_FRAME_B. H.100/H.110 bus data. H.100/H.110 bit clock A. H.100/H.110 frame reference A. H.100/H.110 bit clock B. H.100/H.110 frame reference B. H.100/H.110 network reference 1. H.100/H.110 network reference 2. H-MVIP™ compatibility clock (16.384 MHz, differential). H-MVIP compatibility clock (16.384 MHz, differential). MVIP compatibility clock (4.096 MHz). MVIP compatibility clock (2.048 MHz). SC-bus compatibility clock. SC-bus compatibility clock. Compatibility frame reference. Table 3. L-Bus (Local) Interface Signals Signal L_D L_SC FG I/O I/O Out I/O Width 32 4 8 Local bus data. Local bus clock outputs. Local frame groups. Function 10 10 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 2 Pin Description (continued) 2.1 Interface Signals (continued) Table 4. Clock Circuit Interface Signals Signal XTAL1_IN XTAL1_OUT XTAL2_IN XTAL2_OUT LREF TCLK_OUT PRI_REF_OUT PRI_REF_IN NR1_SEL_OUT NR1_DIV_IN NR2_SEL_OUT NR2_DIV_IN I/O In Out In Out In Out Out In Out In Out In Width 1 1 1 1 8 1 1 1 1 1 1 1 Function Crystal oscillator #1 input (16.384 MHz). Crystal oscillator #1 feedback. Crystal oscillator #2 input (6.176 MHz or 12.352 MHz). Crystal oscillator #2 feedback. Local clock reference inputs. Internal chip clock output. Main divider reference out for CLAD/DJAT. CLAD/DJAT reference in for APLL1. CT_NETREF1 selection out for CLAD/DJAT. CLAD/DJAT reference in for CT_NETREF1 divider. CT_NETREF2 selection out for CLAD/DJAT. CLAD/DJAT reference in for CT_NETREF2 divider. Table 5. GPIO Interface Signals Signal GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 I/O I/O I/O I/O I/O I/O I/O I/O I/O Width 1 1 1 1 1 1 1 1 GPIO Function GPIO bit 0 I/O GPIO bit 1 I/O GPIO bit 2 I/O GPIO bit 3 I/O GPIO bit 4 I/O GPIO bit 5 I/O GPIO bit 6 I/O GPIO bit 7 I/O Alternate Function A-master indicator out. B-master indicator out. — — — — — — Table 6. Miscellaneous Interface Signals Signal RESET# SYSERR CLKERR LPUE PEN TESTMODE I/O In Out Out In In In Width 1 1 1 1 1 1 Function Chip reset. System error indicator. Clocking error indicator. Pull-up enable for signals: FG, GP, L_D, LREF, D, NR1_DIV_IN, NR2_DIV_IN, PRI_REF_IN. Reserved. Must be left unconnected. Reserved. Must be left unconnected. Table 7. JTAG Signals Signal TRST# TCK TMS TDI TDO Agere Systems Inc. I/O In In In In Out Width 1 1 1 1 1 JTAG reset. JTAG clock. JTAG mode select. JTAG data in. JTAG data out. 11 Function Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 2 Pin Description (continued) 2.2 T8110L Pinout Information The T8110L package is a 272-pin PBGA ball grid array. Refer to the table below for ball assignment, buffer type, and pull-up/pull-down information. Note: The pull-up/down column in the following table is defined as follows: ! ! ! ! 20 kΩ down—20 kΩ pull-down resistor is always in-circuit. 50 kΩ up—50 kΩ pull-up resistor is always in-circuit. LPUE: 50 kΩ up—when LPUE = 1, a 50 kΩ pull-up resistor is in-circuit. Enabled: 50 kΩ up/20 kΩ Vpre—when H100_ENABLE = 1, a 50 kΩ pull-up resistor is in-circuit (see Figure 1 on page 20). When H110_ENABLE = 1, a 20 kΩ pull-down resistor from the VPRECHARGE input to this signal is incircuit. 12 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts Microprocessor Interface Ball F1 G1 K3 J3 K1 K2 L3 L4 G2 G3 H1 H2 H3 J4 J1 J2 W1 V1 V2 U3 U1 U2 T3 T4 T1 T2 R3 P4 R1 R2 P2 P3 N1 P1 L1 L2 M1 M2 M3 M4 N2 N3 Pin Name A0 A1 A10 A11 A12 A13 A14 A15 A2 A3 A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RD#(DS#) WR#(R/W#) A16 A17 A18 A19 CSN WB_SEL RDY(DTACK#) IM_SEL Buffer Type 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA 3-state 8 mA I/O-Schmitt Pull-Up/Down (see note on page 12) 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up 20 kΩ down 20 kΩ down 20 kΩ down 20 kΩ down LPUE: 50 kΩ up LPUE: 50 kΩ up External pull-up required LPUE: 50 kΩ up 13 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts (continued) H-Bus Interface Ball C1 D5 D7 A11 B11 C10 C11 A10 B10 B9 C9 A9 B8 C8 A8 C7 A7 B7 C6 A6 B6 C5 A5 B5 A4 B4 C4 A3 B3 C3 A2 B2 B1 C2 D2 A13 A12 B13 B12 A14 B14 D9 14 Pin Name VPRECHARGE H110_ENABLE H100_ENABLE CT_D0 CT_D1 CT_D2 CT_D3 CT_D4 CT_D5 CT_D6 CT_D7 CT_D8 CT_D9 CT_D10 CT_D11 CT_D12 CT_D13 CT_D14 CT_D15 CT_D16 CT_D17 CT_D18 CT_D19 CT_D20 CT_D21 CT_D22 CT_D23 CT_D24 CT_D25 CT_D26 CT_D27 CT_D28 CT_D29 CT_D30 CT_D31 CT_C8_A /CT_FRAME_A CT_C8_B /CT_FRAME_B CT_NETREF1 CT_NETREF2 /C16+ Buffer Type Op amp noninvert Input Input PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O 24 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt PCI I/O PCI I/O 24 mA I/O-Schmitt Pull-Up/Down (see note on page 12) — 20 kΩ down 20 kΩ down Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up Enabled: 50 kΩ up Enabled: 50 kΩ up Enabled: 50 kΩ up Enabled: 50 kΩ up/20 kΩ Vpre Enabled: 50 kΩ up/20 kΩ Vpre 50 kΩ up Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts (continued) H-Bus Interface (continued) Ball D10 D12 D14 C14 C13 C12 J20 J19 J18 K17 K20 K19 K18 L18 L20 L19 M18 M17 M20 M19 N19 N18 N20 P20 P19 P18 R20 R19 R18 P17 T20 T19 T18 U20 V20 U19 U18 T17 H20 H19 H18 G19 Agere Systems Inc. Pin Name /C16– /C4 C2 SCLK /SCLKX2 /FR_COMP LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 L_SC0 L_SC1 L_SC2 L_SC3 Buffer Type 24 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt 24 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA 3-state 8 mA 3-state 8 mA 3-state 8 mA 3-state Pull-Up/Down (see note on page 12) 50 kΩ up 50 kΩ up 50 kΩ up 50 kΩ up 50 kΩ up 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up — — — — 15 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts (continued) L-Bus Interface Ball Y20 Y19 W20 W19 W18 V19 V18 V17 B20 C19 E20 F19 A15 B15 C15 C16 A16 B16 Ball B17 C17 G20 A17 A18 B18 A19 D19 C20 Ball D1 E1 E2 F2 D3 F3 E3 E4 Pin Name FG0 FG1 FG2 FG3 FG4 FG5 FG6 FG7 XTAL1_IN XTAL1_OUT XTAL2_IN XTAL2_OUT LREF0 LREF1 LREF2 LREF3 LREF4 LREF5 Pin Name LREF6 LREF7 TCLK_OUT PRI_REF_OUT PRI_REF_IN NR1_SEL_OUT NR1_DIV_IN NR2_SEL_OUT NR2_DIV_IN Pin Name GP0/AMASTER GP1/BMASTER GP2 GP3 GP4 GP5 GP6 GP7 Buffer Type 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt Input Crystal feedback Input Crystal feedback Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt Clock Circuit Interface Buffer Type Input-Schmitt Input-Schmitt 8 mA 3-state 8 mA 3-state Input-Schmitt 8 mA 3-state Input-Schmitt 8 mA 3-state Input-Schmitt GPIO Interface Buffer Type 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt 8 mA I/O-Schmitt Pull Up/Down (see note on page 12) LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up Pull Up/Down (see note on page 12) LPUE: 50 kΩ up LPUE: 50 kΩ up — — LPUE: 50 kΩ up — LPUE: 50 kΩ up — LPUE: 50 kΩ up Pull Up/Down (see note on page 12) LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up — — — — LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up LPUE: 50 kΩ up 16 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts (continued) Miscellaneous Interfaces Ball Y1 V3 W2 J17 A20 F20 Pin Name RESET# SYSERR CLKERR LPUE PEN TESTMODE Buffer Type Input-Schmitt 8 mA 3-state 8 mA 3-state Input Input Input JTAG Interface Ball C18 E18 D18 F18 G18 Ball B19 E19 D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 Ball A1 D4 D8 D13 D17 H4 H17 Agere Systems Inc. Pin Name TRST# TCK TMS TDI TDO Pin Name APLL1VDD APLL2VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Pin Name VSS VSS VSS VSS VSS VSS VSS Buffer Type Input-Schmitt Input-Schmitt Input-Schmitt Input-Schmitt 4 mA 3-state Power Buffer Type Analog VDD Analog VDD — — — — — — — — — — — — Ground Buffer Type — — — — — — — Pull Up/Down — — — — — — — 17 Pull Up/Down — — — — — — — — — — — — — — Pull Up/Down (see note on page 12) 50 kΩ up 50 kΩ up 50 kΩ up 50 kΩ up — Pull Up/Down (see note on page 12) 50 kΩ up — — 50 kΩ up 50 kΩ up. This pin is unused and must be left unconnected. 20 kΩ up. This pin is unused and must be left unconnected. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts (continued) Ground (continued) Ball N4 N17 U4 U8 U13 U17 U5 U11 U16 W5—W9 W10 W13—W17 V4—V9 V13—V16 Y5—Y9 Y13—Y18 J9—12 K9—12 L9—12 M9—12 D16 D20 E17 G17 G4 W3 V12 Y4 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Buffer Type Pull Up/Down — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Thermal Ground — — — — — — — — No Connects No connects must be left unconnected. 18 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 2 Pin Description (continued) 2.2 T8110L Pinout Information (continued) Table 8. T8110L Pinouts (continued) External Pull-Up Ball U7 U9 U12 U14 V10 V11 W4 W11 W12 Y2 Y3 Y10 Y11 Y12 Pin Name EPU EPU EPU EPU EPU EPU EPU EPU EPU EPU EPU EPU EPU EPU Buffer Type — — — — — — — — — — — — — — Pull Up/Down — — — — — — — — — — — — — — Note: The EPU pins must be tied to an exernal pull-up resistor. Multiple pins may share a common resistor. It is recommended that all EPU pins be tied to a common 20 kΩ pull-up resistor. Agere Systems Inc. 19 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 2 Pin Description (continued) 2.3 Special Buffer Requirements 2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down The H1x0 bus pins require special consideration for H.100 and H.110 usage. There are two control pins to select between various internal bus pull-ups/pull-downs, as shown below: ! H100_ENABLE. Enables internal 50 kΩ pull-ups on CT_Dn, CT_NETREF1, CT_NETREF2, CT_C8_A, CT_C8_B, /CT_FRAME_A, and /CT_FRAME_B signals. H110_ENABLE. Enables internal 20 kΩ pull-downs on all 32 CT_Dn signals, CT_NETREF1, and CT_NETREF2 to the VPRECHARGE signal. ! Note: The two H1x0 enables are active-high. Only one or the other should ever be asserted. Warning: Do not assert both at the same time. Please refer to Figure 1 for more detail. CT_Dn, CT_NETREF1, CT_NETREF2 VDD 50 kΩ, MIN PAD 20 kΩ, MIN TO OTHER CT_Dn PAD APPLY 0.7 V, NOMINAL VPRECHARGE H100_ENABLE H110_ENABLE PAD PAD VDD 50 kΩ, MIN PAD CT_C8_A, CT_C8_B, /CT_FRAME_A, /CT_FRAME_B 5-9611 (F) Figure 1. T8110L Pull-Up/Pull-Down Arrangement for H1x0 Pins 2.3.2 Local Bus Signal Internal Pull-Up The LPUE input is active-high; and is used to activate pull-ups on the following local signals: GP[7:0], FG[7:0], D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN. 20 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 3 Main Architectural Features 3.1 T8110L Architecture The T8110L includes all of the clocking and standard switching functions found on previous Ambassador devices, plus additional functionalities that are described in the following sections. The T8110L interfaces to a controller via a standard microprocessor interface which is described in Section 4. Note that the full version of the device, the T8110, contains both microprocessor and PCI interfaces, allowing the device to attach directly to a PCI bus. The T8110L and T8110 are pin compatible. LOCAL CLOCKS FRAME GROUPS AND GP I/O H1x0 CLOCKS CLOCKING AND TIMING CONTROL PARALLEL-TO-SERIAL CONVERSION (OUTPUT) SERIAL-TO-PARALLEL CONVERSION (INPUT) FG FRAME TIMING GROUPS ADDITIONAL I/O H1x0 EVEN CONNECTION MEMORY H1x0 ODD CONNECTION MEMORY LOCAL HIGH CONNECTION MEMORY LOCAL LOW CONNECTION MEMORY DATA MEMORY 2K x 8 DATA MEMORY 2K x 8 DATA MEMORY CONTROLLER INTERNAL CLOCKS H1x0 STREAMS (BIDIRECTIONAL) ERROR SIGNALS INTERRUPT AND ERROR CONTROL CLOCK ERRORS SYSTEM ERRORS GENERALPURPOSE I/O LOCAL STREAMS (BIDIRECTIONAL) GENERALPURPOSE I/O REGISTER ACCESS CONTROL ADDRESS DATA CONNECTION MEMORY CONTROLLER MICROPROCESSOR INTERFACE 5-8920 (F) Figure 2. T8110L Architecture Block Diagram Agere Systems Inc. 21 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 4 Microprocessor Interface 4.1 Intel/Motorola Protocol Selector IM_SEL = 1 is the default, if left unconnected, and selects an Intel handshake protocol. IM_SEL = 0 selects a Motorola handshake protocol. Note: The IM_SEL signal must be static (either pulled high or pulled low). Table 9. Intel/Motorola Protocol Selector Intel/Motorola Protocol Selector Signal D[15:0] A[19:0] CSN RDY (DTACK#) RD# (DS#) WR# (R/W#) WB_SEL IM_SEL Intel Mnemonic D[15:0] A[15:0] CSn RDY RDn (read strobe) WRn (write strobe) Default Default Motorola Mnemonic D[15:0] A[15:0] CSn DTACKn DSn (data strobe) R/Wn (read/write selector) Default Default 4.2 Word/Byte Addressing Selector WB_SEL = 1 is the default, if left unconnected, and selects 16-bit word aligned addressing. WB_SEL = 0 selects 8-bit byte aligned addressing. Note: The WB_SEL signal may be static or dynamic in nature. If dynamic, WB_SEL must follow the same timing requirements as the address bus. Word-aligned addressing produces 16-bit data transfers via D[15:0]. Byte-aligned addressing produces 8-bit data transfers via D[7:0] (D[15:8] is unused). The T8110L internal data bus is 32 bits, so A[1:0] address bits are decoded along with WB_SEL to control a dword-to-word or dword-to-byte swap function back to the data bus. 22 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus The T8110L microprocessor bus interface allows access to three internal regions: registers, connection memory, and data memory. All microprocessor bus asynchronous strobes are synchronized to the T8110L's internal 65.536 MHz clock domain. There are 20 address bits provided to address the internal regions and these are defined in Table 10. Table 10. T8110L Memory Mapping to Microprocessor Space Region Registers Subregion Reserved Operating control and status Clocks Rate control Frame group General-purpose I/O Interrupt control Reserved Reserved Reserved Data memory Reserved Connection memory Reserved — — — — — Range (hex) 0x00000—0x000FF 0x00100—0x001FF 0x00200—0x002FF 0x00300—0x003FF 0x00400—0x004FF 0x00500—0x005FF 0x00600—0x006FF 0x00700—0x007FF 0x00800—0x0FFFF 0x10000—0x1FFFF 0x20000—0x2FFFF 0x30000—0x3FFFF 0x40000—0x4FFFF 0x50000—0xFFFFF Agere Systems Inc. 23 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus (continued) 4.3.1 Microprocessor Interface Register Map The T8110L registers map into the microprocessor bus space as follows. Table 11. Microprocessor Interface Register Map DWORD Cross Address Reference (20 bits) 0x00100 5.1.1, 5.1.2 0x00104 5.1.3, 5.1.4 0x00108 0x0010C 0x00114 0x00118 0x00120 0x00124 0x00128 0x00140 0x00144 0x00148 0x00200 0x00204 0x00208 0x0020C 0x00210 0x00214 0x00220 0x00224 0x00228 0x00300 0x00320 0x00400 24 5.1.4 5.1.4 4.1.5 6.1.11 5.2.1 5.2.2 5.2.2.2 11.1 11.1 11.1 6.1 6.1 6.1 6.1 6.1 6.1 6.2 6.2 6.2 9.1 9.2 7.1 Register Byte 3 Master enable Phase alignment select Fallback trigger, upper Watchdog EN, upper Reserved Reserved Status 3, latched clock errors, upper Status 7, system errors Device ID, upper Diag3 Diag7 Diag11 APLL1 rate APLL2 rate DPLL1 rate DPLL2 rate Reserved Reserved C8 output rate SCLK output rate L_SC3 select H-bus rate H/G L-bus rate H/G FG0 rate Byte 2 Reserved Byte 1 Reset select Byte 0 Soft reset Reserved Fallback control Watchdog select, C8 Failsafe control OOL threshold low Status 0, transient clock errors, lower Status 4 Version ID Diag0 Diag4 Diag8 Main input selector Main inversion select LREF input select LREF inversion select NETREF1 input selector NETREF2 input selector Master output enables CCLK output enables L_SC0 select H-bus rate B/A L-bus rate B/A FG0 lower start Agere Systems Inc. Clock register access Data memory mode select select Fallback trigger, lower Fallback type select Watchdog EN, lower Failsafe sensitivity OOL monitor Status 2, latched clock errors, lower Reserved Device ID, lower Diag2 Diag6 Diag10 APLL1 input selector Reserved DPLL1 input selector DPLL2 input selector NETREF1 LREF select NETREF2 LREF select /FR_COMP width TCLK select L_SC2 select H-bus rate F/E L-bus rate F/E FG0 width Watchdog select, NETREF Failsafe enable OOL threshold high Status 1, transient clock errors, upper Reserved Reserved Diag1 Diag5 Diag9 Main divider Resource divider Reserved Reserved NETREF1 divider NETREF2 divider NETREF output enables Reserved L_SC1 select H-bus rate D/C L-bus rate D/C FG0 upper start Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus (continued) 4.3.1 Microprocessor Interface Register Map (continued) Table 11. Microprocessor Interface Register Map (continued) DWORD Cross Address Reference (20 bits) 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00474 0x00480 0x00500 0x00600 0x00604 0x00608 0x0060C 0x00610 0x00614 0x006FC 7.1 7.1 7.1 7.1 7.1 7.1 7.1 7.2 7.3 8.1 12.1 10.1 10.1 10.1 10.1 10.1 10.1 Register Byte 3 FG1 rate FG2 rate FG3 rate FG4 rate FG5 rate FG6 rate FG7 rate FG7 mode upper Reserved GPIO override FGIO interrupt polarity GPIO interrupt polarity System interrupt enable, upper Clock interrupt enable, upper CLKERR output select Reserved Byte 2 FG1 width FG2 width FG3 width FG4 width FG5 width FG6 width FG7 width FG7 mode lower FGIO R/W GPIO R/W Reserved Reserved System interrupt enable, lower Clock interrupt enable, lower SYSERR output select Reserved Byte 1 FG1 upper start FG2 upper start FG3 upper start FG4 upper start FG5 upper start FG6 upper start FG7 upper start FG7 counter high byte FGIO read mask GPIO read mask FGIO interrupt enable GPIO interrupt enable System interrupt pending, upper Clock interrupt pending, upper Reserved Reserved In-service, high Byte 0 FG1 lower start FG2 lower start FG3 lower start FG4 lower start FG5 lower start FG6 lower start FG7 lower start FG7 counter low byte FGIO data register GPIO data register FGIO interrupt pending GPIO interrupt pending System interrupt pending, lower Clock interrupt pending, lower Arbitration control Reserved In-service, low CLKERR pulse width SYSERR pulse width Agere Systems Inc. 25 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus (continued) 4.3.1 Microprocessor Interface Register Map (continued) Microprocessor Access Read Cycle, Intel Protocol taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID CSn tas RDn tRDYhi tRDYlo RDY tah tde D[15:0], READ CYCLE tdv READ DATA VALID tdz 5-9418 (F) Microprocessor Access Write Cycle, Intel Protocol taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID CSn tas WRn tRDYhi tRDYlo RDY tds tdh WR DATA VALID tah D[15:0], WRITE CYCLE 5-9419 (F) Figure 3. Microprocessor Access Timing, Intel Protocol 26 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus (continued) 4.3.1 Microprocessor Interface Register Map (continued) Microprocessor Access Read Cycle, Motorola Protocol taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID R/Wn CSn tas DSn tDTACKlo DTACKn tde D[15:0], READ CYCLE tdv READ DATA VALID 5-9416 (F) tah tDTACKhi tdz Microprocessor Access Write Cycle, Motorola Protocol taccess WORD/BYTE SELECT, A[19:0] ADDRESS VALID R/Wn CSn tas DSn tDTACKlo DTACKn tds D[15:0], WRITE CYCLE tdh tDTACKhi tah WR DATA VALID 5-9417 (F) Figure 4. Microprocessor Access Timing, Motorola Protocol Agere Systems Inc. 27 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus (continued) 4.3.2 Register Space Access The T8110L registers are always immediately available for access, providing low latency time to acknowledge the transaction. Read access to [reserved] addresses returns 0x00. Register access timing for Figure 3 and Figure 4 is shown below. Table 12. Register Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Overall Access Time Address Setup Time Address Hold Time Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time Parameter Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) — — — 12 72 70 15 14 9 16 — — 4.3.3 Connection Memory Space Access The T8110L connection memory is always immediately available for access (via dedicated access times assigned for microprocessor transactions) providing low latency time to acknowledge the transaction. Connection memory access timing for Figure 3 and Figure 4 is shown below. Table 13. Connection Memory Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Parameter Overall Access Time Address Setup Time Address Hold Time Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) — — — 12 72 70 15 14 9 16 — — 28 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 4 Microprocessor Interface (continued) 4.3 Access Via the Microprocessor Bus (continued) 4.3.4 Data Memory Space Access The T8110L data memory is not guaranteed to be immediately available for access. Access to data memory is prioritized for standard H-bus/L-bus switching, with microprocessor bus transaction access allowed as the lowest priority. The latency time to acknowledge these transactions is indeterminate and depends on the H-bus/L-bus switching configuration. Data memory access timing for Figure 3 and Figure 4 is shown below. Table 14. Data Memory Space Access Timing Name taccess tas tah tRDYlo tRDYhi tDTACKlo tDTACKhi tde tdv tdz tds tdh Parameter Overall Access Time Address Setup Time Address Hold Time Intel Cycle, Time to RDY Deasserted Intel Cycle, Time to RDY Reasserted Motorola Cycle, Time to DTACKn Asserted Motorola Cycle, Time to DTACKn Deasserted Read Cycle, Time to Data Enabled Read Cycle, Time to Data Valid Read Cycle, Time to Data Invalid Write Cycle, Data Setup Time Write Cycle, Data Hold Time Min (ns) 41 5 0 6 36 36 10 7 5 10 25 0 Max (ns) —* — — 12 —* —* 15 14 9 16 — — * Max data memory space access time is indeterminate, and depends on how much of the data memory access bandwidth is being taken by TDM switch connections. Agere Systems Inc. 29 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status Overall T8110L operational control and status is configured via registers occupying 0x00100—0x001FC in the address space. 5.1 Control Registers General control functions are soft reset, reset configuration, overall master output enables, and data memory configuration. Clocking-specific general control functions are clock register access configuration, phase alignment, clock fallback, and clock watchdog configuration. Table 15. Control Register Map DWORD Address Byte 3 (20 Bits) 0x00100 Master enable 0x00104 Phase alignment select 0x00108 Fallback trigger, upper 0x0010C Watchdog EN, upper 0x00114 Reserved Register Byte 2 Reserved Clock register access select Fallback trigger, lower Watchdog EN, lower Failsafe threshold low Byte 1 Reset select Data memory mode select Byte 0 Soft reset — Fallback type select Fallback control Watchdog select, Watchdog select, C8 NETREF Failsafe enable and status Failsafe control 5.1.1 Reset Registers The soft reset and reset select registers control soft reset functions and reset signal masking. Writes to the soft reset register trigger the corresponding action, and the set bit(s) are automatically cleared. ! Power-on reset: nonmaskable: — At power-on, initialize all T8110L registers (including reset select register) and connection valid flags. The power-on reset cell test input is controlled via diagnostic register; see Section 11. Hard reset: maskable via reset select register, HRBEB: — On assertion of RESET#, initialize all T8110L registers (excluding reset select register) and connection valid flags. ! Soft resets are maskable via reset select register, SRBEB, and selectable via soft reset register, SRESR. ! ! ! ! Soft reset 1: Initialize all T8110L registers (excluding reset select register) and connection valid flags. Soft reset 2: Initialize all T8110L registers (excluding reset select register). Soft reset 3: Reset all interrupt pending registers and the interrupt in-service register. Soft reset 4: Reset the interrupt in-service register only. 30 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.1 Control Registers (continued) Table 16. Reset Registers Byte Address Name Bit(s) Mnemonic 7:0 SRESR Value 0000 0000 0000 0001 0000 0010 0001 0000 0010 0000 0000 0 1 0 1 Function NOP (default value). Reset all registers and connection valid flags. Reset all registers. Reset interrupt pending and in-service registers. Reset interrupt in-service register only. NOP (default). Disable hard reset to back end. Enable hard reset to back end (default). Disable soft resets to back end. Enable soft resets to back end (default). 0x00100 Soft Reset 0x00101 Reset Select 7:2 1 0 Reserved HRBEB SRBEB 5.1.2 Master Output Enable Register The master output enable register is used to control master output enables to various groups of T8110L signals, including the following: L-bus data streams (L_D[31:0]) L-bus clocks (L_SC[3:0], FG[7:0] when used as frame group outputs) H-bus data streams (CT_D[31:0]) H-bus clocks (CT_C8_A, /CT_FRAME_A, CT_C8_B, /CT_FRAME_B, CT_NETREF1,CT_NETREF2, /C16+, /C16–, /C4, C2, SCLK, /SCLKx2, /FR_COMP) GPIO (GP[7:0]) FGIO (FG[7:0] when used as programmable register outputs) T8110L outputs that are not programmatically enabled (i.e., always driven except during reset) include the following: CLKERR, SYSERR, PRI_REF_OUT, NR1_SEL_OUT, and NR2_SEL_OUT. Agere Systems Inc. 31 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status (continued) 5.1 Control Registers (continued) Table 17. Master Output Enable Register Byte Address Name Bit(s) 7 6 5 4 3 2 1 0 Mnemonic AIOEB Reserved FGREB GPIEB HCKEB HDBEB LCKEB LDBEB Value 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 Function Individual enables via bits [6:0] (default). Enable all (same as bits [6:0] = 1111111). NOP. Disable FGIO (default). Enable FGIO. Disable GPIO (default). Enable GPIO. Disable H-bus clocks (default). Enable H-bus clocks. Disable H-bus data streams (default). Enable H-bus data streams. Disable L-bus clocks, L_SC, FG (default). Enable L-bus clocks. Disable L-bus data streams (default). Enable L-bus data streams. 0x00103 Master Enable 5.1.3 Connection Control—Data Memory Selector Register The data memory mode select register MSbit controls subrate switching enable. The lower 7 bits control the T8110L data memory switching configuration. For more details, see Section 12.2.1.2 on page 116. There are three data memory configurations as outlined below: 1. 4k single-buffered switch. Standard H-bus/L-bus switching only, up to 4096 simplex connections, all connections are minimum delay due to single-buffer configuration. 2. 2k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex connections, all connections are programmable for minimum or constant delay via the double-buffer configuration. 3. 2k single-buffered switch + 1k double-buffered switch. Standard H-bus/L-bus switching only, up to 2048 simplex minimum delay connections (single buffer) and up to 1024 simplex minimum or constant delay connections (double buffer). Table 18. Data Memory Mode Select Register Byte Address Name Bit(s) Mnemonic 7 6:0 GSREB DMMSP Value 0 1 Function Disable subrate switching (default). Enable subrate switching. 0x00105 Data Memory Mode Select 100 0000 4k single-buffer switch (default). 010 0000 2k double-buffer switch. 011 0000 2k single-buffer, 1k double-buffer switch. 32 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.1 Control Registers (continued) 5.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register The clock register access select register controls the selection between accessing the active vs. the inactive set of T8110L clock registers. The T8110L contains two sets of clock registers, X and Y. The X and Y register sets are comprised of the registers listed in Table 33 on page 45, Clock Input Control Register Map, and Table 46 on page 53, Clock Output Control Register Map. Only one set is used at a time. It is selected based on the clock fallback setup. The clock register set that is currently in use is denoted as the active set; see Section 6.3 on page 57 for more details. Table 19. Clock Register Access Select Register Byte Address Name Bit(s) Mnemonic 7:0 CSASR Value Function 0x00106 Clock Register Access Select 0000 0000 Access inactive clock registers (default). 0000 0001 Access active clock registers. 5.1.5 Phase Alignment Select Register The phase alignment select register selects the phase alignment configuration. For more details, see Section 6.4.5.1 on page 62. The T8110L internally generates an 8 kHz frame reference. Shown below are three configurations to control phase alignment between this internally generated frame reference and a selected incoming frame reference from the H-bus (/CT_FRAME_A, /CT_FRAME_B, or /FR_COMP) or local clock reference (LREF[4:7]). ! ! ! Disable alignment, no realignment of unaligned frames Snap alignment, immediate realignment of unaligned frames Slide alignment, gradual realignment of unaligned frames Table 20. Phase Alignment Select Register Byte Address Name Bit(s) Mnemonic 7:0 PAFSR Value Function 0x00107 Phase Alignment Select 0000 0000 Phase alignment is disabled (default). 0000 0001 Enable snap alignment. 0000 0010 Enable slide alignment. 5.1.6 Fallback Control Register The fallback control register allows user control over the active and inactive clock register sets. For more details, see Section 6.7.1 on page 64. Writes to the fallback control register trigger the corresponding action, and the set bit(s) are automatically cleared. The four commands are shown below: ! GO_CLOCKS. At initialization, the clock register Y set is active, the X set is inactive, and access is enabled to the X set. The GO_CLOCKS command transitions the Y set to inactive and the X set to active. This command can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference (synchronized to frame). CLEAR_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets after a fallback event has occurred. This command can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference (synchronized to frame). ! Agere Systems Inc. 33 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status (continued) 5.1 Control Registers (continued) 5.1.6 Fallback Control Register (continued) ! FORCE_FALLBACK. Forces a state transition for active/inactive assignment of the clock register X and Y sets by creating a fallback event. This command can either be performed immediately upon issue or can wait to be performed until the next 8 kHz frame reference (synchronized to frame). COPY ACTIVE TO INACTIVE SET. Copies all register values in the current active clock register set to the inactive clock register set. This command is performed immediately upon issue. ! Table 21. Fallback Control Register Byte Address Name Bit(s) Mnemonic 7:0 FBCSR Value 0000 0000 0000 0001 0000 0010 0000 0100 0001 0001 0001 0010 0001 0100 0010 0000 Function NOP (default). GO_CLOCKS command. CLEAR_FALLBACK command. FORCE_FALLBACK command. GO_CLOCKS synchronized to frame*. CLEAR_FALLBACK synchronized to frame*. FORCE_FALLBACK synchronized to frame*. COPY ACTIVE TO INACTIVE SET command. 0x00108 Fallback Control * The synchronized to frame command also has a diagnostic element—instead of performing the command right at the frame boundary, the user can elect to perform the command at a specified offset time from the frame boundary, by programming the Diag11 and Diag10 registers, 0x0014B—0x0014A. 5.1.7 Fallback Type Select Register The upper nibble configures which H-bus clocks are selected to trigger a clock fallback event. Any of the legacy modes have predetermined trigger enables and ignore the fallback trigger register settings. Nonlegacy modes require the fallback trigger register settings. For more details, see Section 6.7.1 on page 64. The lower nibble configures the state machine that controls clock register set active/inactive assignments. There are three possible selections. For more details, see Section 6.7 on page 64. ! ! ! Disabled. No transitions of clock register X and Y sets to active/inactive. Fixed secondary. Swap the active/inactive sets on a fallback event; swap them back when fallback is cleared. Rotating secondary. Swap the active/inactive sets on a fallback event; maintain this state when fallback is cleared. 34 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.1 Control Registers (continued) 5.1.7 Fallback Type Select Register (continued) Table 22. Fallback Type Select Register Byte Address Name Bit(s) Mnemonic 7:4 FTRSN Value 0000 0001 0010 0100 1000 1001 0000 0001 0010 Function NOP (default). Legacy, fallback to OSC/4 on main select failure. Legacy, fallback X/Y set on main select failure. Legacy, fallback X/Y set on H-bus A/B failure. Fallback trigger registers control fallback. Fallback trigger registers control fallback and H-Bus clock enable state machine is enabled. Fallback is disabled (default). Enable fixed secondary fallback. Enable rotating secondary fallback. 0x00109 Fallback Type Select 3:0 FSMSN 5.1.8 Fallback Trigger Registers The fallback trigger registers are used in conjunction with the fallback type select register and control which H-bus clocks are enabled to trigger a clock fallback event in case of error. The sync reference inputs to DPLL1 and DPLL2 can also trigger a clock fallback event upon detection of an error. Table 23. Fallback Trigger Registers Byte Address 0x0010A Name Fallback Trigger, Lower Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 S2FEB SCFEB C2FEB C4FEB CMFEB CPFEB CBFEB CAFEB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable /SCLKx2 trigger (default). Enable /SCLKx2 trigger. Disable SCLK trigger (default). Enable SCLK trigger. Disable C2 trigger (default). Enable C2 trigger. Disable /C4 trigger (default). Enable /C4 trigger. Disable /C16– trigger (default). Enable /C16– trigger. Disable /C16+ trigger (default). Enable /C16+ trigger. Disable CT_C8_B trigger (default). Enable CT_C8_B trigger. Disable CT_C8_A trigger (default). Enable CT_C8_A trigger. Agere Systems Inc. 35 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status (continued) 5.1 Control Registers (continued) 5.1.8 Fallback Trigger Registers (continued) Table 23. Fallback Trigger Registers (continued) Byte Address 0x0010B Name Fallback Trigger, Upper Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 Reserved D2FEB D1FEB N2FEB N1FEB FCFEB FBFEB FAFEB 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NOP (default). Disable DPLL2 sync trigger (default). Enable DPLL2 sync trigger. Disable DPLL1 sync trigger (default). Enable DPLL1 sync trigger. Disable CT_NETREF2 trigger (default). Enable CT_NETREF2 trigger. Disable CT_NETREF1 trigger (default). Enable CT_NETREF1 trigger. Disable /FR_COMP trigger (default). Enable /FR_COMP trigger. Disable /CT_FRAME_B trigger (default). Enable /CT_FRAME_B trigger. Disable /CT_FRAME_A trigger (default). Enable /CT_FRAME_A trigger. Function 5.1.9 Watchdog Select, C8, and NETREF Registers The watchdog select, C8 register controls the watchdog circuits to monitor the proper frequency for the CT_C8_A and CT_C8_B signals. These signals can take on two values, including 8.192 MHz (ECTF mode) and 4.096 MHz (MC1 mode). The watchdog select, NETREF register controls the watchdog circuits to monitor the proper frequency for the CT_NETREF1 and CT_NETREF2 signals. These signals can take on three values depending on system-level clocking architecture, including 8 kHz (frame reference), 1.544 MHz (T1 bit clock), and 2.048 MHz (E1 bit clock). Table 24. Watchdog Select, C8, NETREF Registers Byte Address Name Bit(s) Mnemonic 7:4 3:0 0x0010D Watchdog Select, NETREF 7:4 CBWSN CAWSN N2WSN Value 0000 0001 0000 0001 0000 0001 0010 0000 0001 0010 Function CT_C8_B watchdog at 8.192 MHz (default). CT_C8_B watchdog at 4.096 MHz MC1mode. CT_C8_A watchdog at 8.192 MHz (default). CT_C8_A watchdog at 4.096 MHz MC1mode. CT_NETREF2 watchdog at 8 kHz (default). CT_NETREF2 watchdog at 1.544 MHz. CT_NETREF2 watchdog at 2.048 MHz. CT_NETREF1 watchdog at 8 kHz (default). CT_NETREF1 watchdog at 1.544 MHz. CT_NETREF1 watchdog at 2.048 MHz. 0x0010C Watchdog Select, C8 3:0 N1WSN 36 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.1 Control Registers (continued) 5.1.10 Watchdog EN Register The watchdog EN registers are used to enable/disable watchdogs on the individual H-bus clocks and the watchdogs on the sync inputs of DPLL1 and DPLL2. Table 25. Watchdog EN Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x0010F Watchdog EN, Upper 7 6 5 4 3 2 1 0 S2WEB SCWEB C2WEB C4WEB CMWEB CPWEB CBWEB CAWEB FSWEB D2WEB D1WEB N2WEB N1WEB FCWEB FBWEB FAWEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable /SCLKx2 watchdog (default). Enable /SCLKx2 watchdog. Disable SCLK watchdog (default). Enable SCLK watchdog. Disable C2 watchdog (default). Enable C2 watchdog. Disable/C4 watchdog (default). Enable/C4 watchdog. Disable/C16– watchdog (default). Enable/C16– watchdog. Disable/C16+ watchdog (default). Enable/C16+ watchdog. Disable CT_C8_B watchdog (default). Enable CT_C8_B watchdog. Disable CT_C8_A watchdog (default). Enable CT_C8_A watchdog. Disable FAILSAFE ref watchdog (default). Enable FAILSAFE ref watchdog. Disable DPLL2 sync watchdog (default). Enable DPLL2 sync watchdog. Disable DPLL1 sync watchdog (default). Enable DPLL1 sync watchdog. Disable CT_NETREF2 watchdog (default). Enable CT_NETREF2 watchdog. Disable CT_NETREF1 watchdog (default). Enable CT_NETREF1 watchdog. Disable /FR_COMP watchdog (default). Enable /FR_COMP watchdog. Disable /CT_FRAME_B watchdog (default). Enable /CT_FRAME_B watchdog. Disable /CT_FRAME_A watchdog (default). Enable /CT_FRAME_A watchdog. 0x0010E Watchdog EN, Lower Agere Systems Inc. 37 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status (continued) 5.1 Control Registers (continued) 5.1.11 Failsafe Control Registers Table 26. Failsafe Control Register Byte Address 0x00114 Name Failsafe Control Bit(s) Mnemonic 7:0 FSCSR Value Function 0000 0000 NOP (default). 0000 0001 Return from failsafe to nonfallback condition. 0000 0010 Return from failsafe to fallback condition. 0000 0000 Failsafe disabled. 0000 0001 Failsafe enabled. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 Failsafe watchdog highest sensitivity. Failsafe watchdog + 30.5 ns. Failsafe watchdog + 121.0 ns. Failsafe watchdog + 244.0 ns. Failsafe watchdog + 488.0 ns. 0x00115 0x00116 Failsafe Enable Failsafe Sensitivity 7:0 7:0 FSEER FSSSR 0x00118 0x00119 0x0011A OOL Threshold Low OOL Threshold High OOL Monitor 7:0 7:0 7:0 OLLLR OLHLR OOLER LLLL LLLL Failsafe threshold value, low byte. LLLL LLLL Failsafe threshold value, high byte. 0000 0000 Monitor direct APLL1 lock detect at PLOCK. 0000 0001 Monitor user threshold lock detect at PLOCK. The failsafe control register controls a return from the failsafe state. Writes to the failsafe control register trigger the corresponding action, and the set bit(s) are automatically cleared. From the failsafe state, the user can return to either the primary or secondary clock register sets. For more on failsafe, please see Section 6.7.2 on page 70. The failsafe enable register controls the enable/disable of failsafe operation. For more on failsafe operation, please see Section 6.7.2 on page 70. The failsafe sensitivity register allows the failsafe watchdog timer to be desensitized by either 1, 4, 8, or 16 watchdog sample clock periods. The OOL threshold registers allow for programmable threshold times which indicate the APLL1 out-of-lock. Resolution for the threshold value increments is one 32.768 MHz clock period (30.5 ns). The register contains [count – 1], a value of 0x0000 yields a 30.5 ns threshold. A value of 0xFFFF yields a 1.99 ms threshold. For more on OOL operation, please see Section 6.7.2 on page 70. The OOL monitor register allows the user to monitor either the raw APLL1 out-of-lock status, OR the status flag that indicates that the APLL1 has been out-of-lock for more than the threshold defined in the OOL threshold registers. 38 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.2 Error and Status Registers Status 7, 6, and 3—0 registers are writable by the user for clearing specific error bits. Writing a 1 to any of the bits of these registers will clear the corresponding error bit. The remaining error and status registers are read-only. Table 27. Error and Status Register Map DWORD Address (20 bits) 0x00120 0x00124 0x00128 0x0012C Register Byte 3 Byte 2 Byte 1 Status 1, transient clock errors, upper Reserved Reserved Reserved Byte 0 Status 0, transient clock errors, lower Status 4 fallback and failsafe status Version ID Reserved Status 3, latched clock Status 2, latched clock errors, upper errors, lower Status 7, system errors Device ID, upper Reserved Reserved Device ID, lower Reserved Agere Systems Inc. 39 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status (continued) 5.2 Error and Status Registers (continued) 5.2.1 Clock Errors 5.2.1.1 Transient Clock Errors Registers The transient clock error registers are used in conjunction with the watchdog EN registers and indicate error status for H-bus clocks and DPLL1/DPLL2 sync inputs whose watchdogs are enabled. The transient indicators are dynamic in nature; if a clock is in error only for a short time and then recovers, the error indication is deasserted when the clock recovers. Additionally, an APLL1 out-of-lock indicator is provided, and used in conjunction with the failsafe clocking mode. For more details, please see Section 6.7.1 on page 64 and Section 6.7.2 on page 70. Table 28. Clock Error Registers Byte Address 0x00120 Name Status 0, Transient Clock Errors, Lower Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x00121 Status 1, Transient Clock Errors, Upper 7 6 5 4 3 2 1 0 S2TOB SCTOB C2TOB C4TOB CMTOB CPTOB CBTOB CATOB FSTOB D2TOB D1TOB N2TOB N1TOB FCTOB FBTOB FATOB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function /SCLKx2 no error (default). /SCLKx2 error. SCLK no error (default). SCLK error. C2 no error (default). C2 error. /C4 no error (default). /C4 error. /C16– no error (default). /C16– error. /C16+ no error (default). /C16+ error. CT_C8_B no error (default). CT_C8_B error. CT_C8_A no error (default). CT_C8_A error. Failsafe indicator: APLL1 reference no error. APLL1 reference error. DPLL2 sync no error (default). DPLL2 sync error. DPLL1 sync no error (default). DPLL1 sync error. CT_NETREF2 no error (default). CT_NETREF2 error. CT_NETREF1 no error (default). CT_NETREF1 error. /FR_COMP no error (default). /FR_COMP error. /CT_FRAME_B no error (default). /CT_FRAME_B error. /CT_FRAME_A no error (default). /CT_FRAME_A error. 40 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.2 Error and Status Registers (continued) 5.2.1 Clock Errors (continued) 5.2.1.2 Latched Clock Error Register The latched clock error registers capture transient clock errors. The latched indicators capture and hold any transient error status and are used by the clock fallback logic. For more details, see Section 6.7 on page 64, and Section 10 on page 90 for more details. Table 29. Latched Clock Error Registers Byte Address Name Bit(s) 7 6 5 4 3 2 1 0 0x00123 Status 3, Latched Clock Errors, Upper 7 6 5 4 3 2 1 0 Mnemonic Value S2LOB SCLOB C2LOB C4LOB CMLOB CPLOB CBLOB CALOB FSLOB D2LOB D1LOB N2LOB N1LOB FCLOB FBLOB FALOB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function /SCLKx2 no error (default). /SCLKx2 error. SCLK no error (default). SCLK error. C2 no error (default). C2 error. /C4 no error (default). /C4 error. /C16– no error (default). /C16– error. /C16+ no error (default). /C16+ error. CT_C8_B no error (default). CT_C8_B error. CT_C8_A no error (default). CT_C8_A error. Failsafe indicator: APLL1 reference no error. APLL1 reference error. DPLL2 sync no error (default). DPLL2 sync error. DPLL1 sync no error (default). DPLL1 sync error. CT_NETREF2 no error (default). CT_NETREF2 error. CT_NETREF1 no error (default). CT_NETREF1 error. /FR_COMP no error (default). /FR_COMP error. /CT_FRAME_B no error (default). /CT_FRAME_B error. /CT_FRAME_A no error (default). /CT_FRAME_A error. 0x00122 Status 2, Latched Clock Errors, Lower Agere Systems Inc. 41 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 5 Operating Control and Status (continued) 5.2 Error and Status Registers (continued) 5.2.2 System Status 5.2.2.1 Clock Fallback Status Register The upper nibble provides status indicators for clock fallback. FBFOB indicates whether the circuit is in a clock fallback state. FBSOP indicates which of five possible states the circuit is in; see Section 6.7.1 on page 64 for more details. The lower nibble provides status indicators related to the X and Y clock register set active/inactive assignments. XYSOB indicates which of the clock register sets is active. The remaining bits indicate a pending status for GO_CLOCKS, CLEAR_FALLBACK, and FORCE_FALLBACK commands issued (via the fallback control register, 0x00108), which are waiting for a frame sync. Table 30. Fallback and Failsafe Status Register Byte Address Register Name Bit(s) Mnemonic Value 7 6:4 FBFOB FBSOP 0 1 111 000 001 010 011 100 101 0 1 0 1 0 1 0 1 Function Indicates not in fallback/failsafe state (default). Indicates fallback/failsafe state. Fallback state = INITIAL (default). Fallback state = PRIMARY. Fallback state = TO_PRIMARY. Fallback state = SECONDARY. Fallback state = TO_SECONDARY. Failsafe state = FS_1. Failsafe state = FS_2. Clock register Y set is active, X is inactive. Clock register X set is active, Y is inactive. No GO_CLOCKS pending (default). GO_CLOCKS pending, waiting for frame. No CLEAR_FALLBACK pending (default). CLEAR_FALLBACK pending, waiting for frame. No FORCE_FALLBACK pending (default). FORCE_FALLBACK pending, waiting for frame. 0x00124 Status 4, Clock Fallback Status 3 2 1 0 XYSOB GOPOB CFPOB FFPOB 42 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 5 Operating Control and Status (continued) 5.2 Error and Status Registers (continued) 5.2.2 System Status (continued) 5.2.2.2 Device Identification Registers Table 31. System Errors Registers Byte Address Register Name Bit(s) Mnemonic 7 6 5:0 5.2.2.3 System Device Errors These registers identify the device type and revision status, T8110L revision n. Table 32. Device Identification Registers Byte Address Name Bit(s) Mnemonic 7:0 7:0 7:0 VEROR IDLOR IDHOR Value Function CFSOB CFBOB Reserved Value 0 1 0 1 0 Function No error. Clock failsafe indicator. No error. Clock fallback indicator. NOP. 0x00127 Status 7, System Errors 0x00128 Version ID 0x0012A Device ID, Lower 0x0012B Device ID, Upper 0000 0001 Revision status (value shown = REV1). 0001 0000 Device ID low status 0x10. 1000 0001 Device ID high status 0x81. Agere Systems Inc. 43 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture WATCHDOGS /CT_FRAME_A /CT_FRAME_B /FR_COMP LREF[4:7] PROGRAMMABLE INVERSION LREF[0:7] CT_NETREF1 CT_NETREF2 CT_C8_A CT_C8_B MVIP (2 CLOCKS) H-MVIP (4 CLOCKS) SC-BUS (2 CLOCKS) SCSA (2 CLOCKS) BIT SLIDER CONTROLS FRAME SEL WATCHDOG PHASE ALIGNMENT 2.048 MHz 4.096 MHz 8.192 MHz 16.364 MHz FRAME 32.768 MHz (INTERNAL) FRAME MEMORIES SAMPLED FRAME SYNC DPLL1 SOURCE AND RATE 2 OR 4 MHz DPLL1 65.536 MHz APLL1 BYPASS FAIL SAFE CLOCK SOURCE SELECT MULT BY 2 WATCHDOG 4 CLOCK SELECT 8 INTERNAL CLOCK GENERATION RESOURCE DIVIDE-BY-n DIVIDE REGISTER MAIN DIVIDE-BY-n DIVIDE REGISTER APLL1 65.536 MHz WATCHDOGS CLK SEL PROG. INVERSION FRAME TO TCLK_OUT MUX DPLL2 1, 5, 3, 6, or 12 MHz APLL2 49.408 MHz X4 X8 DIV BY 4 OSC1 DPLL2 SOURCE AND RATE PRI_REF_OUT PRI_REF_IN APLL2 BYPASS APLL2 RATE SELECT XTAL2 OUT OSC2 XTAL1 OUT XTAL1 IN/ OSC1 IN XTAL2 IN/ OSC2 IN 5-9432 (F) Figure 5. T8110L Main Clocking Paths NR1_SEL_OUT PROGRAMMABLE INVERSION CT_NETREF2 NETREF1 SEL DIV BY 8 8 NR1 SOURCE SELECT NR2 SOURCE SELECT NETREF2 SEL CT_NETREF1 PROGRAMMABLE INVERSION NR2_SEL_OUT NR1_DIV_IN PROGRAMMABLE INVERSION NETREF1 DIVIDE-BY-n NR1 DIV SELECT DIVIDE REGISTER CT_NETREF1 (FROM XTAL2) (FROM XTAL1) LREF[0:7] NR2 DIV SELECT NETREF2 DIVIDE-BY-n DIVIDE REGISTER PROGRAMMABLE INVERSION CT_NETREF2 NR2_DIV_IN 5-9433 (F) Figure 6. T8110L NETREF Paths 44 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.1 Clock Input Control Registers The following registers control the T8110L main clocking paths and NETREF paths. Table 33. Clock Input Control Register Map DWORD Address (20 Bits) 0x00200 0x00204 0x00208 0x0020C 0x00210 0x00214 Register Byte 3 APLL1 rate APLL2 rate DPLL1 rate DPLL2 rate Reserved Reserved Byte 2 APLL1 input selector Reserved DPLL1 input selector DPLL2 input selector NETREF1 LREF select NETREF2 LREF select Byte 1 Main divider Resource divider Reserved Reserved NETREF1 divider NETREF2 divider Byte 0 Main input selector Main inversion select LREF input select LREF inversion select NETREF1 input selector NETREF2 input selector 6.1.1 Main Input Selector Register The main input selector register controls clock and frame input selection. Table 34. Main Input Selector Register Byte Address 0x00200 Name Main Input Selector Bit(s) 7:0 Mnemonic CKMSR Value 0000 0000 0001 0001 0001 0010 0010 0001 0010 0010 0100 0001 0100 0010 0100 0100 0100 1000 1000 0000 1000 0001 1000 0010 1000 0100 1000 1000 Function Select oscillator/crystal (default). Select NETREF1. Select NETREF2. Select LREF[0:7] individually. Select LREF[0:3, 4:7] paired. Select H-bus A-clocks. Select H-bus B-clocks. Select MC1 R-clocks. Select MC1 L-clocks. Select MVIP clocks (C2 bit clock)*. Select MVIP clocks (/C4 bit clock). Select H-MVIP clocks (/C16± bit clock). Select SC-bus clocks 2 MHz. Select SC-bus clocks 4/8 MHz. * C2 is allowed as the bit clock input. Choices include the following: Oscillator/crystal clock = XTAL1_IN (16.384 MHz), no frame NETREF1 clock = CT_NETREF1 (8 kHz, 1.544 MHz, or 2.048 MHz), no frame NETREF2 clock = CT_NETREF2 (8 kHz, 1.544 MHz, or 2.048 MHz), no frame LREF individual clock = one of LREF[0:7]*, no frame LREF paired clock = one of LREF[0:3] (2.048 MHz), frame = one of LREF[4:7]* H-bus A-clocks clock = CT_C8_A (8.192 MHz), frame = /CT_FRAME_A (8 kHz) * Selection of which LREF is controlled at register 0x00208. Selection of LREF polarity is controlled at register 0x0020C. Agere Systems Inc. 45 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) H-bus B-clocks clock = CT_C8_B (8.192 MHz), frame = /CT_FRAME_B (8 kHz) MC1 R-clocks clock = inverted CT_C8_A (4.096 MHz), frame = /CT_FRAME_A (8 kHz) MC1 L-clocks clock = inverted CT_C8_B (4.096 MHz), frame = /CT_FRAME_B (8 kHz) MVIP clocks clock = /C4 (4.096 MHz), frame = /FR_COMP (8 kHz) MVIP clocks* clock = C2 (2.048 MHz), frame = /FR_COMP (8 kHz) H-MVIP clocks clock = /C16± (16.384 MHz), frame = /FR_COMP (8 kHz) SC-BUS 2 MHz clock = /SCLKx2, frame = /FR_COMP (8 kHz) SC-BUS 4/8 MHz clock = SCLK, frame = /FR_COMP (8 kHz) * C2 is allowed as the bit clock input. 6.1.2 Main Divider Register The main divider register contains [divider value – 1]. A value of 0x00 yields a divide-by-1 function. A value of 0xFF yields a divide-by-256 function. Table 35. Main Divider Register Byte Address Name Bit(s) Mnemonic 7:0 CKMDR Value LLLL LLLL Function Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively. 0x00201 Main Divider 6.1.3 Analog PLL1 (APLL1) Input Selector Register The APLL1 input selector register controls APLL1 reference input selection. The choices include the following: ! ! ! ! ! APLL1 reference clock = oscillator/4 (4.096 MHz) APLL1 reference clock = output of the main divider (4.096 MHz or 2.048 MHz) APLL1 reference clock = output of the resource divider (4.096 MHz or 2.048 MHz) APLL1 reference clock = output of DPLL1 (4.096 MHz or 2.048 MHz) APLL1 reference clock = input from signal PRI_REF_IN (4.096 MHz or 2.048 MHz) Table 36. APLL1 Input Selector Register Byte Address Name Bit(s) Mnemonic 7:0 P1ISR Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 Function Select oscillator/4 (default). Select main divider output. Select resource divider output. Select DPLL1 output. Select external input PRI_REF_IN. 0x00202 APLL1 Input Selector 46 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) 6.1.4 APLL1 Rate Register The APLL1 rate register provides the rate multiplier value to APLL1. When APLL1 reference clock is at 4.096 MHz, the [x16 (multiplied by)] value must be selected. When APLL1 reference clock is at 2.048 MHz, the [x32 (multiplied by)] value must be selected. A [x1 (multiplied by)] value is provided in order to bypass APLL1. Table 37. APLL1 Rate Register Byte Address Name Bit(s) Mnemonic 7:0 P1RSR Value 0000 0000 0000 0001 0001 xxxx Function Times 16 (default). Times 32. Times 1 BYPASS (lower nibble is don't care). 0x00203 APLL1 Rate 6.1.5 Main Inversion Select Register The main inversion select register controls programmable inversions at various points within the T8110L main clocking paths and NETREF paths. Internal points allowed for programmable inversion include the following: ! ! ! ! ! Main clock selection CLK SEL MUX output; see Figure 5 on page 44. NETREF2 divider output; see Figure 6 on page 44. NETREF2 selection MUX output. NETREF1 divider output. NETREF1 selection MUX output. Table 38. Main Inversion Select Register Byte Address Name Bit(s) Mnemonic 7:5 4 3 2 1 0 Reserved ICMSB N2DSB N2SSB N1DSB N1SSB Value 000 0 1 0 1 0 1 0 1 0 1 NOP (default). Don't invert main clock selection (default). Invert main clock selection. Don't invert NETREF2 divider output (default). Invert NETREF2 divider output. Don't invert NETREF2 selection (default). Invert NETREF2 selection. Don't invert NETREF1 divider output (default). Invert NETREF1 divider output. Don't invert NETREF1 selection (default). Invert NETREF1 selection. Function 0x00204 Main Inversion Select Agere Systems Inc. 47 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) 6.1.6 Resource Divider Register The resource divider register contains [divider value – 1]. A value of 0x00 yields a divide-by-1 function. A value of 0xFF yields a divide-by-256 function. Table 39. Resource Divider Register Byte Address 0x00205 Name Resource Divider Bit(s) Mnemonic 7:0 CKRDR Value Function LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively. 6.1.7 Analog PLL2 (APLL2) Rate Register The APLL2 rate register provides the rate multiplier value to APLL2. When the APLL2 reference clock is at 12.352 MHz, the (times 4) value must be selected. When the APLL2 reference clock is at 6.176 MHz, the (times 8) value must be selected. A (times 1) value is provided in order to bypass APLL2. Table 40. APLL2 Rate Register Byte Address Name Bit(s) Mnemonic 7:0 P2RSR Value 0000 0000 0000 0001 0001 xxxx Function Times 4 (default). Times 8. Times 1 BYPASS (lower nibble is don't care). 0x00207 APLL2 Rate 48 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) 6.1.8 LREF Input Select Registers The LREF input select register is used in conjunction with the main input selector (0x00200) and provides the selection control among the eight LREF inputs when the main selection is set for either individual or paired LREFs. The LREF inversion select register allows programmable inversion for each LREF input. Please refer to Section 6.4.1.3 on page 60 for further details. Table 41. LREF Input/Inversion Select Registers Byte Address Name Bit(s) Mnemonic 7:0 LRISR Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 0001 0001 0010 0010 0100 0100 1000 1000 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Select LREF0 (default). Select LREF0. Select LREF1. Select LREF2. Select LREF3. Select LREF4. Select LREF5. Select LREF6. Select LREF7. Select paired, clock = LREF0, frame = LREF4. Select paired, clock = LREF1, frame = LREF5. Select paired, clock = LREF2, frame = LREF6. Select paired, clock = LREF3, frame = LREF7. Don't invert LREF7 (default). Invert LREF7. Don't invert LREF6 (default). Invert LREF6. Don't invert LREF5 (default). Invert LREF5. Don't invert LREF4 (default). Invert LREF4. Don't invert LREF3 (default). Invert LREF3. Don't invert LREF2 (default). Invert LREF2. Don't invert LREF1 (default). Invert LREF1. Don't invert LREF0 (default). Invert LREF0. 0x00208 LREF Input Select 0x0020C LREF Inversion Select 7 6 5 4 3 2 1 0 IR7SB IR6SB IR5SB IR4SB IR3SB IR2SB IR1SB IR0SB Agere Systems Inc. 49 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) 6.1.9 DPLL1 Input Selector The DPLL1 input selector selects one of three sources for DPLL1 synchronization input (see Section 6.4.2 on page 61), including the following: ! ! ! Main clock selection CLK SEL MUX output Main divider output Resource divider output 6.1.9.1 DPLL1 Rate Register The DPLL1 rate register controls the DPLL1 output frequency. Table 42. DPLL1 Input Selector Registers Byte Address Name Bit(s) Mnemonic 7:0 D1ISR Value Function 0x0020A DPLL1 Input Selector 0000 0000 Main selector (default). 0000 0001 Main divider. 0000 0010 Resource divider. 0000 0000 DPLL1 output at 4.096 MHz (default). 0000 0001 DPLL1 output at 2.048 MHz. 0x0020B DPLL1 Rate 7:0 D1RSR 6.1.10 DPLL2 Input Selector The DPLL2 input selector selects one of five sources for DPLL2 synchronization input (see Section 6.5.1 on page 63), including the following: ! ! ! ! ! Main clock selection CLK SEL MUX output Main divider output Resource divider output Internal frame External input via PRI_REF_IN signal 50 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) 6.1.10 DPLL2 Input Selector (continued) 6.1.10.1 DPLL2 Rate Register The DPLL2 rate register controls the DPLL2 output frequency. Table 43. DPLL2 Register Byte Address Name Bit(s) Mnemonic 7:0 D2ISR Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 Function Main selector (default). Main divider. Resource divider. T8110L internally generated frame. External input PRI_REF_IN. DPLL2 output off (default). DPLL2 output at 1.544 MHz. DPLL2 output at 3.088 MHz. DPLL2 output at 6.176 MHz. DPLL2 output at 12.352 MHz. 0x0020E DPLL2 Input Selector 0x0020F DPLL2 Rate 7:0 D2RSR 6.1.11 NETREF1 Registers The NETREF1 input selector, NETREF1 divider, and NETREF1 LREF select registers control the signal paths used to generate CT_NETREF1 (see Figure 6 on page 44). Table 44. NETREF1 Registers Byte Address 0x00210 Name NETREF1 Input Selector Bit(s) Mnemonic 7:4 3:0 N1DSN N1ISN Value 0000 0001 0000 0001 0010 0100 1000 Function Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. CT_NETREF2 input. LREF input*. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz. 0x00211 0x00212 NETREF1 Divider NETREF1 LREF Select 7:0 7:0 NR1DR N1LSR LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Select LREF0 (default). Select LREF0. Select LREF1. Select LREF2. Select LREF3. Select LREF4. Select LREF5. Select LREF6. Select LREF7. * Selection of which LREF is controlled at register 0x00212. Agere Systems Inc. 51 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.1 Clock Input Control Registers (continued) 6.1.12 NETREF2 Registers The NETREF2 input selector, NETREF2 divider, and NETREF2 LREF select registers control the signal paths used to generate CT_NETREF2 (see Figure 6 on page 44). Table 45. NETREF2 Registers Byte Address Name Bit(s) Mnemonic 7:4 3:0 N2DSN N2ISN Value 0000 0001 0000 0001 0010 0100 1000 Function Divider input = selector output (default). Divider input = external input NR1_DIV_IN. Oscillator/XTAL1-div-8, 2.048 MHz (default). Oscillator/XTAL1, 16.384 MHz. CT_NETREF1 input. LREF input*. Oscillator/XTAL2, 6.176 MHz, or 12.352 MHz. 0x00214 NETREF2 Input Selector 0x00215 NETREF2 Divider 0x00216 NETREF2 LREF Select 7:0 7:0 NR2DR N2LSR LLLL LLLL Divider value, {0x00 to 0xFF} = {div1 to div256}, respectively. 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 Select LREF0 (default). Select LREF0. Select LREF1. Select LREF2. Select LREF3. Select LREF4. Select LREF5. Select LREF6. Select LREF7. * Selection of which LREF is controlled at register 0x00216. 52 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.2 Clock Output Control Registers The registers listed below control output enable and rate selection of the T8110L clock path outputs. Table 46. Clock Output Control Register Map DWORD Address (20 Bits) 0x00220 0x00224 0x00228 Register Byte 3 C8 output rate SCLK output rate L_SC3 select Byte 2 /FR_COMP width TCLK select L_SC2 select Byte 1 NETREF output enables Reserved L_SC1 select Byte 0 Master output enables CCLK output enables L_SC0 select 6.2.1 Master Output Enables Register The master output enables register controls the output enables for H-bus and compatibility clocks (CCLK) for T8110L clock mastering. A-clocks refers to the combination of CT_C8_A bit clock and /CT_FRAME_A frame reference. B-clocks refers to the CT_C8_B bit clock and /CT_FRAME_B frame reference. These programmable enables are used in conjunction with master enable register 0x00103, H-bus clock enables, HCKEB. The NETREF output enables register controls the output enables for CT_NETREF1 and CT_NETREF2. These programmable enables are used in conjunction with master enable register 0x00103, H-bus clock enables, HCKEB. The CCLK output enables register is used in conjunction with register 0x00220 and controls the output enables for various groupings of compatibility clocks, including the following: ! ! ! ! ! H-MVIP bit clock only(/C16±) MVIP clocks (/C4, C2) H-MVIP clocks (/C16±, /C4, C2) SC-bus clocks (SCLK, /SCLKx2) /FR_COMP compatibility frame reference Agere Systems Inc. 53 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.2 Clock Output Control Registers (continued) 6.2.1 Master Output Enables Register (continued) Table 47. Master Output Enables Registers Byte Address 0x00220 Name Master Output Enables Bit(s) Mnemonic 7:4 ABOEN Value 0000 0001 0010 0011 0000 0001 0010 0000 0001 0000 0001 0000 0001 0000 0001 0010 0011 0100 Function Disable A and B clock outputs (default). Enable A clock outputs only. Enable B clock outputs only. Enable both A and B clock outputs. Disable compatibility (C clock) outputs (default). Enable C clocks individually*. Enable all C clocks. CT_NETREF2 disabled (default). CT_NETREF2 enabled. CT_NETREF1 disabled (default). CT_NETREF1 enabled. /FR_COMP disabled (default). /FR_COMP enabled. C-clock bit clocks disabled (default). Enable H-MVIP bit clock. Enable MVIP clocks. Enable H-MVIP all clocks. Enable SC-bus clocks. 3:0 CCOEN 0x00221 NETREF Output Enables CCLK Output Enables 7:4 3:0 7:4 3:0 N2OEN N1OEN FRSEN CCSEN 0x00224 * Overall selection includes all C clocks OFF, all C clocks ON, or select individual groups of C clocks to be enabled, in conjunction with register 0x00224. 6.2.2 Clock Output Format Registers The clock output format registers select the pulse width of the /FR_COMP pulse width. Note: When the T8110L is slowing to a compatibility bus, the /FR_COMP signal must be 122 ns. The T8110L cannot phase align to a 244 ns /FR_COMP signal. The C8 output rate register selects the CT_C8_A and CT_C8_B clock output frequency 8.192 MHz for ECTF (H1x0) mode, or 4.096 MHz for MC1 mode. The SCLK output rate register selects between three SC-Bus clock configurations, including the following: ! ! ! SCLK = 2.048 MHz, /SCLKx2 = 4.096 MHz SCLK = 4.096 MHz, /SCLKx2 = 8.192 MHz SCLK = 8.192 MHz, /SCLKx2 = 8.192 MHz (phase shifted from SCLK) 54 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.2 Clock Output Control Registers (continued) 6.2.2 Clock Output Format Registers (continued) Table 48. Clock Output Format Registers Byte Address Name Bit(s) Mnemonic 7:0 7:4 3:0 0x00227 SCLK Output Rate 7:0 FRWSR BCRSN ACRSN SCRSR Value Function 0x00222 /FR_COMP Width 0x00223 C8 Output Rate 0000 0000 /FR_COMP width is 122 ns (default). 0000 0001 /FR_COMP width is 244 ns. 0000 0001 0000 0001 CT_C8_B output at 8.192 MHz (default). CT_C8_B output at 4.096 MHz, MC1 mode. CT_C8_A output at 8.192 MHz (default). CT_C8_A output at 4.096 MHz, MC1 mode. 0000 0000 SCLK = 2 MHz, /SCLKx2 = 4 MHz (default). 0000 0001 SCLK = 4 MHz, /SCLKx2 = 8 MHz. 0000 0010 SCLK = 8 MHz, /SCLKx2 = 8 MHz phase shifted. 6.2.3 TCLK and L_SCx Select Registers The TCLK select register controls the selection of various internally generated clocks for output to the TCLK_OUT signal. The L_SCx select registers control the selection of various internally generated clocks for output to the L_SC0, L_SC1, L_SC2, and L_SC3 signals. Agere Systems Inc. 55 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.2 Clock Output Control Registers (continued) 6.2.3 TCLK and L_SCx Select Registers (continued) Table 49. TCLK Select and L_SCx Select Registers Byte Address 0x00226 Name TCLK Select Bit(s) Mnemonic 7:0 TCOSR Value 0000 0000 0000 0001 0000 0010 0001 0001 0001 0010 0010 0000 0010 0001 0010 0010 0011 0000 0011 0001 0011 0010 0100 0000 0100 0001 0100 0010 0100 0100 0100 1000 0101 0000 0101 0001 0101 0010 0101 0100 0101 1000 1000 0000 1000 0001 1000 0010 1001 0000 1001 0001 1001 0010 0000 0000 0000 0001 0001 0001 0100 0000 0100 0001 0100 0010 0100 0100 0100 1000 0101 0000 0101 0001 0101 0010 0101 0100 0101 1000 1000 0000 1000 0001 1000 0010 1001 0000 1001 0001 1001 0010 Function TCLK output disabled (default). Select OSC1/XTAL1. Select OSC2/XTAL2. Select OSC1/XTAL1 inverted. Select OSC2/XTAL2 inverted. Select DPLL2 output. Select APLL1 output, 65.536 MHz. Select APLL2 output, 49.704 MHz. Select DPLL2 output inverted. Select APLL1 output inverted. Select APLL2 output inverted. Select generated 2.048 MHz. Select generated 4.096 MHz. Select generated 8.192 MHz. Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. select generated 32.768 MHz inverted. Select generated frame. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted. L_SCx output disabled (default). Select OSC1/XTAL1. Select OSC1/XTAL1 inverted. Select generated 2.048 MHz. Select generated 4.096 MHz. Select generated 8.192 MHz. Select generated 16.384 MHz. Select generated 32.768 MHz. Select generated 2.048 MHz inverted. Select generated 4.096 MHz inverted. Select generated 8.192 MHz inverted. Select generated 16.384 MHz inverted. Select generated 32.768 MHz inverted. Select generated frame. Select generated CT_NETREF1. Select generated CT_NETREF2. Select generated frame inverted. Select generated CT_NETREF1 inverted. Select generated CT_NETREF2 inverted. Agere Systems Inc. 0x00228 (0x00229) (0x0022A) (0x0022B) L_SC0 Select L_SC1 Select L_SC2 Select L_SC3 Select 7:0 LC0SR (LC1SR) (LC2SR) (LC3SR) 56 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.3 Clock Register Access The T8110L clock control registers, 0x00200—0x002FF, consist of two identical sets of registers, X and Y. At any given time, only one set is actually controlling the clocking (denoted as the active set), while the other is in a standby state (inactive set). Either set, X or Y, may be the active set, as determined by a state machine that tracks the clock fallback control and status and assigns either set to be active accordingly. For more details, see Section 6.7.1 on page 64. Users may only access one register set at a time. By default, access is allowed to the current inactive set, but access to the active set is allowed via the clock register access select register, 0x00106; see Section 5.1.4 on page 33. 6.4 Clock Circuit Operation—APLL1 APLL1 can accept either a 4.096 MHz or 2.048 MHz reference clock, and perform a corresponding multiplication function to supply a 65.536 MHz operating clock for the T8110L. Additionally, APLL1 may be bypassed for circuit diagnostic purposes. Please refer to Figure 5 on page 44. 6.4.1 Main Clock Selection, Bit Clock, and Frame APLL1 clock references are selectable as stand-alone bit clocks, frames, or a pairing of bit clock and frame (see main input selector register, 0x00200). The bit clock output of the main clock selection is available as input to the main divider, resource divider, and DPLL1. Table 50. Bit Clock and Frame Bit Clock CT_NETREF1, CT_NETREF2 NA CT_C8_A CT_C8_B /C16± /C4 C2 SCLK /SCLKx2 LREF[0] LREF[1] LREF[2] LREF[3] LREF[4] LREF[5] LREF[6] LREF[7] Corresponding 8 kHz Frame — CT_NETREF1, CT_NETREF2 /CT_FRAME_A /CT_FRAME_B /FR_COMP /FR_COMP /FR_COMP /FR_COMP /FR_COMP LREF[4]† LREF[5]† LREF[6]† LREF[7]† — — — — Value(s) 1.544 MHz (T1), 2.048 MHz (E1) 8 kHz 8.192 MHz (ECTF), 4.096 MHz (MC1) 8.192 MHz (ECTF), 4.096 MHz (MC1) 16.384 MHz (H-MVIP) 4.096 MHz (MVIP) 2.048 MHz (MVIP*) 2.048 MHz, 4.096 MHz, 8.192 MHz (SC-bus) 4.096 MHz, 8.192 MHz (SC-bus) System-specific System-specific System-specific System-specific System-specific System-specific System-specific System-specific * MVIP, /C4 is typically the bit clock. C2 is selectable as the bit clock as well. † Used when LREF pairing is enabled. When using LREF pairing, the bit clock should be 2.048 MHz. Agere Systems Inc. 57 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.4 Clock Circuit Operation—APLL1 (continued) 6.4.1 Main Clock Selection, Bit Clock, and Frame (continued) 6.4.1.1 Watchdog Timers A set of watchdog timers is available for all H1x0, H-MVIP, MVIP, and SC-bus clocks. No watchdogs are available for LREF[7:0] directly; however, the LREF inputs may be monitored indirectly via watchdogs on the DPLL1 and DPLL2 sync inputs, or via the failsafe mechanism; see Section 6.7.2 on page 70. The watchdogs sample the incoming clocks at 32.768 MHz (derived from the XTAL1 crystal) and monitor for loss of signal, as shown below. Table 51. Watchdog Timer Description Watchdog H1x0 clock monitors* Signal, Value CT_C8_A at 8.192 MHz CT_C8_B at 8.192 MHz CT_C8_A at 4.096 MHz CT_C8_B at 4.096 MHz FRAME monitors /CT_FRAME_A /CT_FRAME_B /FR_COMP Description ECTF mode. Checks for CT_C8 rising edge within a 35 ns window of its expected arrival. MC1 mode. Monitors for loss of signal (falling edges). Monitors for 8 kHz frequency. Detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early). NETREF monitors* CT_NETREF1 at 1.544 MHz NETREF is T1 bit clock. Monitors for loss of signal CT_NETREF2 at 1.544 MHz (rising or falling edges). CT_NETREF1 at 2.048 MHz NETREF is E1 bit clock. Monitors for loss of signal CT_NETREF2 at 2.048 MHz (rising or falling edges). CT_NETREF1 at 8 kHz CT_NETREF2 at 8 kHz NETREF is 8 kHz frame reference. Monitors for 8 kHz frequency. Detects frame overflow (i.e., next frame pulse too late) and frame underflow (i.e., next frame pulse too early). Gross loss-of-signal detector—clocks are sampled and normalized to 1.024 MHz. It can take up to 976 ns for these watchdog timers to detect loss of a compatibility clock. Compatibility clock monitors /C16± at 16.384 MHz /C4 at 4.096 MHz C2 at 2.048 MHz SCLK, /SCLKx2 at any of their defined values. DPLL1, DPLL2 sync monitors † Output of MUX selector to the Monitors for 8 kHz frequency. Detects frame overflow SYNC input of each (i.e., next frame pulse too late) and frame underflow DPLL (8 kHz) (i.e., next frame pulse too early). * User selects frequency at which to monitor the CT_C8 clocks via register 0x0010C, watchdog select, C8. † DPLL sync reference is expected to be 8 kHz. 58 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.4 Clock Circuit Operation—APLL1 (continued) 6.4.1 Main Clock Selection, Bit Clock, and Frame (continued) 6.4.1.2 Frame Center Sampling Frame center samples are used in order to phase-align the incoming frame reference to the internally generated frame reference; see Section 6.4.5.1 on page 62. The incoming frame reference signal is sampled with a recovered clock (output of the APLL1 feedback divider) to determine the frame center. Frame center sampling is only relevant when the main clock selection is based on a paired bit clock/frame reference, as follows. Table 52. Frame Center Sampling Frame Signal /CT_FRAME_A /CT_FRAME_B /FR_COMP Corresponding Bit Clock CT_C8_A CT_C8_B /C16± (H-MVIP) or /C4 (MVIP) or C2 (MVIP) SCLK or /SCLKx2 (SC-bus) LREF[0] LREF[1] LREF[2] LREF[3] Sample Clock Recovered 8.192 MHz, rising edge. Recovered 8.192 MHz, rising edge. Recovered 4.096 MHz, falling edge. /FR_COMP LREF[4] LREF[5] LREF[6] LREF[7] Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Recovered 2.048 MHz, rising edge. Agere Systems Inc. 59 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.4 Clock Circuit Operation—APLL1 (continued) 6.4.1 Main Clock Selection, Bit Clock, and Frame (continued) 6.4.1.3 LREF Pair Polarity Configuration The T8110L may derive its clocking from an LREF pair, which is compromised of a frame pulse and a 2.048 MHz bit clock. In order to achieve proper phase alignment when deriving clocking from LREF pairs, the T8110L must be provided with a frame pulse and bit clock with polarities as shown below. MASTER FRAME SIGNAL MAY BE EITHER 122 NS OR 244 NS WIDE. FRAME CENTER MASTER FRAME (LREF 7/6/5/4) MASTER BIT CLOCK (LREF 3/2/1/0) SLAVE FRAME THE OUTPUT FRAME SIGNAL LENGTH IS PROGRAMMABLE. (SEE SECTION 8 OF THE T8110 DATA SHEET.) Figure 7. T8110L Required Frame Pulse and Bit Clock with Polarities If the frame pulse and bit clock cannot be externally provided with the proper polarities, the polarities can be internally adjusted via the main inversion select register (0x204) and the LREF inversion select register (0x20C). The main inversion select register will allow inversion of only the bit clock, while the LREF inversion select register allows any LREF signal to be inverted. Note: Once the frame pulse and bit clock polarity have been properly configured, they must not be changed while the T8110L is deriving clocking from the LREF pair. 60 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.4 Clock Circuit Operation—APLL1 (continued) 6.4.2 Main and Resource Dividers Two independently programmable dividers are available to divide down the main clock selection signal. The function ranges from divide-by-1 (bypass) to divide-by-256. ! ! For binary divider values of 1, 2, 4, 8, 16, 32, 64, 128, and 256, the output is 50% duty cycle. For a divider value of 193, the output is almost 50% duty cycle (low-level duration is one clock cycle shorter than high-level duration). For all other divider values, the output is a pulse whose width is one full period of the main clock selection signal. ! Output of both dividers is available to the DPLL1 and the APLL1 reference selector. The output of the main divider is also available at the PRI_REF_OUT chip output. Both dividers are reset whenever a changeover between X and Y clock register sets is detected; see Section 6.3 on page 57. This allows for immediate loading of the newly activated divider register values. 6.4.3 DPLL1 A digital phase-lock loop is provided to generate a 4.096 MHz or 2.048 MHz reference to APLL1, selectable via register 0x0020B (DPLL1 rate). The DPLL1 operates at 32.768 MHz, derived from the XTAL1 crystal input. The DPLL1 synchronization source is selectable (register 0x0020A, DPLL1 input selector) between the main clock selection signal, the output of the resource divider, or the output of the main divider, and is intended to be presented as an 8 kHz frame reference. DPLL1 is determined to be in-lock or out-of-lock, based on the state of the output clock when an edge transition is detected at the synchronization source. An out-of-lock condition results in a DPLL1 correction, which can either lengthen or shorten its current output clock period by 30.5 ns. 6.4.4 Reference Selector The APLL1 reference clock is selectable between five possible sources via register 0x00202, APLL1 input selector. A 4.096 MHz or 2.048 MHz reference must be provided. The five possible sources are shown below: ! ! ! ! ! XTAL1 crystal (16.384 MHz) divided-by-4 Main divider output Resource divider output DPLL1 output PRI_REF_IN external chip input 6.4.5 Internal Clock Generation The main internal functions of T8110L are synchronous to the 65.536 MHz output of APLL1. This clock is further divided to generate 32.768 MHz, 16.384 MHz, and 8 kHz internal reference signals. Additional divide-down values to 8.192 MHz, 4.096 MHz, and 2.048 MHz are generated. These generated clocks are the source for H1x0, H-MVIP, MVIP, and SC-bus clocks when the T8110L is mastering the bus clocks; see Section 6.2 on page 53. These internally generated clocks can either be free-running, or can be aligned to the incoming main selection clock and frame, via a phase alignment circuit (see Section 7.4.5.1). Agere Systems Inc. 61 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.4 Clock Circuit Operation—APLL1 (continued) 6.4.5 Internal Clock Generation (continued) 6.4.5.1 Phase Alignment Phase alignment allows the free-running internally generated clocks to be forced into alignment with the incoming main selection clock and frame, under the following conditions: ! The main selection clock is based on a paired bit clock/frame reference (see Section 6.4.1.2 on page 59), and the phase alignment circuit is enabled (via register 0x00107, phase alignment select). The incoming frame center is monitored via the frame center samplers (see Section 6.4.1.2 on page 59) and compared to the state of the internally generated frame. The circuit determines whether the frame centers are aligned. If not, three possible actions take place as shown below: ! ! NOP: no corrections when phase alignment is disabled. Snap correction: the internally generated clocks and frame immediately snap into alignment with the incoming frame center. Slide correction: the internally generated clocks and frame gradually slide into alignment with the incoming frame center, at a rate of one 65.536 MHz clock period per frame. The sliding occurs in one direction only and creates frame periods that are 15.25 ns longer than 125 µs until the frames are aligned. Please refer to Figure 8. INCOMING FRAME CENTER INCOMING BIT CLOCK CT_C8_A INCOMING FRAME /CT_FRAME_A INTERNAL CLOCK, 8.192 MHz INTERNAL FRAME MISALIGNED INTERNAL FRAME CENTER ! 125 µs INCOMING FRAME CENTER SNAP ALIGNMENT REALIGNED INTERNAL FRAME CENTER 5-9414 (F) A. Phase Alignment—SNAP 125 µs INCOMING BIT CLOCK CT_C8_A INCOMING FRAME /CT_FRAME_A 45 ns INTERNAL CLOCK, 8.192 MHz SLIDE ALIGNMENT INTERNAL FRAME MISALIGNED INTERNAL FRAME CENTER MISALIGNED INTERNAL FRAME CENTER MISALIGNED INTERNAL FRAME CENTER REALIGNED INTERNAL FRAME CENTER 5-9415 (F) 125 µs 125 µs 30 ns 15 ns SLIDE ALIGNMENT SLIDE ALIGNMENT B. Phase Alignment—SLIDE Figure 8. T8110L Phase Alignment, SNAP and SLIDE 62 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.5 Clock Circuit Operation, APLL2 APLL2 requires either a 6.176 MHz or 12.352 MHz reference clock to produce a 49.408 MHz clock for operating DPLL2. A user-supplied rate multiplier (register 0x00207, APLL2 rate) provides either a times 8 function (when reference clock = 6.176 MHz) or a times 4 function (when reference clock = 12.352 MHz). Additionally, APLL2 may be bypassed for circuit diagnostic purposes (see Figure 5 on page 44). 6.5.1 DPLL2 A second digital phase-lock loop is provided to generate various derivations of T1 operating frequencies, available by selection via the TCLK_OUT output. The possible output frequencies are selectable via register 0x0020F (DPLL2 rate) and include 1.544 MHz, 3.088 MHz, 6.176 MHz, and 12.352 MHz. The DPLL2 input clock operates at 49.408 MHz from the APLL2 output. Synchronization sources for DPLL2 include the same sources provided to DPLL1 (selectable between the main clock selection signal, the output of the resource divider, or the output of the main divider) and two additional sources, including the T8110L internally generated frame signal and the PRI_REF_IN input. These selections are available via register 0x0020E, DPLL2 input selector. DPLL2 is determined to be in-lock or out-of-lock based on the state of its output when an edge transition is detected at the synchronization source. An out-of-lock condition results in a DPLL2 correction, which can either lengthen or shorten its current output clock period by 20.2 ns. 6.6 Clock Circuit Operation, CT_NETREF Generation The T8110L provides two independently programmable paths to generate CT_NETREF1 and CT_NETREF2, via registers 0x00210—0x00216. Each CT_NETREF is individually enabled with register 0x00221, NETREF output enables. Each path consists of a source selector MUX and a divider circuit (see Figure 6 on page 44). 6.6.1 NETREF Source Select XTAL1 input DIV 8 (2.048 MHz) XTAL1 input (16.384 MHz) XTAL2 input (6.176 MHz or 12.352 MHz) LREF[7:0] CT_NETREFx (the other NETREF—i.e., CT_NETREF1 can be derived from CT_NETREF2, and vise-versa). The output of the source select MUX is made available directly to the NETREF divider, and also to chip output (NR1_SEL_OUT, NR2_SEL_OUT). 6.6.2 NETREF Divider Each NETREF path provides a divider from a divide-by-1 function up to a divide-by-256 function. The clock source for the divider is selectable between the output of the source select MUX or from external chip input (NR1_DIV_IN, NR2_DIV_IN). ! ! For binary divider values of 1, 2, 4, 8, 16, 32, 64, and 128, output is 50% duty cycle. For divider values of 256, 193, plus all other nonbinary values, output is a pulse whose width is one-half of a clock period, asserted during the second half of the divider clock period. The NETREF dividers are reset whenever a changeover between X and Y clock register sets is detected (see Section 6.3 on page 57). This allows for immediate loading of the newly activated divider register values. Agere Systems Inc. 63 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe Fallback is a means to alter the reference source to APLL1 by switching between two clock control register sets upon detection of a fallback event. Failsafe is a feature to provide a safety net for the reference source to APLL1, independent of clock fallback. 6.7.1 Clock Fallback Clock fallback is a means to alter the APLL1 reference clock source upon detection of a fallback event and is controlled by eight registers, 0x00108—0x0010F (refer to Section 5.1.4 on page 33). These registers enable and control the state transitions that determine which of two clock register sets is used to control the APLL1 reference clock source (see Section 6.1 on page 45 through Section 6.3, Table 54 on page 67, and Figure 10 on page 66). 6.7.1.1 Fallback Events Clock fallback (transition from primary to secondary clock sets) can only occur if the fallback mode is enabled (register 0x00109, lower nibble) and a fallback event occurs. When enabled, there are three ways to trigger the fallback event: ! Software, via a FORCE_FALLBACK command. The user sets bit 2 of the fallback control register, 0x00108, creating a software-invoked fallback event. Hardware via the fallback trigger enable registers, 0x0010A—0x0010B. User may enable specific watchdog timers and corresponding fallback trigger enable bits. If a watchdog timer indicates a clock error, and its corresponding trigger enable bit is set, a hardware-invoked fallback event is produced. Hardware, legacy modes, via the fallback type select register, 0x00109, upper nibble. The legacy modes are included to maintain backwards compatibility with earlier Ambassador devices. User may enable specific watchdog timers, but the fallback trigger enable registers are ignored. Instead, the watchdogs which are allowed to trigger a fallback event are automatically selected based on the state of the main input selector register, 0x00200 (refer to Table 53). If a watchdog timer indicates a clock error, and its corresponding trigger enable is selected via the main input selector, a hardware-invoked fallback event is produced. ! ! 64 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.1 Clock Fallback (continued) 6.7.1.1 Fallback Events (continued) Table 53. Legacy Mode Fallback Event Triggers Main Input Selector Function (Register 0x00200) Oscillator/crystal CT_NETREF1 CT_NETREF LREF, individual LREF, paired H-bus, A clocks H-bus, B clocks MC1, R clocks MC1, L clocks MVIP clocks (/C4 or C2 bit clock) H-MVIP clocks SC-bus clocks (2 MHz or 4/8 MHz) 6.7.1.2 Fallback Scenarios—Fixed vs. Rotating Secondary When clock fallback is enabled (register 0x00109, lower nibble), there are two possible scenarios for transitioning between the primary and secondary clock sets. In a fixed secondary scheme, a fallback event switches the active clock set from primary to secondary. When the fallback event is cleared (via user-invoked CLEAR_FALLBACK), the active clock set returns to primary. In a rotating secondary scheme, a fallback event switches the active clock set from primary to secondary. When the fallback event is cleared, the secondary remains as the new active clock set. In effect, the secondary becomes the new primary, and the primary becomes the new secondary. The concepts are illustrated in the figure below. Selected Watchdog Triggers (Legacy Modes) None NETREF1 watchdog NETREF2 watchdog None None CT_C8_A and /CT_FRAME_A watchdogs CT_C8_B and /CT_FRAME_B watchdogs None None /C4, C2, and /FR_COMP watchdogs /C16±, /C4, C2, and /FR_COMP watchdogs SCLK, /SCLKx2, and /FR_COMP watchdogs PRIMARY REGISTER SET (X OR Y) FALLBACK EVENT FALLBACK CLEARED SECONDARY REGISTER SET (X OR Y) FIXED SECONDARY SCENARIO FALLBACK EVENT FALLBACK CLEARED REGISTER SET X FALLBACK EVENT ROTATING SECONDARY SCENARIO REGISTER SET Y FALLBACK CLEARED 5-9420 (F) Figure 9. Fallback—Fixed vs. Rotating Secondary Agere Systems Inc. 65 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.1 Clock Fallback (continued) 6.7.1.1 Fallback Scenarios—Fixed vs. Rotating Secondary (continued) RESET INITIAL (Y IS THE ACTIVE SET) USER COMMAND GO_CLOCKS PRIMARY (X IS THE ACTIVE SET) FALLBACK ENABLED AND FALLBACK EVENT TO_SECONDARY (Y IS THE ACTIVE SET, ASSERT FALLBACK FLAG) ROTATING SECONDARY MODE USER COMMAND CLEAR_FALLBACK FIXED SECONDARY MODE FALLBACK TYPE ? ROTATING SECONDARY MODE SECONDARY (Y IS THE ACTIVE SET) FIXED SECONDARY MODE FALLBACK TYPE ? FALLBACK ENABLED AND FALLBACK EVENT TO_PRIMARY (X IS THE ACTIVE SET, ASSERT FALLBACK FLAG) USER COMMAND CLEAR_FALLBACK 5-9422 (F) Figure 10. T8110L Clock Fallback States 66 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.1 Clock Fallback (continued) 6.7.1.1 Fallback Scenarios—Fixed vs. Rotating Secondary (continued) Table 54. Clock Fallback State Description Clock Fallback State INITIAL Description Y is the active clock register set. Default value provides XTAL1-div-4 reference. X is the active clock register set and controls APLL1 REFCLK. Exit To PRIMARY Exit Condition User issues GO_CLOCKS command (set register 0x00108 bit 0). PRIMARY TO_SECONDARY Fallback is enabled and fallback event* occurs. PRIMARY User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = fixed secondary†. User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = rotating secondary†. Fallback is enabled and fallback event* occurs. User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = fixed secondary†. User issues CLEAR_FALLBACK command (set register 0x00108 bit 1) and fallback type = rotating secondary†. TO_SECONDARY Y is the active clock register set and controls APLL1 REFCLK. Fallback flag is asserted. SECONDARY SECONDARY Y is the active clock register set and controls APLL1 REFCLK. X is the active clock register set and controls APLL1 REFCLK. Fallback flag is asserted. TO_PRIMARY TO_PRIMARY SECONDARY PRIMARY * Fallback event; refer to Section 6.7.1.1 on page 64. † Fixed, rotating secondary; refer to Section 6.7.1.2 on page 65. Agere Systems Inc. 67 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.1 Clock Fallback (continued) 6.7.1.3 H-Bus Clock Enable/Disable on Fallback The previous Ambassador devices allowed a fallback mode (A/B fallback) which automatically allowed an H1x0 bus clock master to detect an error in its own output clock and remove itself from the bus, or a clock slave to detect an error on its incoming clock and promote itself to clock master. The H-bus clocks include: ! ! ! A clocks: CT_C8_A, /CT_FRAME_A B clocks: CT_C8_B, /CT_FRAME_B C clocks: /C16±, /C4, C2, SCLK, /SCLKx2, /FR_COMP Refer to Figure 11 and Table 55. The T8110L allows for this mode of operation in two ways: Register 0x00109(7:4) = 0100: legacy mode, A/B fallback—when this mode is selected, the fallback triggers allowed are predefined based on the main input clock selection, and the state machine which controls H-bus clock enable/disable is activated. Register 0x00109(7:4) = 1001: nonlegacy mode—when this mode is selected, the fallback trigger enable registers determine what triggers a fallback, and the state machine which controls H-bus clock enable/disable is activated. Diag_ABC Diag_ABC = Drives A Clocks, B Clocks and C Clocks, no fallback permitted Diag_AB = Drives A Clocks and B Clocks, no fallback permitted C_Only = Drives C Clocks only, no fallback permitted Diag_AB The T8110 enters & leaves these states based on Master Output Enable clock register updates, 0x00220 C_Only B_Only = Drives B Clocks, can be promoted to master and drive C clocks in fallbackcondition B_Master = Drives B & C Clocks, all clocks shut off in fallbackcondition B_Error = all clocks shut off, waiting for B clocks to be reprogrammed Diagnostic/Forced Clocking Fallback Clocking, assumes Fallback enabled in CKS register Initial B_Only B Clocks Fail B_Error A Clocks Fail B Clocks Fail Reprogram B Clocks B_Master A_Only A Clocks Fail A_Error B Clocks Fail A Clocks Fail Reprogram A Clocks A_Only = Drives A Clocks, can be promoted to master and drive C clocks in fallbackcondition A_Master = Drives A & C Clocks, all clocks shut off in fallbackcondition A_Error = all clocks shut off, waiting for A clocks to be reprogrammed A_Master Figure 11. T8110L H-Bus Clock Enable States 68 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.1 Clock Fallback (continued) 6.7.1.1 H-Bus Clock Enable/Disable on Fallback (continued) Table 55. H-Bus Clock Enable State Description H-Bus Clock Enable State INITIAL Description Initial condition, waiting for clock output control register programming. T8110L is driving all H-bus clocks (diagnostic mode). T8110L is driving both the H-bus A and B clocks (diagnostic mode). T8110L is driving only the H-bus C clocks. T8110L clock output control registers are programmed to drive A clocks and C clocks (T8110L is an A clock master), or T8110L was supplying a backup A clock and has been promoted to A clock master. T8110L clock output control registers are programmed to drive A clocks only (T8110L is a B clock slave, and supplies a backup A clock). Exit To Exit Condition Any of the User update of the clock output control regisother states ter (0x00220, master output enables). INITIAL INITIAL INITIAL User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables). DIAG_ABC DIAG_AB C_ONLY A_MASTER A_ERROR A clock error on CT_C8_A or /CT_FRAME_A is detected; disable clock outputs. INITIAL User update of the clock output control register (0x00220, master output enables). A_ONLY A_MASTER A clock error on CT_C8_B or /CT_FRAME_B is detected; promote to A clock master. A_ERROR A clock error on CT_C8_A or /CT_FRAME_A is detected; disable clock outputs. INITIAL INITIAL User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables). A_ERROR T8110L has detected a clock error while driving the A clocks, and has stopped driving any H bus clocks. T8110L clock output control registers are programmed to drive B clocks and C clocks (T8110L is a B clock master), or T8110L was supplying a backup B clock and has been promoted to B clock master. T8110L clock output control registers are programmed to drive B clocks only (T8110L is an A clock slave, and supplies a backup B clock). B_MASTER B_ERROR A clock error on CT_C8_B or /CT_FRAME_B is detected; disable clock outputs. INITIAL User update of the clock output control register (0x00220, master output enables). B_ONLY B_MASTER A clock error on CT_C8_A or /CT_FRAME_A is detected; promote to B clock master. B_ERROR A clock error on CT_C8_B or /CT_FRAME_B is detected; disable clock outputs. INITIAL INITIAL User update of the clock output control register (0x00220, master output enables). User update of the clock output control register (0x00220, master output enables). B_ERROR T8110L has detected a clock error while driving the B clocks, and has stopped driving any H bus clocks. Agere Systems Inc. 69 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.2 Clock Failsafe Clock failsafe provides a safety net for the APLL1 reference clock source and is controlled by three registers, 0x00114—0x00116; see Section 5.1.11 on page 38. A failsafe event overrides the active clock control registers and forces the APLL1 clock selection to be a fixed 4.096 MHz, derived from the XTAL1 crystal, divided by four. Transition into one of the failsafe states is independent of clock fallback (i.e., can enter from any state other than INITIAL). Transitions out of the failsafe states are by user command and allow re-entry into either a nonfallback (primary or secondary) or a fallback (TO_SECONDARY or TO_PRIMARY) state. Refer to Table 56 and Figure 12. 6.7.2.1 Failsafe Events Clock failsafe (transition from either clock register set to a forced XTAL1-div-4 APLL1 reference clock) can only occur if the failsafe mode is enabled (register 0x00115, lower nibble), and a failsafe event occurs. A failsafe event is triggered by a watchdog error on the APLL1 reference clock (i.e., loss-of-reference). Additionally, an out-of-lock (OOL) condition is provided for debug purposes. This does not trigger a failsafe event, but does indicate potential difficulty with the APLL1. A lock status flag is provided out of APLL1, and the OOL is defined by exceeding a user-defined threshold value (register 0x00116). The lock status is a flag indicating when APLL1 is making a correction to maintain synchronization. The flag is continuously sampled. If enough active flags are sampled in a row to exceed the user-defined threshold, this condition is reported via the system status register (0x00125). RESET INITIAL (Y IS THE ACTIVE SET) USER COMMAND GO_CLOCKS PRIMARY (X IS THE ACTIVE SET) FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO NONFALLBACK STATE FS_1 FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO FALLBACK STATE TO_SECONDARY (Y IS THE ACTIVE SET, ASSERT FALLBACK FLAG) FIXED SECONDARY MODE USER COMMAND CLEAR_FALLBACK FALLBACK TYPE ? ROTATING SECONDARY MODE SECONDARY (Y IS THE ACTIVE SET) FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO NONFALLBACK STATE FS_2 FAILSAFE ENABLED AND FAILSAFE EVENT FAILSAFE RETURN TO FALLBACK STATE TO_PRIMARY (X IS THE ACTIVE SET, ASSERT FALLBACK FLAG) FALLBACK ENABLED AND FALLBACK EVENT ROTATING SECONDARY MODE FALLBACK ENABLED AND FALLBACK EVENT FIXED SECONDARY MODE FALLBACK TYPE ? USER COMMAND CLEAR_FALLBACK 5-9421 (F) Figure 12. T8110L Clock Failsafe States 70 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 6 Clock Architecture (continued) 6.7 Clock Circuit Operation—Fallback and Failsafe (continued) 6.7.2 Clock Failsafe (continued) 6.7.2.1 Failsafe Events (continued) Table 56. Clock Failsafe State Descriptions Clock Failsafe State FS_1 Description APLL1 REFCLK is forced to XTAL1-div-4. FAILSAFE FLAG is asserted. Exit To PRIMARY Exit Condition User issues FAILSAFE_RETURN to nonfallback state command (set register 0x00114 bit 0). TO_SECONDARY User issues FAILSAFE_RETURN to fallback state command (set register 0x00114 bit 1). SECONDARY User issues FAILSAFE_RETURN to non-fallback state command (set register 0x00114 bit 0). User issues FAILSAFE_RETURN to fallback state command (set register 0x00114 bit 1). FS_2 APLL1 REFCLK is forced to XTAL1-div-4. FAILSAFE FLAG is asserted. TO_PRIMARY Agere Systems Inc. 71 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 7 Frame Group and FG I/O There are eight independently programmable T8110L frame group/FGIO signals, FG[7:0]. In the frame group mode, the pin is an 8 kHz frame reference output, with programmable pulse width, polarity, and delay offset from the internally generated frame reference. In the FGIO mode, the pin behaves as a general-purpose register bit, with programmable direction (IN or OUT) and read masking. The FG7 signal allows for an additional mode of operation, providing a timer via a 16-bit programmable counter. Table 57. Frame Group and FG I/O Register Map DWORD Address (20 bits) 0x00400 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00474 0x00480 Register Byte 3 FG0 rate FG1 rate FG2 rate FG3 rate FG4 rate FG5 rate FG6 rate FG7 rate FG7 mode upper Reserved Byte 2 FG0 width FG1 width FG2 width FG3 width FG4 width FG5 width FG6 width FG7 width FG7 mode lower FGIO R/W Byte 1 FG0 upper start FG1 upper start FG2 upper start FG3 upper start FG4 upper start FG5 upper start FG6 upper start FG7 upper start FG7 counter high byte FGIO read mask Byte 0 FG0 lower start FG1 lower start FG2 lower start FG3 lower start FG4 lower start FG5 lower start FG6 lower start FG7 lower start FG7 counter low byte FGIO data register 7.1 Frame Group Control Registers 7.1.1 FGx Lower and Upper Start Registers The FGx lower and upper start registers provide a 12-bit delay offset value for the corresponding frame group bit. Offsets are relative to the T8110L internally generated 8 kHz frame reference and have a resolution down to one 32.768 MHz clock period (30.5 ns increments). Table 58. FGx Lower and Upper Start Registers Byte Address 0x00400 0x00410 0x00420 0x00430 0x00440 0x00450 0x00460 0x00470 0x00401 (0x00411) (0x00421) (0x00431) (0x00441) (0x00451) (0x00461) (0x00471) Name FG0 Lower Start (FG1 Lower Start) (FG2 Lower Start) (FG3 Lower Start) (FG4 Lower Start) (FG5 Lower Start) (FG6 Lower Start) (FG7 Lower Start) FG0 Upper Start (FG1 Upper Start) (FG2 Upper Start) (FG3 Upper Start) (FG4 Upper Start) (FG5 Upper Start) (FG6 Upper Start) (FG7 Upper Start) Bit(s) 7:0 Mnemonic F0LLR (F1LLR) (F2LLR) (F3LLR) (F4LLR) (F5LLR) (F6LLR) (F7LLR) F0ULR (F1ULR) (F2ULR) (F3ULR) (F4ULR) (F5ULR) (F6ULR) (F7ULR) Value Function LLLL LLLL Lower 8 bits of 12-bit start offset. 7:0 0000 LLLL Upper 4 bits of 12-bit start offset. 72 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 7 Frame Group and FG I/O (continued) 7.1 Frame Group Control Registers (continued) 7.1.2 FGx Width Registers The FGx width registers control the polarity and the pulse widths generated for the corresponding frame group bit. The pulse-width programming works in conjunction with the FGx rate registers to provide 1-bit, 2-bit, 4-bit, 1-byte, and 2-byte wide pulses for any of the available frame group rates (see Table 59). Table 59. FGx Width Registers Byte Address 0x00402 (0x00412) (0x00422) (0x00432) (0x00442) (0x00452) (0x00462) (0x00472) Name FG0 Width (FG1 Width) (FG2 Width) (FG3 Width) (FG4 Width) (FG5 Width) (FG6 Width) (FG7 Width) Bit(s) Mnemonic 7 F0ISB (F1ISB) (F2ISB) (F3ISB) (F4ISB) (F5ISB) (F6ISB) (F7ISB) F0WSP (F1WSP) (F2WSP) (F3WSP) (F4WSP) (F5WSP) (F6WSP) (F7WSP) Value 0 1 Function Generate active-high pulse (default). Generate active-low pulse. 6:0 000 0000 000 0001 000 0010 000 0100 001 0000 010 0000 1-bit wide pulse (default). 1-bit wide pulse. 2-bit wide pulse. 4-bit wide pulse. 1-byte wide pulse. 2-byte wide pulse. 7.1.3 FGx Rate Registers The FGx rate registers either enable FGIO operation* or work in conjunction with FGx width registers to provide various width frame group pulses at rates of 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. Table 60. FGx Rate Registers Byte Address 0x00403 (0x00413) (0x00423) (0x00433) (0x00443) (0x00453) (0x00463) (0x00473) Name FG0 Rate (FG1 Rate) (FG2 Rate) (FG3 Rate) (FG4 Rate) (FG5 Rate) (FG6 Rate) (FG7 Rate) Bit(s) Mnemonic 7:0 F0RSR (F1RSR) (F2RSR) (F3RSR) (F4RSR) (F5RSR) (F6RSR) (F7RSR) Value 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0000 1001 Function Off (default). FGIO enabled* (not used as a frame group). FGx rate = 2.048 MHz. FGx rate = 4.096 MHz. FGx rate = 8.192 MHz. FGx rate = 16.384 MHz. * FGIO operation is controlled at registers 0x00480—482. Refer to Section 7.3 on page 75. Agere Systems Inc. 73 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 7 Frame Group and FG I/O (continued) 7.2 FG7 Timer Option The FG7 signal allows for an added function of a timer output, via a 16-bit programmable counter. 7.2.1 FG7 Counter (Low and High Byte) Registers The FG7 counter (low and high byte) registers set the timer value. The timer is actually a divider, so the value entered must be [divider value – 1], i.e., 0000000000000011 would yield a div-by-4 operation. The FG7 mode lower register enables the timer option, with two clock source options: T8110L internal frame or an external timer clock via the FG6 signal. The FG7 mode upper register controls the shape of the timer pulse. For more details, see Section 7.4.3 on page 79. Table 61. FG7 Counter (Low and High Byte) Registers Byte Address Name Bit Mnemonic FCLLR FCULR F7MSR Value LLLL LLLL LLLL LLLL 0000 0000 0000 0001 0000 0010 0 1 000 001 010 100 0001 0010 0100 1000 Function Lower 8 bits of 16-bit counter value. Upper 8 bits of 16-bit counter value. Normal operation* (default). Enable timer, clock = internal frame. Enable timer, clock = external FG6. Normal FG7 timer output, high pulses (default). Inverted FG7 timer output, low pulses. FG7 timer output off (default). FG7 timer output = square wave†. FG7 timer output = carry out pulse‡. FG7 timer output = programmable pulse§. Programmable pulse width = 30.5 ns. Programmable pulse width = 61.0 ns. Programmable pulse width = 91.5 ns. Programmable pulse width = 122 ns. 0x00474 FG7 Counter, Low Byte 7:0 0x00475 FG7 Counter, High Byte 7:0 0x00476 FG7 Mode Lower 7:0 0x00477 FG7 Mode Upper 7 FCISB 6:4 F7SSP 3:0 F7WSN * Normal operation allows frame group or FGIO control via registers 0x00470—473. Enabling the counter overrides 0x00470—473 settings. † Square wave is only available when FG7 counter high/low value is a binary multiple 1, 2, 4, 8, 16, etc. Other values yield a carry out pulse shape. ‡ Carry out pulse is active for one FG7 timer clock period. § Programmable pulses are based on T8110L internal 32.768 MHz clock periods. 74 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 7 Frame Group and FG I/O (continued) 7.3 FGIO Control Registers 7.3.1 FGIO Data Register The FGIO data register provides read/write access and write storage to/from any FG signals being used as general-purpose register bits. Writes to FGIO work in conjunction with the corresponding FGIO enabled settings in the FGx rate registers. Reads are maskable, controlled via register 0x00481. Table 62. FGIO Data Register Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 7.3.2 FGIO Read Mask Register The FGIO read mask register controls the masking of any FG signals being used as general-purpose register bits on a read access to the FGIO register. Table 63. FGIO Read Mask Register Byte Address 0x00481 Name FGIO Read Mask Bit(s) Mnemonic 7 6 5 4 3 2 1 0 F7MEB F6MEB F5MEB F4MEB F3MEB F2MEB F1MEB F0MEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmask FGIO bit 7 (default). Mask FGIO bit 7, return 0 on a read. Unmask FGIO bit 6 (default). Mask FGIO bit 6, return 0 on a read. Unmask FGIO bit 5 (default). Mask FGIO bit 5, return 0 on a read. Unmask FGIO bit 4 (default). Mask FGIO bit 4, return 0 on a read. Unmask FGIO bit 3 (default). Mask FGIO bit 3, return 0 on a read. Unmask FGIO bit 2 (default). Mask FGIO bit 2, return 0 on a read. Unmask FGIO bit 1 (default). Mask FGIO bit 1, return 0 on a read. Unmask FGIO bit 0 (default). Mask FGIO bit 0, return 0 on a read. F7IOB F6IOB F5IOB F4IOB F3IOB F2IOB F1IOB F0IOB Value L L L L L L L L FGIO bit 7 value. FGIO bit 6 value. FGIO bit 5 value. FGIO bit 4 value. FGIO bit 3 value. FGIO bit 2 value. FGIO bit 1 value. FGIO bit 0 value. Function 0x00480 FGIO Data Register Agere Systems Inc. 75 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 7 Frame Group and FG I/O (continued) 7.3 FGIO Control Registers (continued) 7.3.3 FGIO R/W Register The FGIO R/W register provides direction control for any of the FG signals being used as general-purpose register bits. Table 64. FGIO R/W Register Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 F7DSB F6DSB F5DSB F4DSB F3DSB F2DSB F1DSB F0DSB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function FGIO bit 7 direction is input (default). FGIO bit 7 direction is output. FGIO bit 6 direction is input (default). FGIO bit 6 direction is output. FGIO bit 5 direction is input (default). FGIO bit 5 direction is output. FGIO bit 4 direction is input (default). FGIO bit 4 direction is output. FGIO bit 3 direction is input (default). FGIO bit 3 direction is output. FGIO bit 2 direction is input (default). FGIO bit 2 direction is output. FGIO bit 1 direction is input (default). FGIO bit 1 direction is output. FGIO bit 0 direction is input (default). FGIO bit 0 direction is output. 0x00482 FGIO R/W 76 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 7 Frame Group and FG I/O (continued) 7.4 FG Circuit Operation Each of the eight frame group signals FG[7:0] operate independently and have multiple uses. Refer to Figure 13 below. ! ! ! ! ! As programmable 8 kHz frame reference outputs (frame group) As general-purpose register I/O bits (FGIO) As a programmable timer (FG7 only) As external interrupt input signals As diagnostic observation points for internal testpoints MASTER ENABLE REGISTER (0x00103) TESTPOINT DIAGNOSTIC CONTROL T8110L TESTPOINTS FGIOX R/W FGX RATE FGX WIDTH FGX UPPER/ LOWER START ADDR FGx ENABLE LOGIC OFFSET DETECT PULSE GENERATOR OUTPUT ENABLE T8110L INTERNAL FRAME FROM FG6 INPUT PROGRAMMABLE TIMER (FG7 ONLY) FGX FG7 MODE FG7 COUNTER HI/LO BYTE FGIO DATA REGISTER WRITES FROM REGISTER ACCESS INTERFACE FGIO DATA REGISTER READS TO REGISTER ACCESS INTERFACE IF DIRECTION = OUTPUT, RETURN THE DATA REG CONTENTS ON A READBACK, ELSE RETURN THE I/O PIN VALUE. FGIOX DATA REG FGIOX READ MASK FGIOX R/W FG AS EXTERNAL INTERRUPT TO INTERRUPT CONTROLLER 5-9428a (F) Figure 13. FG[7:0] Functional Paths Agere Systems Inc. 77 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 7 Frame Group and FG I/O (continued) 7.4 FG Circuit Operation (continued) 7.4.1 Frame Group 8 kHz Reference Generation Any of the T8110L FG signals may be used as programmable 8 kHz frame reference outputs. There are two sets of control required, an offset delay from internal frame center, and pulse shaping. The offset delay is provided via the FGx upper/lower start address registers. The delay is relative to the T8110L internal frame center, and the 12 bits used allow for 4096 different offsets, in increments of one 32.768 MHz clock period (30.5 ns). Pulse shaping is controlled via the FGx width and FGx rate registers. Pulses may be programmed to be active-high or active-low. Pulse width can be either 1-bit, 2-bit, 4-bit, 1-byte or 2-byte wide (relative to the rate setting*), with allowable rate settings of 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz. *Pulse widths are bit times or multiples of bit times, for each applicable rate: RATE 2.048 Mbits/s 4.096 Mbits/s 8.192 Mbits/s 16.384 Mbits/s BIT TIME 488 ns 244 ns 122 ns 61 ns Frame Center bitclock rate (2, 4, 8, or 16MHz) T8110 internal frame timeslot 31, 63, 127 or 255 0 1 2 3 4 FG(x), 1-bit width, offset = 0 FG(x), 2-bit width, offset = 0 FG(x), 4-bit width, offset = 0 FG(x), 1-byte width, offset = 0 FG(x), 2-byte width, offset = 0 Notes: Frame group signals shown with offset = 0 (default). At offset = 0, the pulse starts at frame center. Nonzero offsets denote 32.768 MHz period increments (30.5 ns) from frame center. There are up to 4096 increments within an 8 kHz frame period. Offsets may be programmed in the range from 0—4095. Frame group signals are shown as active high pulses (default)—they may be programmed as active-low pulses. Diagram shows frame group pulse widths relative to bit-clock rate and time-slot width. This is applicable for any of the four frame group data rates (2 Mbits/s, 4 Mbits/s, 8 Mbits/s, or 16 Mbits/s). Figure 14. Frame Group 8 kHz Reference Timing 78 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 7 Frame Group and FG I/O (continued) 7.4 FG Circuit Operation (continued) 7.4.2 FGIO General-Purpose Bits Any of the T8110L FG signals may be used as general-purpose I/O bits. Each FG bit used as FGIO is configured by enabling the FGIO function via the FGx rate register(s) and setting the direction via the appropriate bits in the FGIO R/W register. For write access to the FGIO, the FGIO data register is used to hold data for output to the FG pin(s). Read accesses are maskable via the FGIO read mask register. For read access from the FGIO, the logical state of the FG[7:0] signals is returned if unmasked. If an FGIO bit is masked, a read access returns 0. 7.4.3 Programmable Timer (FG7 Only) The FG7 signal can be used as a programmable timer output, via the FG7 mode upper/lower, and FG7 counter high and low byte registers. The FG7 timer is simply a clock divider. The FG7 counter high/low provides a 16-bit [divider value – 1]. Note: [divider value – 1], i.e., a value of 0000000000000011 yields a div-by-4 operation. The FG7 mode lower register enables the counter and selects between two clock sources into the counter: either the T8110L internal frame (8 kHz) or an external clock via the FG6 input. The FG7 mode upper register controls the output pulse shape. The output can be inverted or noninverted and shaped as either a square wave, a carryout pulse, or a programmable-width pulse. ! Square wave. This option is applicable only for divide operations that are binary multiples (i.e., div-by-2, div-by4, div-by-8, div-by-16, div-by-65536). Nonbinary divide operations while square wave is selected result in a carryout pulse. Carryout pulse. The output is a pulse, width = one FG7 timer clock period. Programmable-width pulse. The timer output is synchronized to the T8110L 32.768 MHz clock domain and can be programmed for 1, 2, 3, or 4, 32.768 MHz clock periods in width (30.5 ns, 61 ns, 91.5 ns, or 122 ns). ! ! 7.4.4 FG External Interrupts All FG signals are internally connected as inputs to the interrupt controller logic. Any FG signal, whether an output or an input, may be used to trigger interrupts. When a T8110L FG signal is used as an externally sourced input into the interrupt controller logic, it must be in input mode (i.e., shut-off, FGx rate register(s) FxRSR = 0000 0000). An FG signal in output mode may also be used for interrupts (i.e., an 8 kHz periodic signal, see Section 7.4.1 on page 78). The interrupt control registers (0x00600—603) control how the FG inputs are handled (for more details, refer to Section 10.1 on page 90). 7.4.5 FG Diagnostic Test Point Observation Any of the T8110L FG signals may be used to observe a predefined set of internal testpoints. Each FG bit used as a testpoint output is enabled via diagnostic register 0x00140, FG testpoint enable. Settings in this register override the FGx rate and FGIO R/W register, and force the selected bits to be testpoint outputs, see Section 11.1 on page 106 and Table 88 on page 106. Agere Systems Inc. 79 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 8 General-Purpose I/O There are eight independent T8110L GPIO signals, GP[7:0]. These pins behave as general-purpose register bits, with programmable direction (in or out) and read masking. The GP0 and GP1 signals allow for an additional mode of operation, providing dedicated output signals to indicate A clock and B clock mastering for H.110 bus applications. 8.1 GPIO Control Registers Table 65. GPIO Register DWORD Address (20 bits) 0x00500 Register Byte 3 GPIO override Byte 2 GPIO R/W Byte 1 GPIO read mask Byte 0 GPIO data register 8.1.1 GPIO Data Register The GPIO data register provides read/write access and write storage to/from any GP signals being used as general-purpose register bits. Reads from GPIO are maskable, controlled via register 0x00501. Table 66. GPIO Data Register Byte Address Name Bit(s) 7 6 5 4 3 2 1 0 Mnemonic G7IOB G6IOB G5IOB G4IOB G3IOB G2IOB G1IOB G0IOB Value L L L L L L L L Function GPIO bit 7 value. GPIO bit 6 value. GPIO bit 5 value. GPIO bit 4 value. GPIO bit 3 value. GPIO bit 2 value. GPIO bit 1 value. GPIO bit 0 value. 0x00500 GPIO Data Register 80 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 8 General-Purpose I/O (continued) 8.1 GPIO Control Registers (continued) 8.1.2 GPIO Read Mask Register The GPIO read mask register controls the masking of any GP signals being used as general-purpose register bits on a read access to the GPIO register. Table 67. GPIO Read Mask Register Byte Address 0x00501 Name GPIO Read Mask Bit(s) 7 6 5 4 3 2 1 0 Mnemonic G7MEB G6MEB G5MEB G4MEB G3MEB G2MEB G1MEB G0MEB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmask GPIO bit 7 (default). Mask GPIO bit 7, return 0 on a read. Unmask GPIO bit 6 (default). Mask GPIO bit 6, return 0 on a read. Unmask GPIO bit 5 (default). Mask GPIO bit 5, return 0 on a read. Unmask GPIO bit 4 (default). Mask GPIO bit 4, return 0 on a read. Unmask GPIO bit 3 (default). Mask GPIO bit 3, return 0 on a read. Unmask GPIO bit 2 (default). Mask GPIO bit 2, return 0 on a read. Unmask GPIO bit 1 (default). Mask GPIO bit 1, return 0 on a read. Unmask GPIO bit 0 (default). Mask GPIO bit 0, return 0 on a read. 8.1.3 GPIO R/W Register The GPIO R/W register provides direction control for any of the GP signals being used as general-purpose register bits. Table 68. GPIO R/W Register Byte Address 0x00502 Name GPIO R/W Bit(s) 7 6 5 4 3 2 1 0 Mnemonic G7DSB G6DSB G5DSB G4DSB G3DSB G2DSB G1DSB G0DSB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GPIO bit 7 direction is input (default). GPIO bit 7 direction is output. GPIO bit 6 direction is input (default). GPIO bit 6 direction is output. GPIO bit 5 direction is input (default). GPIO bit 5 direction is output. GPIO bit 4 direction is input (default). GPIO bit 4 direction is output. GPIO bit 3 direction is input (default). GPIO bit 3 direction is output. GPIO bit 2 direction is input (default). GPIO bit 2 direction is output. GPIO bit 1 direction is input (default). GPIO bit 1 direction is output. GPIO bit 0 direction is input (default). GPIO bit 0 direction is output. Agere Systems Inc. 81 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 8 General-Purpose I/O (continued) 8.1 GPIO Control Registers (continued) 8.1.4 GPIO Override Register Table 69. GPIO Override Register Byte Address Name Bit(s) Mnemonic 7:2 1 0 Reserved G1OEB G0OEB Value 0000 0 0 1 0 1 Function NOP (default). GPIO bit 1 is GPIO (default). GPIO bit 1 B-master indicator output. GPIO bit 0 is GPIO (default). GPIO bit 0 A-master indicator output. 0x00503 GPIO Override 8.2 GP Circuit Operation The eight general-purpose I/O group signals GP[7:0] each operate independently and have multiple uses. Please refer to Figure 15 on page 82. ! ! ! ! As general-purpose register I/O bits (GPIO) As H.110 bus clock master indicators (GP0, GP1 only) As external interrupt input signals As diagnostic observation points for internal testpoints MASTER ENABLE REGISTER (0x00103) TESTPOINT DIAGNOSTIC CONTROL T8110L TESTPOINTS GPIOX R/W GPIO OVERRIDE GPx ENABLE LOGIC GP0: A-CLOCK MASTER INDICATOR (0x00220 bit 4) GP1: B-CLOCK MASTER INDICATOR (0x00220 bit 5) OUTPUT ENABLE GPIO DATA REGISTER WRITES FROM REGISTER ACCESS INTERFACE GPIO DATA REGISTER READS TO REGISTER ACCESS INTERFACE GPIOX DATA REG IF DIRECTION = OUTPUT, RETURN THE DATA REG CONTENTS ON A READBACK, ELSE RETURN THE I/O PIN VALUE. GPX GPIOX READ MASK GPIOX R/W GP AS EXTERNAL INTERRUPT TO INTERRUPT CONTROLLER 5-9427a (F) Figure 15. GP[7:0] Functional Paths 82 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 8 General-Purpose I/O (continued) 8.2 GP Circuit Operation (continued) 8.2.1 GPIO General-Purpose Bits Any of the T8110L GP signals may be used as general-purpose I/O bits. Each GP bit used as GPIO is configured by setting the direction via the appropriate bits in the GPIO R/W register. For write access to the GPIO, the GPIO data register is used to hold data for output to the GP pin(s). Read accesses are maskable via the GPIO read mask register. For read access from the GPIO, the logical state of the GP[7:0] signals is returned if unmasked. If a GPIO bit is masked, a read access returns 0. 8.2.2 GP Dual-Purpose Bits GPIO (Override) 8.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) An additional function is provided for GP0 and GP1 only, controlled via the GPIO override register. GP0 may be used as a dedicated output (set GPIO override register bit 0), which transmits the state of the T8110L A clock master enable (register 0x00220, bit 4). This output is intended to drive the external A clock FETs required for H.110 bus mastering. GP1 may be used as a dedicated output (set GPIO override register bit 1), which transmits the state of the T8110L B clock master enable (register 0x00220, bit 5). This output is intended to drive the external B clock FETs required for H.110 bus mastering. 8.2.3 GP External Interrupts Any of the T8110L GP signals may be used as externally sourced inputs into the interrupt controller logic. Each GP bit used as an interrupt input must be shut off by setting the appropriate GPIO R/W register bit to be input. The interrupt control registers (0x00604—607) control how the GP inputs are handled. For more details, see Section 10.1 on page 90. 8.2.4 GP Diagnostic Test Point Observation Any of the T8110L GP signals may be used to observe a predefined set of internal testpoints. Each GP bit used as a testpoint output is enabled via diagnostic register 0x00142, GP testpoint enable. Settings in this register override the GPIO R/W register and force the selected bits to be testpoint outputs (refer to Section 11.1 on page 106, and Table 90 on page 108). Agere Systems Inc. 83 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 9 Stream Rate Control There are a total of 64 data streams, divided into 16 stream groups of four streams each, as shown below. Table 70. T8110L Serial Stream Groupings Stream Group H-bus group A H-bus group B H-bus group C H-bus group D H-bus group E H-bus group F H-bus group G H-bus group H L-bus group A L-bus group B L-bus group C L-bus group D L-bus group E L-bus group F L-bus group G L-bus group H Stream Bits CT_D[0:3] CT_D[4:7] CT_D[8:11] CT_D[12:15] CT_D[16:19] CT_D[20:23] CT_D[24:27] CT_D[28:31] LD[0:3] LD[4:7] LD[8:11] LD[12:15] LD[16:19] LD[20:23] LD[24:27] LD[28:31] The H-bus group operational frequencies are selectable between 2.048 MHz, 4.096 MHz, and 8.192 MHz. The L-bus groups may operate at 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz, which is implemented as multiplexed 8.192 MHz streams. (For more details, see Section 9.2.2 on page 86). 84 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 9 Stream Rate Control (continued) 9.1 H-Bus Stream Rate Control Registers 9.1.1 H-Bus Rate Registers The H-bus rate registers control the serial data stream rate of operation for each of the H-bus stream groups, A—H. The upper nibble controls groups B, D, F, and H. The lower nibble controls groups A, C, E, and G. Table 71. H-Bus Rate Registers DWORD Address (20 Bits) 0x00300 Byte Address 0x00300 (0x00301) (0x00302) (0x00303) Name H-bus Rate B/A (H-bus Rate D/C) (H-bus Rate F/E) (H-bus Rate H/G) Register Byte 3 H-bus rate H/G Bit(s) Mnemonic 7:4 HBRSN (HDRSN) (HFRSN) (HHRSN) HARSN (HCRSN) (HERSN) (HGRSN) Byte 2 H-bus rate F/E Value 0000 0010 0100 1000 0000 0010 0100 1000 Byte 1 H-bus rate D/C Function H-bus group B(D, F, H) off (default). H-bus group B(D, F, H) rate = 2.048 MHz. H-bus group B(D, F, H) rate = 4.096 MHz. H-bus group B(D, F, H) rate = 8.192 MHz. H-bus group A(C, E, G) off (default). H-bus group A(C, E, G) rate = 2.048 MHz. H-bus group A(C, E, G) rate = 4.096 MHz. H-bus group A(C, E, G) rate = 8.192 MHz. Byte 0 H-bus rate B/A 3:0 9.2 L-Bus Stream Rate Control Registers 9.2.1 L-Bus Rate Registers The L-bus rate registers control the serial data stream rate of operation for each of the L-bus stream groups, A—H. The upper nibble controls groups B, D, F, and H. The lower nibble controls groups A, C, E, and G. Local streams have a 16.384 MHz rate option (refer to Section 9.2.2 on page 86). Table 72. L-Bus Rate Registers DWORD Address (20 Bits) 0x00320 Byte Address 0x00320 (0x00321) (0x00322) (0x00323) Name L-bus Rate B/A (L-bus Rate D/C) (L-bus Rate F/E) (L-bus Rate H/G) Register Byte 3 L-bus rate H/G Byte 2 L-bus rate F/E Value 0000 0010 0100 1000 1001 0000 0010 0100 1000 1001 Byte 1 L-bus rate D/C Function L-bus group B(D, F, H) off (default). L-bus group B(D, F, H) rate = 2.048 MHz. L-bus group B(D, F, H) rate = 4.096 MHz. L-bus group B(D, F, H) rate = 8.192 MHz. L-bus group B(D, F, H) rate = 16.384 MHz. L-bus group A(C, E, G) off (default). L-bus group A(C, E, G) rate = 2.048 MHz. L-bus group A(C, E, G) rate = 4.096 MHz. L-bus group A(C, E, G) rate = 8.192 MHz. L-bus group A(C, E, G) rate = 16.384 MHz. Byte 0 L-bus rate B/A Bit(s) Mnemonic 7:4 LBRSN (LDRSN) (LFRSN) (LHRSN) LARSN (LCRSN) (LERSN) (LGRSN) 3:0 Agere Systems Inc. 85 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 9 Stream Rate Control (continued) 9.2 L-Bus Stream Rate Control Registers (continued) 9.2.2 L-Bus 16.384 Mbits/s Operation Local stream 16.384 Mbits/s operation is implemented as two multiplexed 8.192 Mbits/s streams. Bits are shifted at 16.384 MHz, and 16 bits are shifted per 8.192 Mbits/s time slot (refer to Figure 16). This operation makes use of adjacent pairs of the existing single-byte hold and shift registers for local stream operation, with the local even stream assigned as the incoming stream, and the local odd stream assigned as the outgoing stream. Pairs are assigned as LD[0,1], LD[2,3], . . . LD[30,31]. When an L-bus group is set to operate at rate of 16.384 Mbits/s, the hold and shift circuitry is configured such that the serial output of the even stream shift register feeds the serial input of the odd stream shift register (refer to Figure 17). 976 ns (ONE 8 Mbits/s TIME-SLOT) TIME-SLOT n 8.192 MHz 16.384 MHz SERIAL DATA: L_D[EVEN] (INCOMING), L_D[ODD] (OUTGOING) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INCOMING BITS ARE SAMPLED AT THE 3/4 POINT OF THE BIT TIME OFFLOAD INCOMING BYTES FROM TIME-SLOT n – 1 TO HOLDING REGISTERS, LOAD OUTGOING BYTES FOR TIME-SLOT n TO SHIFT REGISTERS OFFLOAD INCOMING BYTES FROM TIME-SLOT n TO HOLDING REGISTERS, LOAD OUTGOING BYTES FOR TIME-SLOT n + 1 TO SHIFT REGISTERS 5-9411 (F) Figure 16. Local Stream 16.384 Mbits/s Timing 86 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 9 Stream Rate Control (continued) 9.2 L-Bus Stream Rate Control Registers (continued) 9.2.2 L-Bus 16.384 Mbits/s Operation (continued) INCOMING SERIAL DATA (EVEN) 8-bit BYTE FROM DATA MEMORY EVEN STREAM OUTGOING HOLDING REGISTER INCOMING SERIAL DATA (ODD) 8 LOCAL EVEN STREAM SHIFT REGISTER 8 EVEN STREAM INCOMING HOLDING REGISTER 8-bit BYTE TO DATA MEMORY (NO LOCAL ODD SERIAL INPUT IF 16.384 Mbits/s OPERATION) MS bit OUTGOING SERIAL DATA (EVEN) (NO LOCAL EVEN SERIAL OUTPUT IF 16.384 Mbits/s OPERATION) 16.384 Mbits/s ENABLE 8-bit BYTE FROM DATA MEMORY ODD STREAM OUTGOING HOLDING REGISTER 8 LOCAL ODD STREAM SHIFT REGISTER 8 ODD STREAM INCOMING HOLDING REGISTER 8-bit BYTE TO DATA MEMORY MS bit OUTGOING SERIAL DATA (ODD) 5-9426 (F) Figure 17. Local Stream 16.384 Mbits/s Circuit Agere Systems Inc. 87 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 9 Stream Rate Control (continued) 9.2 L-Bus Stream Rate Control Registers (continued) 9.2.3 16.384 Mbits/s Local I/O Superrate This 16.384 Mbits/s rate option is available only on the local I/O streams (i.e., it is not supported as a part of the H.100/H.110 specifications). When applying the superrate option to a local I/O group, the I/O for the group is redefined and divided into two pairs of input and output. An input or an output can be selected from each pair, but both can't be used simultaneously. This leads to four possible configurations for each group. Note that inputs are always on even signals and outputs are always on odd signals. Thus, if all local groups are operated at the superrate, then the application can have 16 lines, all at 16.384 Mbits/s, in contrast to the 32 I/O lines at normal rates. LD0 LD1 LOCAL I/O PINS GROUP A LD2 LD3 GROUP A CONFIGURATION AT 2.048, 4.096, OR 8.192 Mbits/s LD0 LD0 GROUP A LOCAL I/O PINS LD2 LOCAL I/O PINS GROUP A LD1 LD1 LD2 LD3 LD3 GROUP A CONFIGURATION 1 AT 16.384 Mbits/s SUPERRATE GROUP A CONFIGURATION 2 AT 16.384 Mbits/s SUPERRATE LD0 LD0 GROUP A LOCAL I/O PINS LD2 LOCAL I/O PINS GROUP A LD1 LD1 LD2 LD3 LD3 GROUP A CONFIGURATION 3 AT 16.384 Mbits/s SUPERRATE GROUP A CONFIGURATION 4 AT 16.384 Mbits/s SUPERRATE Figure 18. Superrate I/O Configuration 88 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 9 Stream Rate Control (continued) 9.2 L-Bus Stream Rate Control Registers (continued) 9.2.4 16.384 Mbits/s Local I/O Superrate The configurations are selected as a consequence of the connection programming. The data is inputted or outputted as a true 16-bit at 16.384 Mbits/s signal. Programming a 16-bit connection requires two separate byte connections, one for the MS-byte and the other for the LS-byte. 8.192 Mbits/s STREAM n, TIMESLOT m AND 8.192 Mbits/s STREAM n + 1, TIMESLOT m 7 122 ns 6 5 4 3 2 1 0 8.192 Mbits/s INPUT DATA BITS ARE SAMPLED AT 3/4 POINT (91 ns) OF THE 122 ns BIT TIME 61 ns 16.384 Mbits/s INPUT DATA BITS ARE SAMPLED AT 3/4 POINT (45 ns) OF THE 61 ns BIT TIME SUPERRATE STREAMPAIR n/n + 1, TIMESLOT m IF INPUT USE STREAM n, IF OUTPUT USE STREAM n + 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGRAMMING A CONNECTION FOR STREAM n + 1, TIME SLOT m WRITES TO/READS FROM HERE PROGRAMMING A CONNECTION FOR STREAM n, TIME SLOT m WRITES TO/READS FROM HERE Note: n = even number, m = integer. Figure 19. Relationship Between 8.192 Mbits/s and 16.384 Mbits/s Time Slots Thus, programming a connection to stream n + 1 is programming a connection to the MS-byte on output pin n + 1 and programming a connection to stream n is programming a connection to the LS-byte on output pin n + 1. Similarly, programming a connection from stream n + 1 is programming a connection from the MS-byte on input pin n and programming a connection from stream n is programming a connection from the LS-byte on input pin n. (An easier way to remember this is that the even/odd identifier becomes the MS-byte/LS-byte identifier.) As a consequence of this arrangement, the T8110L permits byte-packing at the superrate in analogous manner to subrate bit-packing. Agere Systems Inc. 89 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control 10.1 Interrupt Control Registers Table 73. Interrupt Control Register Map DWORD Address (20 bits) 0x00600 0x00604 0x00608 0x0060C 0x00610 0x00614 0x006FC Register Byte 3 Byte 2 Byte 1 FGIO interrupt enable GPIO interrupt enable System interrupt pending high Clock interrupt pending high Reserved Reserved In-service, high Byte 0 FGIO interrupt pending GPIO interrupt pending System interrupt pending low Clock interrupt pending low Arbitration control Reserved In-service, low FGIO polarity Reserved GPIO polarity Reserved System interrupt enable System interrupt enable high low Clock interrupt enable Clock interrupt enable high low CLKERR output select SYSERR output select CLKERR pulse width SYSERR pulse width Reserved Reserved 10.1.1 Interrupts Via External FG[7:0] Registers 10.1.1.1 FGIO Interrupt Pending Register The FGIO interrupt pending register stores detected interrupts via the FG[7:0] signals. The user can clear specific pending bits by writing 1 to that bit (write 1 to clear). Interrupts via these signals are maskable via the FGIO interrupt enable register. Table 74. FGIO Interrupt Pending Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 JF7OB JF6OB JF5OB JF4OB JF3OB JF2OB JF1OB JF0OB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via FG7 (default). Pending interrupt via FG7. No pending interrupts via FG6 (default). Pending interrupt via FG6. No pending interrupts via FG5 (default). Pending interrupt via FG5. No pending interrupts via FG4 (default). Pending interrupt via FG4. No pending interrupts via FG3 (default). Pending interrupt via FG3. No pending interrupts via FG2 (default). Pending interrupt via FG2. No pending interrupts via FG1 (default). Pending interrupt via FG1. No pending interrupts via FG0 (default). Pending interrupt via FG0. 0x00600 FGIO Interrupt Pending 90 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.1 Interrupts Via External FG[7:0] Registers (continued) 10.1.1.1 FGIO Interrupt Pending Register (continued) Table 74. FGIO Interrupt Pending Registers (continued) Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 JF7EB JF6EB JF5EB JF4EB JF3EB JF2EB JF1EB JF0EB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable (mask) interrupts via FG7 (default). Enable (unmask) interrupts via FG7. Disable (mask) interrupts via FG6 (default). Enable (unmask) interrupts via FG6. Disable (mask) interrupts via FG5 (default). Enable (unmask) interrupts via FG5. Disable (mask) interrupts via FG4 (default). Enable (unmask) interrupts via FG4. Disable (mask) interrupts via FG3 (default). Enable (unmask) interrupts via FG3. Disable (mask) interrupts via FG2 (default). Enable (unmask) interrupts via FG2. Disable (mask) interrupts via FG1 (default). Enable (unmask) interrupts via FG1. Disable (mask) interrupts via FG0 (default). Enable (unmask) interrupts via FG0. 0x00601 FGIO Interrupt Enable The FGIO edge/level and FGIO polarity registers control how interrupts are interpreted on the GP[7:0] signals (negative edge, positive edge, low level, or high level). Table 75. FGIO Edge/Level and Polarity Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 IF7SB IF6SB IF5SB IF4SB IF3SB IF2SB IF1SB IF0SB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function FG7 interrupts are negative edge or low level (default). FG7 interrupts are positive edge or high level. FG6 interrupts are negative edge or low level (default). FG6 interrupts are positive edge or high level. FG5 interrupts are negative edge or low level (default). FG5 interrupts are positive edge or high level. FG4 interrupts are negative edge or low level (default). FG4 interrupts are positive edge or high level. FG3 interrupts are negative edge or low level (default). FG3 interrupts are positive edge or high level. FG2 interrupts are negative edge or low level (default). FG2 interrupts are positive edge or high level. FG1 interrupts are negative edge or low level (default). FG1 interrupts are positive edge or high level. FG0 interrupts are negative edge or low level (default). FG0 interrupts are positive edge or high level. 0x00603 FGIO Polarity Agere Systems Inc. 91 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.2 Interrupts Via External GP[7:0] 10.1.2.1 GPIO Interrupt Pending Register The GPIO interrupt pending register stores detected interrupts via the GP[7:0] signals. The user can clear specific pending bits by writing 1 to that bit (write 1 to clear). Interrupts via these signals are maskable via the GPIO interrupt enable register. Table 76. GPIO Interrupt Pending Register Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00605 GPIO Interrupt Enable 7 6 5 4 3 2 1 0 JG7OB JG6OB JG5OB JG4OB JG3OB JG2OB JG1OB JG0OB JG7EB JG6EB JG5EB JG4EB JG3EB JG2EB JG1EB JG0EB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via GP7 (default). Pending interrupt via GP7. No pending interrupts via GP6 (default). Pending interrupt via GP6. No pending interrupts via GP5 (default). Pending interrupt via GP5. No pending interrupts via GP4 (default). Pending interrupt via GP4. No pending interrupts via GP3 (default). Pending interrupt via GP3. No pending interrupts via GP2 (default). Pending interrupt via GP2. No pending interrupts via GP1 (default). Pending interrupt via GP1. No pending interrupts via GP0 (default). Pending interrupt via GP0. Disable (mask) interrupts via GP7 (default). Enable (unmask) interrupts via GP7. Disable (mask) interrupts via GP6 (default). Enable (unmask) interrupts via GP6. Disable (mask) interrupts via GP5 (default). Enable (unmask) interrupts via GP5. Disable (mask) interrupts via GP4 (default). Enable (unmask) interrupts via GP4. Disable (mask) interrupts via GP3 (default). Enable (unmask) interrupts via GP3. Disable (mask) interrupts via GP2 (default). Enable (unmask) interrupts via GP2. Disable (mask) interrupts via GP1 (default). Enable (unmask) interrupts via GP1. Disable (mask) interrupts via GP0 (default). Enable (unmask) interrupts via GP0. 0x00604 GPIO Interrupt Pending 92 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.2 Interrupts Via External GP[7:0] (continued) 10.1.2.2 GPIO Edge/Level and GPIO Polarity Registers The GPIO edge/level and GPIO polarity registers control how interrupts are interpreted on the GP[7:0] signals (negative edge, positive edge, low level, or high level). Table 77. GPIO Edge/Level and GPIO Polarity Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 IG7SB IG6SB IG5SB IG4SB IG3SB IG2SB IG1SB IF0SB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GP7 interrupts are negative edge or low level (default). GP7 interrupts are positive edge or high level. GP6 interrupts are negative edge or low level (default). GP6 interrupts are positive edge or high level. GP5 interrupts are negative edge or low level (default). GP5 interrupts are positive edge or high level. GP4 interrupts are negative edge or low level (default). GP4 interrupts are positive edge or high level. GP3 interrupts are negative edge or low level (default). GP3 interrupts are positive edge or high level. GP2 interrupts are negative edge or low level (default). GP2 interrupts are positive edge or high level. GP1 interrupts are negative edge or low level (default). GP1 interrupts are positive edge or high level. GP0 interrupts are negative edge or low level (default). GP0 interrupts are positive edge or high level. 0x00607 GPIO Polarity 10.1.3 Interrupts Via Internal System Errors Table 78. System Error Interrupt Assignments System Interrupt Bit SYS15 SYS14 SYS13 SYS12 SYS11 SYS10 SYS9 SYS8 SYS7 SYS6 SYS5 SYS4 SYS3 SYS2 SYS1 SYS0 Agere Systems Inc. Clock failsafe indicator. Clock fallback indicator. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. 93 Description Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.4 System Interrupt Pending High/Low Registers The system interrupt pending high/low registers store detected interrupts via the internal system error signals. The user can clear specific bits by writing 1 to that bit (write 1 to clear). Table 79. System Interrupt Pending High/Low Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x00609 System Interrupt Pending High 7 6 5 4 3 2 1 0 JS7OB JS6OB JS5OB JS4OB JS3OB JS2OB JS1OB JS0OB JSFOB JSEOB JSDOB JSCOB JSBOB JSAOB JS9OB JS8OB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via SYS7 (default). Pending interrupt via SYS7. No pending interrupts via SYS6 (default). Pending interrupt via SYS6. No pending interrupts via SYS5 (default). Pending interrupt via SYS5. No pending interrupts via SYS4 (default). Pending interrupt via SYS4. No pending interrupts via SYS3 (default). Pending interrupt via SYS3. No pending interrupts via SYS2 (default). Pending interrupt via SYS2. No pending interrupts via SYS1 (default). Pending interrupt via SYS1. No pending interrupts via SYS0 (default). Pending interrupt via SYS0. No pending interrupts via SYS15 (default). Pending interrupt via SYS15. No pending interrupts via SYS14 (default). Pending interrupt via SYS14. No pending interrupts via SYS13 (default). Pending interrupt via SYS13. No pending interrupts via SYS12 (default). Pending interrupt via SYS12. No pending interrupts via SYS11 (default). Pending interrupt via SYS11. No pending interrupts via SYS10 (default). Pending interrupt via SYS10. No pending interrupts via SYS9 (default). Pending interrupt via SYS9. No pending interrupts via SYS8 (default). Pending interrupt via SYS8. 0x00608 System Interrupt Pending Low 94 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.5 System Interrupt Enable High/Low Registers The system interrupt enable high/low registers allow for masking of interrupts via the internal system error signals. Table 80. System Interrupt Enable High/Low Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x0060B System Interrupt Enable High 7 6 5 4 3 2 1 0 JS7EB JS6EB JS5EB JS4EB JS3EB JS2EB JS1EB JS0EB JSFEB JSEEB JSDEB JSCEB JSBEB JSAEB JS9EB JS8EB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable (mask) interrupts via SYS7 (default). Enable (unmask) interrupts via SYS7. Disable (mask) interrupts via SYS6 (default). Enable (unmask) interrupts via SYS6. Disable (mask) interrupts via SYS5 (default). Enable (unmask) interrupts via SYS5. Disable (mask) interrupts via SYS4 (default). Enable (unmask) interrupts via SYS4. Disable (mask) interrupts via SYS3 (default). Enable (unmask) interrupts via SYS3. Disable (mask) interrupts via SYS2 (default). Enable (unmask) interrupts via SYS2. Disable (mask) interrupts via SYS1 (default). Enable (unmask) interrupts via SYS1. Disable (mask) interrupts via SYS0 (default). Enable (unmask) interrupts via SYS0. Disable (mask) interrupts via SYS15 (default). Enable (unmask) interrupts via SYS15. Disable (mask) interrupts via SYS14 (default). Enable (unmask) interrupts via SYS14. Disable (mask) interrupts via SYS13 (default). Enable (unmask) interrupts via SYS13. Disable (mask) interrupts via SYS12 (default). Enable (unmask) interrupts via SYS12. Disable (mask) interrupts via SYS11 (default). Enable (unmask) interrupts via SYS11. Disable (mask) interrupts via SYS10 (default). Enable (unmask) interrupts via SYS10. Disable (mask) interrupts via SYS9 (default). Enable (unmask) interrupts via SYS9. Disable (mask) interrupts via SYS8 (default). Enable (unmask) interrupts via SYS8. 0x0060A System Interrupt Enable Low Agere Systems Inc. 95 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.6 Interrupts Via Internal Clock Errors Table 81. Clock Error Interrupt Assignments Clock Interrupt Bit CLK15 CLK14 CLK13 CLK12 CLK11 CLK10 CLK9 CLK8 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 Description Failsafe indicator—APLL1 reference error. DPLL2 sync input error. DPLL1 sync input error. CT_NETREF2 error. CT_NETREF1 error. /FR_COMP error. /CT_FRAME_B error. /CT_FRAME_A error. /SCLKx2 error. SCLK error. C2 error. /C4 error. /C16– error. /C16+ error. CT_C8_B error. CT_C8_A error. 96 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.7 Clock Interrupt Pending High/Low Registers The clock interrupt pending high/low registers store detected interrupts via the internal clock error signals (refer to Section 5.2.1 on page 40). The user can clear specific bits by writing 1 to that bit (write 1 to clear). Table 82. Clock Interrupt Pending High/Low Registers Byte Address Name Bit(s) Mnemonic Value 7 6 5 4 3 2 1 0 0x0060D Clock Interrupt Pending High 7 6 5 4 3 2 1 0 JC7OB JC6OB JC5OB JC4OB JC3OB JC2OB JC1OB JC0OB JCFOB JCEOB JCDOB JCCOB JCBOB JCAOB JC9OB JC8OB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function No pending interrupts via CLK7 (default). Pending interrupt via CLK7. No pending interrupts via CLK6 (default). Pending interrupt via CLK6. No pending interrupts via CLK5 (default). Pending interrupt via CLK5. No pending interrupts via CLK4 (default). Pending interrupt via CLK4. No pending interrupts via CLK3 (default). Pending interrupt via CLK3. No pending interrupts via CLK2 (default). Pending interrupt via CLK2. No pending interrupts via CLK1 (default). Pending interrupt via CLK1. No pending interrupts via CLK0 (default). Pending interrupt via CLK0. No pending interrupts via CLK15 (default). Pending interrupt via CLK15. No pending interrupts via CLK14 (default). Pending interrupt via CLK14. No pending interrupts via CLK13 (default). Pending interrupt via CLK13. No pending interrupts via CLK12 (default). Pending interrupt via CLK12. No pending interrupts via CLK11 (default). Pending interrupt via CLK11. No pending interrupts via CLK10 (default). Pending interrupt via CLK10. No pending interrupts via CLK9 (default). Pending interrupt via CLK9. No pending interrupts via CLK8 (default). Pending interrupt via CLK8. 0x0060C Clock Interrupt Pending Low Agere Systems Inc. 97 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.8 Clock Interrupt Enable High/Low Registers The clock interrupt enable high/low registers allow for masking of interrupts via the internal clock error signals. Table 83. Clock Interrupt Enable High/Low Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x0060F Clock Interrupt Enable High 7 6 5 4 3 2 1 0 JC7EB JC6EB JC5EB JC4EB JC3EB JC2EB JC1EB JC0EB JCFEB JCEEB JCDEB JCCEB JCBEB JCAEB JC9EB JC8EB Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable (mask) interrupts via CLK7 (default). Enable (unmask) interrupts via CLK7. Disable (mask) interrupts via CLK6 (default). Enable (unmask) interrupts via CLK6. Disable (mask) interrupts via CLK5 (default). Enable (unmask) interrupts via CLK5. Disable (mask) interrupts via CLK4 (default). Enable (unmask) interrupts via CLK4. Disable (mask) interrupts via CLK3 (default). Enable (unmask) interrupts via CLK3. Disable (mask) interrupts via CLK2 (default). Enable (unmask) interrupts via CLK2. Disable (mask) interrupts via CLK1 (default). Enable (unmask) interrupts via CLK1. Disable (mask) interrupts via CLK0 (default). Enable (unmask) interrupts via CLK0. Disable (mask) interrupts via CLK15 (default). Enable (unmask) interrupts via CLK15. Disable (mask) interrupts via CLK14 (default). Enable (unmask) interrupts via CLK14. Disable (mask) interrupts via CLK13 (default). Enable (unmask) interrupts via CLK13. Disable (mask) interrupts via CLK12 (default). Enable (unmask) interrupts via CLK12. Disable (mask) interrupts via CLK11 (default). Enable (unmask) interrupts via CLK11. Disable (mask) interrupts via CLK10 (default). Enable (unmask) interrupts via CLK10. Disable (mask) interrupts via CLK9 (default). Enable (unmask) interrupts via CLK9. Disable (mask) interrupts via CLK8 (default). Enable (unmask) interrupts via CLK8. 0x0060E Clock Interrupt Enable Low 98 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.9 Interrupt Servicing Registers 10.1.9.1 Arbitration Control Register The arbitration control register allows for four modes of interrupt control operation as shown below: ! Disabled. This mode bypasses any interrupt controller operation. No FG or GP inputs are allowed as external interrupt inputs. SYSERR assertion is a simple logical OR of the internal system error bits. CLKERR assertion is a simple logical OR of the internal clock error bits. Flat. This mode treats all 48 possible inputs (eight from external FG[7:0], eight from external GP[7:0], 16 from internal system errors, 16 from internal clock errors) with equal weight, and queues them for in-service via a round-robin arbitration. Tier, no pre-empting. This mode assigns three priority levels. The highest level is internal clock errors CLK[15:0]; next level is internal system errors SYS[15:0]; lowest level is external errors FG[7:0] and GP[7:0]. Arbitration priority encodes between the three levels. Multiple interrupts within a level are queued round-robin. Tier, with pre-empting. This mode is the same as tier, with the added ability to pre-empt a current in-service interrupt according to the three priority levels. ! ! ! Table 84. Arbitration Control Register Byte Address 0x00610 Name Arbitration Control Bit(s) Mnemonic 7:0 JAMSR Value 0000 0000 0000 0001 0000 0010 0001 0010 Function Disable interrupt controller (default). Flat structure (round-robin arbiter). Tier structure (three levels), no pre-empting. Tier structure (three levels), pre-empting. 10.1.9.2 SYSERR and CLKERR Output Select Register The SYSERR output select register controls how the SYSERR signal is asserted (active-high level, active-low level, active-high pulse, or active-low pulse). The SYSERR pulse-width register controls how wide the SYSERR pulse is (when selected output format = high or low pulse). Value corresponds to the number of 32.768 MHz periods – 1. The CLKERR output select register controls how the CLKERR signal is asserted (active-high level, active-low level, active-high pulse, or active-low pulse). The CLKERR pulse-width register controls how wide the CLKERR pulse is (when selected output format = high or low pulse). Value corresponds to the number of 32.768 MHz periods – 1. Agere Systems Inc. 99 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.9 Interrupt Servicing Registers (continued) 10.1.9.2 SYSERR and CLKERR Output Select Register (continued) Table 85. SYSERR Output Select Registers Byte Address Name Bit(s) Mnemonic 7:0 JSOSR Value 0000 0000 0000 0001 0001 0000 0001 0001 0000 0000 0000 0001 0001 0000 0001 0001 Function SYSERR is active-high level* (default). SYSERR is active-low level*. SYSERR is active-high single pulse. SYSERR is active-low single pulse. CLKERR is active-high level* (default). CLKERR is active-low level*. CLKERR is active-high single pulse. CLKERR is active-low single pulse. 0x00612 SYSERR Output Select 0x00616 SYSERR Pulse Width 0x00613 CLKERR Output Select 7:0 7:0 JSWSR JCOSR LLLL LLLL SYSERR pulse-width value. 0x00617 CLKERR Pulse Width * 7:0 JCWSR LLLL LLLL CLKERR pulse-width value. When the arbitration control is disabled (0x00610 = 0000 0000), SYSERR or CLKERR levels remain asserted until all the internal system (or clock) pending bits are cleared. 100 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.9 Interrupt Servicing Registers (continued) 10.1.9.3 Interrupt In-Service Registers The interrupt in-service registers provide a 16-bit interrupt vector, with unique encoding to indicate which of the 48 possible interrupts is currently in-service. Table 86. Interrupt In-Service Register Byte Address 0x006FC 0x006FD Register Name Interrupt In-service Low Interrupt In-service High Bit(s) Mnemonic 7:0 7:0 Reserved JISOR Value Function 0000 000 Lower byte of in-service vector; returns zero. 0000 0000 No interrupt in-service (default). 0001 0000 FG0 interrupt in-service. 0001 0001 FG1 interrupt in-service. 0001 0010 FG2 interrupt in-service. 0001 0011 FG3 interrupt in-service. 0001 0100 FG4 interrupt in-service. 0001 0101 FG5 interrupt in-service. 0001 0110 FG6 interrupt in-service. 0001 0111 FG7 interrupt in-service. 0010 0000 GP0 interrupt in-service. 0010 0001 GP1 interrupt in-service. 0010 0010 GP2 interrupt in-service. 0010 0011 GP3 interrupt in-service. 0010 0100 GP4 interrupt in-service. 0010 0101 GP5 interrupt in-service. 0010 0110 GP6 interrupt in-service. 0010 0111 GP7 interrupt in-service. 0100 0000 SYS0 interrupt in-service. 0100 0001 SYS1 interrupt in-service. 0100 0010 SYS2 interrupt in-service. 0100 0011 SYS3 interrupt in-service. 0100 0100 SYS4 interrupt in-service. 0100 0101 SYS5 interrupt in-service. Agere Systems Inc. 101 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.1 Interrupt Control Registers (continued) 10.1.9 Interrupt Servicing Registers (continued) 10.1.9.3 Interrupt In-Service Registers (continued) The interrupt in-service registers provide a 16-bit interrupt vector, with unique encoding to indicate which of the 48 possible interrupts is currently in-service. Table 86. Interrupt In-Service Register (continued) Byte Address 0x006FD Register Name Interrupt In-service High Bit(s) Mnemonic 7:0 Value 0100 0110 0100 0111 0100 1000 0100 1001 0100 1010 0100 1011 0100 1100 0100 1101 0100 1110 0100 1111 1000 0000 1000 0001 1000 0010 1000 0011 1000 0100 1000 0101 1000 0110 1000 0111 1000 1000 1000 1001 1000 1010 1000 1011 1000 1100 1000 1101 1000 1110 1000 1111 Function SYS6 interrupt in-service. SYS7 interrupt in-service. SYS8 interrupt in-service. SYS9 interrupt in-service. SYS10 interrupt in-service. SYS11 interrupt in-service. SYS12 interrupt in-service. SYS13 interrupt in-service. SYS14 interrupt in-service. SYS15 interrupt in-service. CLK0 interrupt in-service. CLK1 interrupt in-service. CLK2 interrupt in-service. CLK3 interrupt in-service. CLK4 interrupt in-service. CLK5 interrupt in-service. CLK6 interrupt in-service. CLK7 interrupt in-service. CLK8 interrupt in-service. CLK9 interrupt in-service. CLK10 interrupt in-service. CLK11 interrupt in-service. CLK12 interrupt in-service. CLK13 interrupt in-service. CLK14 interrupt in-service. CLK15 interrupt in-service. 102 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.2 Error Reporting and Interrupt Controller Circuit Operation T8110L errors are reported via two output signals, CLKERR and SYSERR. These outputs are generated by an interrupt controller circuit; refer to Figure 20. The interrupt control circuit accepts 48 interrupt inputs in all. The way in which these interrupts are arbitrated is selectable, and the means of reporting the interrupts out to the system is also selectable. FGIO INTERRUPT ENABLE REGISTER FGIO POLARITY, FGIO EDGE/LEVEL REGISTERS FG[7:0] EDGE/LEVEL SENSE CONVERSION FGIO INTERRUPT PENDING REGISTER 8 GP[7:0] GPIO POLARITY, GPIO EDGE/LEVEL REGISTERS GPIO INTERRUPT ENABLE REGISTER SYSTEM INTERRUPT ENABLE REGISTERS SYSTEM ERRORS CLOCK INTERRUPT ENABLE REGISTERS CLOCK ERRORS EDGE/LEVEL SENSE CONVERSION GPIO INTERRUPT PENDING REGISTER 8 16 SYSTEM INTERRUPT PENDING REGISTERS CLOCK INTERRUPT PENDING REGISTERS 16 16 INTERRUPT IN-SERVICE REGISTER CLKERR SYSERR 16 ARBITRATION CONTROL REGISTER LOGICAL OR (UNMASKED CLOCK SOURCES) CLKERR OUTPUT SELECT REGISTER 16 ARBITRATION CLKERR TRIGGER SYSERR TRIGGER EDGE/LEVEL SENSE GENERATION SYSERR OUTPUT SELECT REGISTER EDGE/LEVEL SENSE GENERATION 5-9425 (F) Figure 20. Interrupt Controller Agere Systems Inc. 103 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 10 Error Reporting and Interrupt Control (continued) 10.2 Error Reporting and Interrupt Controller Circuit Operation (continued) 10.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] Up to 16 of the 48 interrupt inputs are sourced external to the T8110L, via the FG[7:0] and GP[7:0] signals. Each input is independently controlled via the interrupt control registers (refer to Section 10.1.1 on page 90 and Section 10.1.2 on page 92). Any externally sourced interrupt may be presented as active-high level, active-low level, positive edge, or negative edge sense. Each external interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register, and presented to the arbitration circuit for servicing. 10.2.2 Internally Sourced System Error Interrupts Another set of 16 of the 48 interrupt inputs are sourced internally via the system error register bits (0x00126—127). Each of these inputs is independently controlled via the interrupt control registers (refer to Section 10.1.3 on page 93). All internal system error bit interrupts are presented as active-high level sense. Each system error bit interrupt is maskable. Any detected interrupt which is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing. 10.2.3 Internally Sourced Clock Error Interrupts Another set of 16 of the 48 interrupt inputs are sourced internally via the latched clock error register bits (0x00122—123; refer to Section 5.2.1 on page 40). Each of these inputs is independently controlled via the interrupt control registers (refer to Section 10.1.6 on page 96). All internal clock error bit interrupts are presented as active-high level sense. Each clock error bit interrupt is maskable. Any detected interrupt that is unmasked is held in an interrupt pending register and presented to the arbitration circuit for servicing. 10.2.4 Arbitration of Pending Interrupts The arbitration of the pending interrupts can be handled in one of four selectable modes: arbitration off, flat arbitration, tier arbitration with pre-empting disabled, and tier arbitration with pre-empting enabled. Interrupts are reported to the system via the SYSERR signal. 10.2.4.1 Arbitration Off This mode only allows the 16 internal system error register bits to generate interrupts, and no arbitration takes place. The trigger for the SYSERR output is simply a logical OR of the internal system error register bits. All bits of the internal system error register must be cleared in order to rearm the SYSERR trigger in this mode. 10.2.4.2 Flat Arbitration The flat arbitration mode performs a round-robin arbitrations on all 48 interrupt sources. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next round-robin arbitration cycle. The system must respond to the current in-service interrupt (refer to Section 10.2.7 on page 105), after which the next arbitration cycle takes place. 10.2.4.3 Tier Arbitration The tier arbitration creates three prioritized groups as shown below: ! ! ! Highest priority. The 16 internal latched clock error register bits. Next highest priority. The 16 internal system error register bits. Lowest priority. The 16 external FG[7:0] and GP[7:0] bits. Agere Systems Inc. 104 Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 10 Error Reporting and Interrupt Control (continued) 10.2 Error Reporting and Interrupt Controller Circuit Operation (continued) 10.2.4 Arbitration of Pending Interrupts (continued) 10.2.4.3 Tier Arbitration (continued) Arbitration assigns interrupt servicing priority to the three groups. Multiple pending interrupts within the same group are arbitrated round-robin. When a pending interrupt wins the arbitration, the in-service register is loaded with its corresponding interrupt vector, SYSERR is triggered, and that pending bit is cleared, removing it from the next arbitration cycle. 10.2.4.4 Pre-Empting Disabled With pre-empting disabled, once a pending interrupt wins the arbitration and the in-service register is loaded with its corresponding interrupt vector, new incoming pending interrupts of higher priority must wait for the system to respond to the current in-service interrupt (refer to Section 10.2.7 on page 105), at which time another arbitration cycle takes place. 10.2.4.5 Pre-Empting Enabled With pre-empting enabled, an interrupt that is in-service (i.e., its interrupt vector is loaded in the in-service register and SYSERR has been triggered) can be overridden by new incoming pending interrupts of higher priority. The current in-service interrupt is pushed onto a stack for storage; the higher-priority interrupt vector is loaded into the in-service register and SYSERR is retriggered. Once all interrupts of higher priority have been serviced by the system (refer to Section 10.2.7 on page 105), the stack is popped and the original lower-priority interrupt is reissued. 10.2.5 CLKERR Output The CLKERR output signal is used to indicate any internal clocking errors. The trigger for the CLKERR output is simply a logical OR of the internal latched clock error register bits. All bits of the internal clock error register must be cleared in order to rearm the CLKERR trigger. The CLKERR trigger induces a state machine to generate the CLKERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or activelow single pulse. 10.2.6 SYSERR Output The T8110L SYSERR output signal is used to report interrupts. Internally, the arbitration circuit provides a SYSERR trigger, which induces a state machine to generate the SYSERR signal in one of four possible ways: active-high level, active-low level, active-high single pulse, or active-low single pulse. 10.2.7 System Handling of Interrupts The T8110L interrupt controller presents an interrupt to the system by triggering the SYSERR output and providing a predefined interrupt vector value at the interrupt in-service register (ISR). The system may acknowledge the interrupt in three ways as shown below: ! System reads the T8110L ISR register. This allows the arbiter to advance, and if more pending interrupts are active, reloads the ISR with the winner of the arbitration and retriggers SYSERR. System clears the T8110L ISR register (via register 0x00100, soft reset; write 0x20 clears the ISR). The arbiter advances, and if more pending interrupts are active, reloads the ISR and retriggers SYSERR. System resets the interrupt controller (via register 0x00100, soft reset, write 0x10 clears the ISR and all the pending interrupt registers). All pending interrupts are cleared, and the arbiter is reset. ! ! Agere Systems Inc. 105 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 11 Test and Diagnostics 11.1 Diagnostics Control Registers The diagnostic control registers allow for various diagnostic modes (refer to Section 11.2 on page 112). Table 87. Diagnostics Control Register Map DWORD Address (20 bits) Register Byte 3 Byte 2 Diag2, GP testpoint enable Byte 1 Diag1, FG testpoint select Byte 0 Diag0, FG testpoint enable Diag4, state counter modes low Diag8, interrupt controller diagnostics 0x00140 Diag3, GP testpoint select 0x00144 Diag7, external buffer Diag6, miscellaneous Diag5, state counter RETRY timer diagnostics low modes high 0x00148 Diag11, sync-toframe command offset high Diag10, sync-toframe command offset low Diag9, interrupt controller SYSERR delay 11.1.1 FG Testpoint Enable Register The FG testpoint enable register allows individual programming of FG[7:0] bits for either standard operation (as FG or FGIO) or as testpoint outputs. FG testpoint select controls the MUX selection for which testpoints are selected. Refer to Table 89 on page 107 for testpoint assignments for each FG bit. Table 88. FG Testpoint Enable Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00141 Diag1, FG Testpoint Select 7:0 FT7EB FT6EB FT5EB FT4EB FT3EB FT2EB FT1EB FT0EB FTPSR Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function FG7 is standard FG or FGIO bit (default). FG7 is a testpoint. FG6 is standard FG or FGIO bit (default). FG6 is a testpoint. FG5 is standard FG or FGIO bit (default). FG5 is a testpoint. FG4 is standard FG or FGIO bit (default). FG4 is a testpoint. FG3 is standard FG or FGIO bit (default). FG3 is a testpoint. FG2 is standard FG or FGIO bit (default). FG2 is a testpoint. FG1 is standard FG or FGIO bit (default). FG1 is a testpoint. FG0 is standard FG or FGIO bit (default). FG0 is a testpoint. 0x00140 Diag0, FG Testpoint Enable LLLL LLLL Value for MUX selection of testpoints output to FG[7:0]—see Table 88 on page 106. 106 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 11 Test and Diagnostics (continued) 11.1 Diagnostics Control Registers (continued) 11.1.1 FG Testpoint Enable Register (continued) Table 89. FG[7:0] Internal Testpoint Assignments FG Testpoint Select Value 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 — 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 P_S_SELECTOR Stalled FG3 Reserved Snapping FG2 FG7 FG6 FG5 FG4 i_FRAME i_FRAME i_FRAME Reserved Reserved STATE_COUNT[10:4] (actual time slot) STATE_COUNT_LOOKAHEAD (lookahead time slot) STATE_COUNT_LOOKBEHIND (lookbehind time slot) Reserved Reserved Reserved OOL threshold flag C clock enable FG1 APLL1 lock indicator B clock enable FG0 Reserved Reserved Reserved Reserved Reserved Reserved Failsafe flag A clock enable STATE_COUNT[10:4] (actual time slot) STATE_COUNT_LOOKAHEAD (lookahead time slot) STATE_COUNT_LOOKBEHIND (lookbehind time slot) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Force-to-OSC4 flag Return from FS2 flag Return from FS1 flag Encoded ABC states: 000 or 100 = DIAGS 001 = A_ONLY 010 = A_MASTER 011 = A_ERROR 101 = B_ONLY 110 = B_MASTER 111 = B_ERROR Agere Systems Inc. 107 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 11 Test and Diagnostics (continued) 11.1 Diagnostics Control Registers (continued) 11.1.2 GP Testpoint Enable Register The GP testpoint enable register allows individual programming of GP[7:0] bits for either standard operation (as GPIO) or as testpoint outputs. GP testpoint select controls the MUX selection for which testpoints are selected. Refer to Table 91 on page 109 for testpoint assignments for each GP bit. Table 90. Testpoint Enable Registers Byte Address Name Bit(s) Mnemonic 7 6 5 4 3 2 1 0 0x00143 Diag3, GP Testpoint Select 7:0 GT7EB GT6EB GT5EB GT4EB GT3EB GT2EB GT1EB GT0EB GTPSR Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function GP7 is standard GPIO bit (default). GP7 is a testpoint. GP6 is standard GPIO bit (default). GP6 is a testpoint. GP5 is standard GPIO bit (default). GP5 is a testpoint. GP4 is standard GPIO bit (default). GP4 is a testpoint. GP3 is standard GPIO bit (default). GP3 is a testpoint. GP2 is standard GPIO bit (default). GP2 is a testpoint. GP1 is standard GPIO bit (default). GP1 is a testpoint. GP0 is standard GPIO bit (default). GP0 is a testpoint. 0x00142 Diag2, GP Testpoint Enable LLLL LLLL Value for MUX selection of testpoints output to GP[7:0]—see Table 90 on page 108. 108 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 11 Test and Diagnostics (continued) 11.1 Diagnostics Control Registers (continued) 11.1.2 GP Testpoint Enable Register (continued) Table 91. GP[7:0] Internal Testpoint Assignments GP Testpoint Select Value 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 Reserved Reserved DPLL2 lock P_S_SELECTOR Reserved Reserved DPLL1 lock Fallback encoded states: 000 = PRIMARY 001 = TO_PRIMARY 010 = SECONDARY 011 = TO_SECONDARY 100 = FS1 101 = FS2 110 = [reserved] 111 = INITIAL Snapping Reserved Reserved GP7 GP6 GP5 GP4 BYTEREF_16 i_FRAME BYTEREF_8 Reserved Reserved BYTEREF_4 CP8 read Reserved Reserved Reserved BYTEREF_2 CP8 write Reserved Reserved 1000 0000 Stalled — 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 GP3 GP2 GP1 GP0 STATE_COUNT[3:0] (stream) CP4 read CP4 write Reserved Reserved Reserved Reserved Reserved Reserved Fallback flag Phase alignment frame event Go_clocks indicator APLL1 feedback, 8 MHz tap CLEAR_FALLBACK indicator APLL1 feedback, 4 MHz tap FORCE_FALLBACK indicator APLL1 feedback, 2 MHz tap Reserved Reserved Reserved Reserved CP2 read CP2 write Agere Systems Inc. 109 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 11 Test and Diagnostics (continued) 11.1 Diagnostics Control Registers (continued) 11.1.3 State Counter Modes Registers The state counter modes registers control state counter diagnostics, including the breaking of state counter carry chains, using /FR_COMP as the internal frame reference, and allowing the state counter to roll over early via a modulo function. For more details, refer to Section 11.2 on page 112. Table 92. State Counter Modes Registers Byte Address Name Bit(s) Mnemonic 7:0 7:6 5 4 3 2:0 SCMLR Reserved SCMSB FRMSB SCLSB SCULP Value Function 0x00144 Diag4, State Counter Modes Low 0x00145 Diag5, State Counter Modes High LLLL LLLL Lower 8 bits of state counter modulo load value. 00 NOP (default). 0 Normal carry chain operation (default). 1 Break state counter carry chains. 0 Normal internal frame operation (default). 1 Use /FR_COMP as internal frame. 0 Normal counting (default). 1 State counter modulo counting. LLL Upper 3 bits of state counter modulo load value. 11.1.4 Miscellaneous Diagnostics Low Register The miscellaneous diagnostics low register: bits 2 and 1 allow direct reset of the APLL2 and APLL1 feedback dividers. Bit 0 controls the TST input of the power-on reset cell. Table 93. Miscellaneous Diagnostics Low Register Byte Address Name Bit(s) 7:3 2 1 0 Mnemonic Reserved FB2SB FB1SB Reserved Value 00 0 1 0 1 — Function NOP (default). APLL2 feedback divider reset inactive (default). APLL2 feedback divider reset active. APLL1 feedback divider reset inactive (default). APLL1 feedback divider reset active. — 0x00146 Diag6, Miscellaneous Diagnostics Low 110 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 11 Test and Diagnostics (continued) 11.1 Diagnostics Control Registers (continued) 11.1.5 Miscellaneous Diagnostic Registers Table 94. Miscellaneous Diagnostic Registers Byte Address Name Bit(s) Mnemonic 7:0 7:6 5:4 3:2 1:0 7:0 7:0 Reserved ICDSP ICKLP ISYLP IEXLP IASLR CFLLR Value — 00 01 LL LL LL LLLL LLLL Function 0x00147 Diag7 0x00148 Diag8, Interrupt Controller Diagnostic 0x00149 Diag9, Interrupt Controller Deassertion Delay 0x0014A Diag10, Sync-to-frame Command Delay (Lower) 0x0014B Diag11, Sync-to-frame Command Delay (Upper) 7:4 3:0 CFSEN CFHLN NOP. Interrupt controller, normal mode (default). Interrupt controller, DIAG mode. DIAG mode, force CLK[1:0] errors. DIAG mode, force SYS[1:0] errors. DIAG mode, force EXT[8, 0] errors. Programmable delay to control the deassertion time of SYSERR. LLLL LLLL Low byte of 12-bit offset value for sync-toframe clock commands (GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK). 0000 Disable delay mode (default). 0001 Enable delay mode. LLLL Upper 4 bits of 12-bit offset value for sync-to-frame clock commands (GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK). Agere Systems Inc. 111 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 11 Test and Diagnostics (continued) 11.2 Diagnostic Circuit Operation The T8110L internal diagnostic modes are intended primarily for chip manufacturing test. The diagnostic functions include the following: ! DIAG0—3, observability of internal testpoints via FG(7:0), GP(7:0): — Internal testpoints are brought to chip I/O at FG and GP signals. Refer to Table 89 on page 107 and Table 91 on page 109 for testpoint assignment. DIAG4—5, internal state counter diagnostic modes: — Break counter carry chains—this is used in conjunction with monitoring of the state counter bits at FG and GP, and breaks the 11-bit state counter into three separate pieces (bits [10:8], [7:4] and [3:0]). — Shorten frame operation—the internally generated 8 kHz frame is bypassed in favor of the /FR_COMP input. The /FR_COMP input still denotes the frame center and may be presented at a higher frequency than 8 kHz. This is used in conjunction with the state counter modulo function, which when properly programmed allows the internal state counter to roll over coincident with the /FR_COMP frame center. DIAG6, forced RESET of analog APLL1 feedback dividers: — The APLL1 feedback dividers are typically not reset. This diagnostic mode allows each feedback divider to be held in a reset state. DIAG7, reserved. DIAG8, interrupt controller diagnostics: — When the diagnostic mode is enabled (DIAG8 register, bits 7:6 = 01), then bits 5:4 override the CLK error[1:0] inputs, bits [3:2] override the SYS error[1:0] inputs, bit 1 overrides the GP[0] input, and bit 0 overrides the FG[0] input to the interrupt controller. This allows for direct manipulation to set/clear a portion of interrupt bits from each tier group. Please see Section 10.2 on page 103 for more details. DIAG9, interrupt controller deassertion delay: — Allows a programmable deassertion time for the SYSERR signal in between back-to-back interrupts. DIAG10—11, sync-to-frame command delay: — Allows a programmable delay time from the FRAME boundary for execution of the sync-to-frame clock commands, GO_CLOCKS, CLEAR_FALLBACK, FORCE_FALLBACK. ! ! ! ! ! ! 112 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 12 Connection Control 12.1 Programming Interface Programming the T8110L for time-slot switching requires specific access cycles to the connection memory regions. Access to other regions (data memory or registers) is made through a standard direct access via the interface. 12.1.1 Connection Memory Programming Because the microprocessor interface only allows word or byte accesses, multiple write accesses must occur. For byte access, there are a total of three byte-wide holding registers. For word access, there is one word-wide holding register. The user must load the holding registers with the proper information first, and then write to the upper byte (or upper word) to actually move data into the connection memory; refer to Table 95. The connection memory is divided into four 2K regions, each of which handles up to 128 time slots worth of connectivity for each of 16 serial data streams. The regions include H1x0 even streams (CT_D[30, 28, . . . 0]), H1x0 odd streams (CT_D[31, 29, . . . 1]), local low streams (L_D[15:0]), and local high streams (L_D[31:16]). The connection memory locations are addressed relative to time slot and stream. Connection memory commands are as follows: ! RESET PAGE resets any (up to all four) connection memory region (see Figure 21 on page 114). Address bit 15 determines whether or not it's a reset page command. The reset page command relies on a valid internal chip clock and loops through all addresses within the connection memory region, resetting the VALID bit field. The RESET PAGE command is presented as either two microprocessor WORD writes, or four microprocessor BYTE writes, see Table 95. MAKE/BREAK/QUERY, telephony connection (see Figure 22 on page 114). ! The MAKE and BREAK commands are presented as multiple microprocessor write cycles. The QUERY command is presented as multiple microprocessor read cycles; refer to Table 95. Table 95. Microprocessor Programming, Connection Memory Access Word/Byte (WB_SEL) Byte Byte Byte Byte Word Word A[1:0] 00 01 10 11 0X 1X D[15:8] X X X X Data byte 1 Data byte 3 D[7:0] Access Description Data byte 0 Write data byte 0 to a holding register, or read data byte 0 information. Data byte 1 Write data byte 1 to a holding register, or read data byte 1 information. Data byte 2 Write data byte 2 to a holding register, or read data byte 2 information. Data byte 3 Write data byte 3 plus the holding register data to connection memory, or read data byte 3 information. Data byte 0 Write data bytes 1 and 0 to a holding register, or read data bytes 1 and 0 information. Data byte 2 Write data bytes 3 and 2 plus the holding register data to connection memory, or read data bytes 3 and 2 information. Note: Data byte n required information is shown in Figure 22. Agere Systems Inc. 113 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 12 Connection Control (continued) 12.1 Programming Interface (continued) 12.1.1 Connection Memory Programming (continued) A[19:0] 19:16 0100 15 1 14:0 000000000000000 DATA BYTE 1 7:1 0000000 bit 0 DATA BYTE 0 7:1 0000000 bit 0 0 = NO ACTION 1 = RESET LOCAL HI REGION RLH 0 = NO ACTION 1 = RESET LOCAL LO REGION RLL DATA BYTE 3 7:1 0000000 bit 0 DATA BYTE 2 7:1 0000000 bit 0 0 = NO ACTION 1 = RESET H-BUS ODD REGION RHO 0 = NO ACTION 1 = RESET H-BUS EVEN REGION RHE Figure 21. Microprocessor Programming—Reset Page Command 19:16 0100 15 0 14:8 TIME SLOT 6:2 STREAM A[19:0] 7 1:0 H-BUS/LOCAL SELECT: 0 = LOCAL STREAMS 1 = H.1x0 STREAMS HLS WORD/BYTE ADDRESS LSBITS DATA BYTE 1 7:0 TAG (LOWER BITS) DATA BYTE 0 7 0 6:0 SUBRATE DATA BYTE 3 7 0 6:4 000 3 2 1 0 DATA BYTE 2 7:4 0000 3:0 TAG (UPPER BITS) PME VFC 0 = PATTERN MODE DISABLED 1 = PATTERN MODE ENABLED 0 = USE CURRENT FRAME 1 = USE NEXT FRAME RWS 0 = WRITE TO DATA MEMORY 1 = READ FROM DATA MEMORY MBS 0 = MAKE CONNECTION 1 = BREAK CONNECTION 5-9632 (F) Figure 22. Microprocessor Programming—Make/Break/Query Telephony Connections 114 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 12 Connection Control (continued) 12.2 Switching Operation The basic building block of switching is one-half simplex connections loaded into the connection memory. Each connection memory location controls data flow, either from a serial stream input to a location in data memory, or from data memory to a serial stream output. A typical telephony simplex switch connection would use one from and one to connection, each using the same data memory location. 12.2.1 Memory Architecture and Configuration 12.2.1.1 Connection Memory The T8110L connection memory consists of 8192 locations, one location for each of the possible stream/time-slot combinations, to provide a full nonblocking switch for up to 128 time slots on 32 H1x0 streams (CT_D[31:0]) and 32 local streams (L_D[31:0]). Connection memory is physically addressed by time slot (7 bits), H1x0/local select (1 bit), and stream (5 bits). The 8192 locations are divided into four pages of 2048, with each page dedicated to a set of 16 serial streams as follows: ! ! ! ! H1x0 even streams (CT_D[30, 28, . . . 0]) H1x0 odd streams (CT_D[31, 29, . . . 1]) Local high streams (L_D[31:16]) Local low streams (L_D[15:0]) Each of these connection memory pages are initialized at reset (valid bit entries are reset to invalid). Additionally, each page may be initialized individually via software command, RESET PAGE (refer to Figure 21 on page 114). Connection memory locations contain the following control information: ! ! VALID bit indicates that a valid switch connection exists for this stream/time slot. RWS indicates whether the connection is from (from serial stream to data memory) or to (from DATA memory to serial stream). VFC (virtual framing control) controls which data page is used in double-buffer scenarios. Note: There are two data memory configurations that allow double-buffering of the data, in order to create constant frame delay connections. Refer to Section 12.2.1.2 on page 116 and Section 12.2.2.1 on page 117. ! ! ! PME indicates a pattern mode connection. TAG is the data memory location used for this one-half simplex switch connection (or the data pattern sent to serial output for pattern mode connections). SUBRATE information is subrate switching control (bitswap). ! Agere Systems Inc. 115 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.1 Memory Architecture and Configuration (continued) 12.2.1.2 Data Memory The T8110L data memory is 4096 bytes, which can be programmatically configured in three ways, via the data memory mode select register (0x00105; refer to Section 5.1.3 on page 32). DATA MEMORY MODES 0x20000 DATA MEMORY ADDRESSING 0x20000 4K UTILIZED 0x20FFF 0x21000 0x20800 0x20BFF TEL TEL TEL 0x20FFF 0x20000 TEL 0x207FF 4K SINGLEBUFFERED SWITCH (SET BY CONTROL REGISTER 0x00105) 2K SINGLE BUFFERED + 1K DOUBLE BUFFERED 0x20000 TEL 0x207FF TOTAL ADDRESSED SPACE IS 64K TEL 2K DOUBLEBUFFERED SWITCH (RESERVED) 0x2FFFF 5-9638 (F) Figure 23. T8110L Data Memory Map and Configurations 116 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching Standard telephony switching is achieved by loading control fields into the connection memory for one-half simplex connections (refer to Figure 22 on page 114, and Section 12.2.1.1 on page 115). 12.2.2.1 Constant Delay and Minimum Delay Connections The VFC control bit in connection memory determines which of two data pages is accessed, when the data memory is configured to double-buffering for telephony connections (refer to Figure 23). This bit always affects to connections (read the data memory, send it out to a serial stream output) in a double-buffer configuration. This bit can control a from connection in a double-buffer configuration, only if it is a subrate connection; otherwise, the VFC bit has no bearing on from connections. The double-buffering configuration creates two data pages. During a particular frame (125 µs time boundary, partitioned into time slots), one page is the active page, the other is the inactive page. The active/inactive page status toggles at every frame boundary. For all from connections (except for subrate connections), incoming serial data is always written to the active page. For all to connections, the VFC control bit indicates whether to read from the active or inactive page. Manipulation of this bit affects the latency between the incoming from data and the outgoing to data. This latency defines whether or not a connection is constant delay or minimum delay. Please see Appendix A on page 139 for more details on constant and minimum delay connections. 12.2.2.2 Pattern Mode The PME control bit in connection memory affects only to connections. Instead of reading a value out of the data memory for subsequent output to a serial stream, the lower 8 bits of the TAG field provide a byte pattern for the serial output. 12.2.2.3 Subrate The subrate control bit field in connection memory is used only by from connections and controls how individual bits or groups of bits of an incoming serial byte are shuffled prior to writing them to the data memory, in order to achieve subrate switching. Agere Systems Inc. 117 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching (continued) 12.2.2.1 Subrate (continued) Subrate Switching Overview Traditional byte-oriented TDM data switching provides 8 bits of data per time slot, or channel, regardless of the TDM stream bit rate. A particular channel occurs once every 8 kHz frame, and there are 8K frames per second. This allows for a channel data propagation rate of (8 bits/frame * 8K frames/s = 64 kbits/s). Refer to Figure 24 and Table 97. ONE FRAME (8 kHz) 8 Mbits/s 4 Mbits/s 2 Mbits/s 0 0 1 2 1 0 3 4 2 5 6 3 1 7 124 62 125 126 63 31 127 TDM TDM Stream Bit rate = 8MB/s: 8 Mbits/s: has STREAM BIT RATE = each stream EACH STREAM HAS 128 TIME 128 timeslots (channels) per frame FRAME SLOTS (CHANNELS) PER TDM STREAM BIT RATE = 4 Mbits/s: EACH STREAM HAS 64 TIME SLOTS (CHANNELS) PER FRAME TDM STREAM BIT RATE = 2 Mbits/s: EACH STREAM HAS 32 TIME SLOTS (CHANNELS) PER FRAME EACH CHANNEL CONTAINS ONE 8-BIT BYTE, REGARDLESS OF THE TDM DATA STREAM BIT RATE Figure 24. TDM Data Stream Bit Rates Subrate refers to switching fractional portions of the byte-oriented TDM data streams. The T8110L allows the 8 bits of a byte-oriented channel to be broken into multiple channels of fewer bits, either two 4-bit channels, four 2-bit channels, or eight 1-bit channels. This lowers the data propagation rate per channel, but increases the overall channel capacity for a given time slot. Refer to Table 96 and Table 97. Table 96. TDM Data Stream One Time slot (or Channel) Bit Di-Bit Nibble Byte Notes: Bit subrate = 8 channels per time slot, 1 bit per channel. Di-bit = 4 channels per time slot, 2 bits per channel. Nibble subrate = 2 channels per time slot, 4 bits per channel. Byte (no subrate) = 1 channel per time slot, 8 bits per channel. 7 7:6 6 5 5:4 7:4 4 3 3:2 2 1 1:0 3:0 0 7:0 118 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching (continued) 12.2.2.1 Subrate (continued) Subrate Switching Overview (continued) Table 97. Subrate Switching, Data Propagation Rate vs. Channel Capacity Subrate Type Bit Di-bit Nibble Byte (no subrate) Bits per Channel 1 2 4 8 Channel Data Propagation Rate (Bits/Frame x 8K Frames/s) 8 kbits/s 16 kbits/s 32 kbits/s 64 kbits/s Channel Capacity (Relative to Byte Switching) 8X 4X 2X 1X Subrate Switching Using T8110L The H1x0 bus and the local stream bus are based on byte-oriented TDM data streams—data is always switched as whole bytes. The subrate data must be packed into these bytes prior to switching (refer to Sections and ). The data bytes are not necessarily constrained to using fully packed bytes—any portion of a byte may be used. Subrate switching using T8110L requires the following: ! Overall subrate enable mode is activated (register 0x00105, data memory mode select bit 7 is set; see Section 5.1.3 on page 32). The subrate field of the connection memory entry for that switch connection is set up. This field contains 7 bits which control the type of subrate (i.e., bit, di-bit, nibble, or byte), and the data bit shuffling within the TDM byte data, from and to (refer to Figure 22 on page 114, and Table 98). The VFC connection memory bit for cases where a double-buffering configuration is set up in the data memory (refer to Figure 22, and Sections 12.2.1.2, 12.2.2.1). ! ! In order to program a subrate simplex connection, the subrate field is only required for the from half of that connection. Incoming serial byte data has its bit positions rearranged based on the subrate field contents prior to being written into the data memory. For double-buffered data memory configurations, the VFC bit controls which of two data pages the rearranged byte is written to. The to half of a subrate simplex connection simply outputs the entire byte found at the data memory location used for that connection, and its connection memory subrate field is ignored. Agere Systems Inc. 119 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching (continued) 12.2.2.1 Subrate (continued) Subrate Switching Using T8110L (continued) Table 98. Subrate Switching, Connection Memory Programming Setup Subrate Type Bit Subrate Connection Memory Bit Field (6:0) 6 1 5 4 3 2 1 0 000 = to bit 0 000 = from bit 0 001 = to bit 1 001 = from bit 1 010 = to bit 2 010 = from bit 2 011 = to bit 3 011 = from bit 3 100 = to bit 4 100 = from bit 4 101 = to bit 5 101 = from bit 5 110 = to bit 6 110 = from bit 6 111 = to bit 7 111 = from bit 7 Subrate Connection Memory Bit Field (6:0) 4 3 2 1 0 Reserved 00 = to bits[1:0] 00 = from bits[1:0] 01 = to bits[3:2] 01 = from bits[3:2] 10 = to bits[5:4] 10 = from bits [5:4] 11 = to bits[7:6] 11 = from bits[7:6] Subrate Connection Memory Bit Field (6:0) 4 3 2 1 0 0 = from bits[3:0] Reserved 0 = to bits[3:0] 1 = from bits[7:4] 1 = to bits[7:4] Subrate Connection Memory Bit Field (6:0) 4 3 2 1 0 Reserved 6 Di-Bit 01 5 Subrate Type Nibble 6 5 001 6 Byte 5 000 Subrate Packing of Outgoing Bytes The output from subrate connections is always an entire byte so that it does not violate the H.100 or H.110 specifications. The output byte is composed of smaller, i.e., subrate pieces. The process of combining the incoming pieces into a whole byte suitable for output is called packing. In the T8110L (and other subrate-capable Ambassador devices), packing is accomplished by making several from connections for each single to connection. For example, in Figure 25, four from connections (of different stream/time-slot origins), all di-bits, are used to construct a byte that will be output as defined by the to connection. The outgoing to half of a simplex connection reads an entire byte from a data memory location. The packing of separate incoming subrate pieces into this byte is achieved by setting up multiple from one-half simplex connections for one to one-half simplex connection, all using the same data memory location. An example is illustrated in Figure 25. This example shows the packing of four separate incoming di-bits from four different channels into one outgoing byte on one channel. Note: Please note the limitation that multiple di-bits from the same time slot cannot be switched simultaneously. This would require the byte of that time slot to be unpacked first, which is discussed in Section on page 122. 120 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching (continued) 12.2.2.1 Subrate (continued) Subrate Packing of Outgoing Bytes (continued) FRAME (8 kHz) TIME SLOT TIME SLOT BIT POSTITIONS OF DI-BITS WITHIN THE DATA BYTE STREAM a, DI-BIT CHANNELS IN STREAM b, DI-BIT CHANNELS IN STREAM c, DI-BIT CHANNELS IN STREAM d, DI-BIT CHANNELS IN 7: 6 5: 4 n 3: 2 1: 0 7: 6 n+1 5: 4 3: 2 1: 0 7: 6 n+2 5: 4 3: 2 1: 0 7: 6 n+3 5: 4 3: 2 1: 0 7: 6 n + 10 5: 4 3: 2 1: 0 a 1 a 2 a 3 a 4 b 1 b 2 b 3 b 4 c 1 c 2 c 3 c 4 d 1 d 2 d 3 d 4 a 4 d 2 b 4 c 3 STREAM e, DI-BIT CHANNELS OUT Notes: Connectivity is as follows: ! From stream a, time slot n, bits[1:0] to stream e, time slot n + 10, bits[7:6]. ! From stream b, time slot n + 1, bits[1:0] to stream e, time slot n + 10, bits[3:2]. ! From stream c, time slot n + 2, bits[3:2] to stream e, time slot n + 10, bits[1:0]. ! From stream d, time slot n + 3, bits[5:4] to stream e, time slot n + 10, bits[5:4]. Required connection memory programming is as follows: Five 1/2 simplex connections are required to pack four incoming di-bits into an outgoing byte. ! From stream a, time slot n. Connection memory subrate field = 0100X11. ! From stream b, time slot n + 1. Connection memory subrate field = 0100X01. ! From stream c, time slot n + 2. Connection memory subrate field = 0101X00. ! From stream d, time slot n + 3. Connection memory subrate field = 0110X10. ! To stream e, time slot n + 10. Connection memory subrate field is don't care. Figure 25. Subrate Switching Example, Byte Packing Agere Systems Inc. 121 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching (continued) 12.2.2.1 Subrate (continued) Subrate Unpacking of Incoming Bytes Because the H1x0 bus and the local stream bus are based on byte-oriented TDM data streams, and the T8110L architecture is geared towards standard byte switching, it is not possible to simultaneously switch subrate portions of a single byte to different places. This limitation is overcome by application. To gain access to each subrate piece contained in one incoming byte, that byte must be broadcast onto additional channels, one channel for each subrate piece required. The means of broadcasting is up to the application—either the source device of the packed subrate byte can broadcast it, or the device receiving that byte can broadcast it over unused channels and loop the broadcast bytes back in. The example from Figure 25 is extended in Figure 26. This example shows the unpacking of the packed byte created in Figure 25, output to four different channels. 122 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 12 Connection Control (continued) 12.2 Switching Operation (continued) 12.2.2 Standard Switching (continued) 12.2.2.1 Subrate (continued) Subrate Unpacking of Incoming Bytes (continued) FRAME (8 kHz) TIME SLOT TIME SLOT BIT POSITIONS OF DI-BITS WITHIN THE DATA BYTE 7: 6 n+3 5: 4 3: 2 1: 0 7: 6 n+4 5: 4 3: 2 1: 0 7: 6 n+5 5: 4 3: 2 1: 0 7: 6 n+6 5: 4 3: 2 1: 0 7: 6 n+7 5: 4 3: 2 1: 0 7: 6 n+8 5: 4 3: 2 1: 0 BROADCASTED INCOMING BYTE STREAM e, DI-BIT CHANNELS IN a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 a 4 d 2 b 4 c 3 STREAM f, DI-BIT CHANNELS IN (BROADCASTS OF THE ORIGINAL INPUT) STREAM g, DI-BIT CHANNELS OUT STREAM h, DI-BIT CHANNELS OUT STREAM i, DI-BIT CHANNELS OUT STREAM j, DI-BIT CHANNELS OUT a 4 X X c 3 XX XX b 4 X X d 2 X X XX Notes: Connectivity is as follows: From stream e, time slot n + 3, bits[1:0] to stream j, time slot n + 8, bits[7:6]. From stream f, time slot n + 5, bits[3:2] to stream i, time slot n + 8, bits[5:4]. From stream f, time slot n + 6, bits[5:4] to stream h, time slot n + 8, bits[1:0]. From stream f, time slot n + 7, bits[7:6] to stream g, time slot n + 8, bits[7:6]. Required connection memory programming is as follows: Eight 1/2 simplex connections are required to unpack one incoming byte to four separate outgoing di-bits. From stream e, time slot n + 3. Connection memory subrate field = 0100X11. From stream f, time slot n + 5. Connection memory subrate field = 0101X10. From stream f, time slot n + 6. Connection memory subrate field = 0110X00. From stream f, time slot n + 7. Connection memory subrate field = 0111X11. To stream g, time slot n + 8. Connection memory subrate field is don't care. To stream h, time slot n + 8. Connection memory subrate field is don't care. To stream i, time slot n + 8. Connection memory subrate field is don't care. To stream j, time slot n + 8. Connection memory subrate field is don't care. Figure 26. Subrate Switching Example, Byte Unpacking Agere Systems Inc. 123 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Electrical Characteristics 13.1 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage; the table below shows absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 99. Absolute Maximum Ratings Parameter Supply Voltage XTAL1_IN, XTAL2_IN, XTAL1_OUT, XTAL2_OUT pins Voltage Applied to I/O Pins Operating Temperature Storage Temperature 13.1.1 Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 W, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The T8110L has a HBM ESD threshold voltage rating of 1500 V minimum. Symbol VDD — — — Tstg Min — VSS VSS – 0.3 –40 –55 Max 4.2 VDD VDD 5.5 85 125 Unit V V V °C °C 13.2 Crystal Specifications 13.2.1 XTAL1 Crystal The T8110L requires a 16.384 MHz clock source derived from an oscillator or a crystal. If a crystal is used it has to be a 16.384 MHz crystal and must be connected between the XTAL1_IN and the XTAL1_OUT pins. External 24 pF, 5% capacitors must be connected from XTAL1_IN and XTAL1_OUT to Vss, as shown in the diagram below. The ±32 ppm tolerance is the suggested value if the oscillator is used as the clocking source while mastering the bus. Otherwise, a crystal with a lesser tolerance can be used. The crystal specifications are shown below. Table 100. XTAL1 Specifications Parameter Frequency Oscillation Mode Effective Series Resistance Load Capacitance Shunt Capacitance Frequency Tolerance and Stability Value 16.384 MHz Fundamental, parallel resonance 50 Ω maximum 18 pF 7 pF maximum 32 ppm XTAL1_OUT T8110L 24 pF 1 MΩ 24 pF XTAL1_IN 16.384 MHZ CRYSTAL VSS 5-6390f(c) 124 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 13 Electrical Characteristics (continued) 13.2 Crystal Specifications (continued) 13.2.1 XTAL1 Crystal (continued) If an oscillator is used (see Section 6.4.4 on page 61), the signal has to be connected to the XTAL1_IN pin. XTAL1_OUT must be left unconnected in this configuration. XTAL1_IN and XTAL1_OUT are not 5 V tolerant. The oscillator must meet the requirements shown below. Table 101. 16.384 MHz Oscillator Requirements Parameter Frequency Maximum Rise or Fall Time Minimum Pulse Width Low 20 ns 13.2.2 XTAL2 Crystal XTAL2 is an optional crystal oscillator input. If a crystal is used, it has to be a 6.176 MHz or a 12.352 MHz crystal and must be connected between the XTAL2_IN and the XTAL2_OUT pins, as shown in the diagram below. External 24 pF, 5% capacitors must be connected from XTAL2_IN and XTAL2_OUT to Vss. The ±32 ppm tolerance is the suggested value if the oscillator is used as the clocking source while mastering the bus. Otherwise, a crystal with a lesser tolerance can be used (see Table 121). If XTAL2 is not used, XTAL2_IN should be tied to VDD and XTAL2_OUT should be left unconnected. Table 102. XTAL2 Specifications Parameter Frequency Oscillation Mode Effective Series Resistance Load Capacitance Shunt Capacitance Frequency Tolerance and Stability * 120 Ω maximum for 6.176 MHz crystal. † 24 pF for 6.176 MHz crystal also. ‡ 18 pF for 6.176 MHz crystal also. Value 16.384 MHz 10 ns, 10%—90% VDD High 20 ns Value 12.352 MHz Fundamental, parallel resonance 75* Ω maximum 18‡ pF 7 pF maximum 32 ppm 5-6390d XTAL2_OUT 24 pF† T8110L XTAL2_IN 1 MΩ 24 pF† 12.352 MHz CRYSTAL VSS If an oscillator is used (see Section 6.5.1 on page 63), the signal has to be connected to the XTAL2_IN pin. XTAL2_OUT must be left unconnected in this configuration. XTAL2_IN and XTAL2_OUT are not 5 V tolerant. The oscillator must meet the requirements shown below. Table 103. 6.176 MHz/12.352 MHz Oscillator Requirements Parameter Frequency Maximum Rise or Fall Time Minimum Pulse Width Agere Systems Inc. Low 54 ns Value 6.176 MHz 10 ns, 10%—90% VDD High 54 ns Value 12.352 MHz 10 ns, 10%—90% VDD Low 27 ns High 27 ns 125 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Electrical Characteristics (continued) 13.2 Crystal Specifications (continued) 13.2.3 Reset Pulse Table 104. Reset Pulse Parameter RESET# Minimum Pulse Width Min 61 Max — Unit ns 13.3 Thermal Parameters (Definitions and Values) System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 °C, temperature activated failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and integrate their systems. It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ΘJA—Junction to Air Thermal Resistance ΘJA is a number used to express the thermal performance of a part under JEDEC standard natural convection conditions. ΘJA is calculated using the following formula: ΘJA = (TJ – Tamb)/P; where P = power ΘJMA—Junction to Moving Air Thermal Resistance ΘJMA is effectively identical to ΘJA but represents performance of a part mounted on a JEDEC four layer board inside a wind tunnel with forced air convection. ΘJMA is reported at airflows of 200 lft./min and 500 lft./min, which roughly correspond to 1 m/s and 2.5 m/s (respectively). ΘJMA is calculated using the following formula: ΘJMA = (TJ – Tamb)/P ΘJC—Junction to Case Thermal Resistance ΘJC is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. ΘJC is calculated using the following formula: ΘJC = (TJ – TC)/P 126 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 13 Electrical Characteristics (continued) 13.3 Thermal Parameters (Definitions and Values) (continued) ΘJB—Junction to Board Thermal Resistance ΘJB is the thermal resistance from junction to board. This number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. This is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. ΘJB is calculated using the following formula: ΘJB = (TJ – TB)/P ΨJT ΨJT correlates the junction temperature to the case temperature. It is generally used by the customer to infer the junction temperature while the part is operating in their system. It is not considered a true thermal resistance. ΨJT is calculated using the following formula: ΨJT = (TJ – TC)/P Table 105. Thermal Parameter Values Parameter ΘJA ΘJMA (1 m/s) ΘJMA (2.5 m/s) ΘJC ΘJB ΨJT 22 19 17.5 20 TBD 1.0 Temperature °C/Watt 13.4 Reliability Product reliability can be calculated as the probability that the product will perform under normal operating conditions for a set period of time. Factors influencing the reliability of a product cover a range of variables, including design and manufacturing. The failure rate of a product is given as the number of units failing per unit time. This failure rate is known as FIT, which is as follows: 1 FIT = 1 Failure/1x10e9 hours. Another unit used for failure rate is known as MTBF, which is 1/FIT. Many assumptions are made when calculating the failure rate for a product, such as the average junction temperature and activation energy. The assumptions made for calculating FIT and MTBF are shown in Table 106: Table 106. Reliability Data Junction Temperature 55 °C FIT (Per 10e9 Device Hours 10 MTBF 1.0e hours 8 Activation Energy .7eV Agere Systems Inc. 127 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Electrical Characteristics (continued) 13.5 dc Electrical Characteristics 13.5.1 Electrical Drive Specifications, CT_C8 and /CT_FRAME VDD = 3.3 V and VSS = 0.0 V, unless otherwise specified. Table 107. Electrical Drive Specifications, CT_C8 and /CT_FRAME Parameter Output High Voltage Output Low Voltage Positive-going Threshold Negative-going Threshold Hysteresis (Vt+—Vt–) Input Pin Capacitance Symbol VOH VOL Vt+ Vt– VHYS CIN Condition IOUT = –24 mA IOUT = 24 mA — — — — Min 2.4 –0.25 1.2 0.6 0.4 — Max 3.3 0.4 2.0 1.6 — 10 Unit V V V V V pF PCI-compliant data line I/O cells are used for the CT bus data lines. (See PCI Specification, Rev. 2.2, Chapter 4.) /C16, /C4, C2, SCLK, /SCLKx2, and /FR_COMP all use the same driver/receiver pairs as those specified for the CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.1x0 specification. 128 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 13 Electrical Characteristics (continued) 13.5 dc Electrical Characteristics (continued) 13.5.2 All Other Pins VDD = 3.3 V and Vss = 0.0 V, unless otherwise specified. Table 108. dc Electrical Characteristics, All Other Pins Parameter Supply Current Supply Voltage Input High Voltage Input Low Voltage Input Current Input Capacitance (input only) Input Capacitance (I/O pins) Leakage Current (3-state) Input Clamp Voltage Output High Voltage Output Low Voltage Output Short-circuit Current Symbol IDD VDD VIH VIL II CI CIO ILEAK VC VOH VOL IOS Condition 2000 H-bus/L-bus connections — — — — — — — — I = 8 mA I = 8 mA VOH tied to GND Min — 3.0 2.0 — — — — — — 2.4 — — Typ 300 — — — — — — — — — — — Max — 3.6 — 0.8 1 5 10 10 –1.0 — 0.4 100 Unit mA V V V µA pF pF µA V V V mA 13.6 H-Bus Timing 13.6.1 Timing Diagrams /CT_FRAME (A/B) CT_C8 (A/B) /FR_COMP /C16 C2 /C4 SCLK (2.048 MHz) /SCLKx2 (2.048 MHz MODE) SCLK (4.096 MHz MODE) /SCLKx2 (4.096 MHz MODE) SCLK (8.192 MHz MODE) /SCLKx2 (8.192 MHz MODE) FRAME BOUNDARY 5-6119F Figure 27. Clock Alignment Agere Systems Inc. 129 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Electrical Characteristics (continued) 13.6 H-Bus Timing (continued) 13.6.1 Timing Diagrams (continued) FRAME BOUNDARY 125 µs /CT_FRAME CT_C8 CT_DX 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 TIME SLOT 0 127 Note: Bit 1 is the MSB and Bit 8 is the LSB. MSB is always transmitted first in all transfers. 5-6120F Figure 28. Frame Timing Diagram Vt+ CT_C8_A CT_C8_A Vt+ tSKC8 tSKCOMP Vt+ CT_C8_B COMPATIBILITY CLOCKS Vt+ Vt– tSKCOMP 5-6122F Figure 29. Detailed Clock Skew Timing Diagram 13.7 ac Electrical Characteristics 13.7.1 Skew Timing, H-Bus Table 109. Skew Timing, H-Bus Symbol tSKC8 — Parameter Maximum Skew Between CT_C8_A and CT_C8_B* †‡ § Maximum Skew Between CT_C8_A and L_SCx Clock* Min — — — Typical — — — Max ±10, ±Φ ±5 ±2 Unit ns ns ns TSKCOMP Maximum Skew Between CT_C8_A and any Compatibility Clock* * Test load—50 pF. † Assumes A and B masters in adjacent slots. ‡ When static skew is 10 ns and in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum skew of 30 ns will occur during that clock cycle. § Meeting the skew requirements in Table 109 and the requirements of Section 15.5 H-Bus Timing on page 129 could require the PLLs generating CT_C8 to have different time constants when acting as primary and secondary clock masters. 130 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 13 Electrical Characteristics (continued) 13.7 ac Electrical Characteristics (continued) 13.7.1 Skew Timing, H-Bus (continued) Table 110. L_SC[3:0] and Frame Group Rise and Fall Time Parameter L_SCx Rise Time L_SCx Fall Time Frame Group Rise Time Frame Group Fall Time * Worst-case loading of 50 pF on all outputs. Min — — — — Typ — — — — Max 5 4 3 3 Unit* ns ns ns ns 13.8 Hot Swap The T8110L has features which assist in H.110 hot swap applications. All H.110 bus signals are put in high impedance (3-state and/or input) during the early power phase of board insertion/removal. The ECTF H.110 specification requires that all CT data lines and CT_NETREF clocks have 0.7 V applied through 18 kΩ resistors before plugging into and releasing from the H.110 bus. A feature on the T8110L incorporates all 34 18 kΩ precharge resistors internally (32 for the CT data signals, 2 for NETREFs). These resistors accept 0.7 V directly through the VPRECHARGE input. The ECTF H.110 specification requires that the T8110L must be powered from early power in hot swap applications. The circuit that generates the 0.7 V precharge voltage must also be powered from early power. Refer to ECTF H.110 and PICMG CompactPCI ® Hot Swap specifications for hot swap requirements. 13.8.1 LPUE (Local Pull-Up Enable) LPUE is used as an assist in CompactPCI specifically for hot swap; see Section 2.3.2 on page 20. During live board insertion/removal, the only devices which should be on early power are the power controller and interface parts (PCI interface attached to J1, H.110 interface attached to J4). Without the LPUE, any device connected to the T8110L would get current flow from the early power through the pull-up resistors. When late power parts power up, they already have current flowing through the I/O and these devices could possibly latch up. The current flow is eliminated by LPUE disabling the pull-up resistors. LPUE is typically controlled by the power controller. The power controller will pull LPUE low during board insertion/removal and will release LPUE high so that the pull ups are reenabled with late power turning on. Signals that have pull-ups disabled by LPUE are GP[7:0], FG[7:0], D[15:0], LD[31:0], LREF[7:0], PRI_REF_IN, NR1_DIV_IN, and NR2_DIV_IN. 13.9 Decoupling Decoupling the T8110L VDDs with 0.1 µF capacitors is recommended. 1000 pF or 0.01 µF capacitors may be used in addition to the 0.1 µF capacitors to provide additional decoupling. Agere Systems Inc. 131 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Electrical Characteristics (continued) 13.10 APLL VDD Filter Separate VDDs are provided for APLL1 and APLL2 for filtering purposes. VDD filtering will provide stability in the APLL, primarily the VCOs. An R/C low pass filter should be applied to the PLL VDDs, see Figure 30. Depending on the quality of VDD and board layout characteristics, the R/C values should be selected to filter out unwanted frequencies above a targeted frequency. For example, a 25 Ω resistor and 10 µF capacitor will have a cut-off frequency of 636 Hz. Characterize the quality of your VDD and select component values accordingly. 25 Ω is the maximum recommended resistor value. At high frequencies the ESR of a bulk cap becomes a problem (no longer effectively low passes) so a high-frequency cap of 0.1 µF or so is required to compensate for some of the higher clocks and various harmonics. This needs to be placed as close to the T8110L device as possible to minimize the radiational pick-up in the remaining trace length. APLL1 and APLL2 each draw approximately 7 mA at 3.3 V. Hot swap applications can use late power to ensure the capacitance and in-rush current do not violate the PICMG Hot Swap specification. VDD = 3.3 V R APLL1VDD C 0.1 µF VSS T8110L VDD = 3.3 V R APLL2VDD C 0.1 µF VSS 0995(F) Figure 30. APLL VDD Filtering 132 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 13 Electrical Characteristics (continued) 13.11 PC Board PBGA Considerations The T8110L is a 272-ball plastic ball grid array package. The 16 centrally located thermal balls should be connected to board ground. While there are no special printed-circuit board requirements for the T8110L, there are specification requirements for PC board layout that must be adhered to. For instance, per the ECTF H.110 specification, all CT bus data signals must not exceed 4 inches in length from connector to I/O cell and all CT bus clock signals must not exceed 2 inches in length from connector to I/O cell. We advise the customer to become familiar with applicable specifications for any PC board requirements. 13.12 Unused Pins Multiple pins may share a common resistor. Signals with pull-up/down resistors may be left unconnected if unused. Unused 8 mA 3-state signals may be left unconnected. If XTAL1_IN and/or XTAL2_IN are being driven from an oscillator, then XTAL1_OUT and/or XTAL2_OUT must be left unconnected. If XTAL2 is not used, XTAL2_IN should be pulled-up or tied directly to VDD and XTAL2_OUT should be left unconnected. If VPRECHARGE is unused, this signal may be left unconnected. All signals listed as no connect (D16, D20, E17, and G17) in Table 8 must be left unconnected. 13.13 External Pull-Up Pins The EPU pins must be tied to an external pull-up resistor. Multiple pins may share a common resistor. It is recommended that all EPU pins be tied to a commmon 20 kΩ pull-up resistor. 13.14 T8110L Evaluation Kits There is no T8110L-specific evaluation kit. If an evaluation kit is required, please purchase a T8110 PCI evaluation kit, as the evaluation board allows the T8110 to be configured to be functionally identical to the T8110L. Each kit contains an evaluation board, software, and documentation. The evaluation board is a full-length PCI board and it includes the T8110 chip, a PCI-to-local bus bridge, a dual T1/E1 line interface, a dual codec, and a dual SLIC. The software includes full source code, including rights to reuse. The documentation CD includes evaluation board schematics (ORCAD and .pdf formats), evaluation board bill of material (BOM), and advisories. Please refer to the website http://www.agere.com/enterprise_metro_access/tdm_interconnect.html for additional information. 13.15 T8110L Ordering Information Table 111. T8110L Ordering Information Device Part Number T-8110L---BAL-DB Package 272-Ball PBGA Comcode 700052229 Agere Systems Inc. 133 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Package Outline (continued) 13.15 Pin and Pad Assignments (continued) LOCAL REFERENCE INPUTS H-BUS DATA H.110 CLOCKS EXTERNAL CLADs/DJATs A PRECHARGE B C D E GPIO F G µPROCESSOR ADDRESS H J K L M µPROCESSOR CONTROL SIGNALS N P R T µPROCESSOR DATA U V W Y RESET VSS PLL (XTAL#1) VSS VDD VSS VDD VSS VDD VSS PLL (XTAL#2) BIST VDD H.110 PE H.100 PE COMPATIBILITY CLOCKS PLL MLAC JTAG PORT VDD VSS (N/C) VSS LOCAL CLOCK OUTPUTS VDD LOCAL PE VDD VSS EPU THERMAL GROUND VDD VSS LOCAL DATA VDD VSS VSS VDD VSS VDD VSS VSS VDD VSS FRAME GROUP 1 2 3 EPU (NO CONNECT) 4 5 6 7 8 VSS 9 10 11 EPU 12 13 14 15 16 VSS (NO CONNECT) 17 18 19 20 ERROR SIGNALS 5-8906F(b). Figure 31. T8110L Pins by Functional Group 134 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 13 Package Outline (continued) 13.15 Pin and Pad Assignments (continued) 19 SPACES @ 1.27 = 24.13 19 20 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y A1 BALL PAD CORNER +0.14 0.76 –0.16 19 SPACES @ 1.27 = 24.13 5-4406 BOTTOM VIEW Agere Systems Inc. 135 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 13 Package Outline (continued) 13.15 Pin and Pad Assignments (continued) +0.04 0.36 –0.06 1.17 ± 0.05 +0.19 2.13 –0.21 SEATING PLANE 0.20 0.60 ± 0.10 SOLDER BALL 5-4406 SIDE VIEW 27.00 A1 BALL PAD CORNER +0.70 24.00 –0.50 +0.70 24.00 –0.50 27.00 5-4406 TOP VIEW 136 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch 14 JTAG/Boundary Scan 14.1 The Principle of Boundary-Scan Architecture Each primary input signal and primary output signal is supplemented with a multipurpose memory element called a boundary-scan cell. Cells on device primary inputs are referred to as input cells and cells on primary outputs are referred to as output cells. Input and output is relative to the core logic of the device. At any time, only one register can be connected from TDI to TDO. For example, instruction register (IR), bypass, boundary-scan, ident, or even some appropriate register internal to the core logic (see Figure 32). The selected register is identified by the decoded output of the instruction register. Certain instructions are mandatory, such as EXTEST (boundary-scan register selected), whereas others are optional, such as the IDCODE instruction (Ident register selected). INTERNAL CORE LOGIC TDI TEST DATA IN BYPASS IDENTIFICATION REGISTER INSTRUCTION REGISTER (IR) TDO TEST DATA OUT TEST MODE SELECT TEST CLOCK TMS TCK TAP CONTROLLER TEST RESET (TRSTN) Figure 32. IEEE® 1149.1 Boundary-Scan Architecture Figure 32 shows the following elements: ! A set of four dedicated test pins, test data in (TDI), test mode select (TMS), test clock (TCK), test data out (TDO), and one optional test pin test reset (TRSTN). These pins are collectively referred to as the test access port (TAP). A boundary-scan cell on each device’s primary input and primary output pin, connected internally to form a serial boundary-scan register (boundary scan). A finite-state machine TAP controller with inputs TCK and TMS. An n-bit (n = 3) instruction register (IR), holding the current instruction. A 1-bit bypass register (BYPASS). An optional 32-bit identification register (ident) capable of being loaded with a permanent device identification code. ! ! ! ! ! Agere Systems Inc. 137 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 14 JTAG/Boundary Scan (continued) 14.1.1 Instruction Register The instruction register is 3 bits long and the capture value is 001. Table 112. Instruction Register Instruction EXTEST SAMPLE IDCODE BYPASS HIGH Z Binary Code 000 001 101 110, 111 010 Description Places the boundary-scan register in EXTEST mode. Places the boundary-scan register in sample mode. Identification code. Places the bypass register in the scan chain. Places all outputs and I/Os in 3-state mode. 14.2 Boundary-Scan Register The T8110L boundary scan register is identical to that of the T8110 in the condition that the T8110’s VIO/uP_SELECT pin is tied to ground. The only difference is that for the T8110L, this pin (U5) is internally tied to ground. Please refer to the T8110 datasheet for the bit-to-pin assignment. 138 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix A. Constant and Minimum Delay Connections A.1 Connection Definitions A forward connection is defined as one in which the output to time slot has a greater value than the input from time slot, or, put another way, the delta between them is positive. A reverse connection is defined as one in which the output to time slot has a lesser value than the input from time slot, and the delta between them is negative. For example, going from TS(1) to TS(38) is a forward connection, and the TS∆ is +37, but going from TS(38) to TS(1) is a reverse connection, with a TS∆ of –37: where TS∆ = TS(to) – TS(from). Similarly, a delta can be introduced for streams which will have a bearing in certain exceptions (discussed later): STR∆ = STR(to) – STR(from). There is only one combination which forms a TS∆ of +127 or –127: TS∆ = TS(127) – TS(0) = +127, and TS∆ = TS(0) – TS(127) = –127, but there are two combinations which form TS∆s of +126 or –126: TS∆ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and TS∆ = TS(1) – TS(127) = TS(0) – TS(126) = –126, there are three combinations which yield +125 or –125, and so on. The user can utilize the TS∆ to control the latency of the resulting connection. In some cases, the latency must be minimized. In other cases, such as a block of connections which must maintain some relative integrity while crossing a frame boundary, the required latency of some of the connections may exceed a one frame (>128 time slots) to maintain the integrity of this virtual frame. The device uses a control bit at each connection memory location, VFC, for controlling latency, allowing each connection to select one of two alternating data buffers. A.2 Delay Type Definitions Constant Delay—This is a well-defined, predictable, and linear region of latency in which the to time slot is at least 128 time slots after the from time slot, but no more than 256 time slots after the from time slot. Mathematically, constant delay latency is described as follows*, with L denoting latency, and VFC set to the value indicated: Forward connections, VFC = 1: L = 128 + TS∆ (0 ≤ TS∆ ≤ 127) Reverse connections, VFC = 0: L = 256 + TS∆ (–127 ≤ TS∆ ≤ –1) Example: Switching from TS(37) to TS(1) as a constant delay, the delta is –36, so FME is set to 0 and the resulting latency is 256 – 36 = 220 time slots. Thus, the connection will be made from TS(37) of frame(n) to TS(1) of frame(n + 2). Use constant delay for latencies of 128 to 256 time slots, set VFC = 1 for forward connections, set VFC = 0 for reverse connections. Simple summary: * Since TS∆ = TS(to) –TS(from), the user can modify the equations to solve for either TS(to) or TS(from). Agere Systems Inc. 139 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix A. Constant and Minimum Delay Connections (continued) A.2 Delay Type Definitions (continued) 127 255 C VF =1 APPLIED DELTA (TIME SLOTS) 0 128 RESULTING LATENCY (TIME SLOTS) =0 256 VF C –127 129 Figure 33. Constant Delay Connection Latency Minimum Delay—This is the most common type of switching, but has a shorter range than constant delay, and the user must be aware of exceptions caused by interactions between the device's internal pipeline and the dual buffering. The to time slot is at least 3 time slots after the from time slot, but no more than 128 time slots after the from time slot. Exceptions exist at TS∆s of +1, +2, –126, and –127. Forward connections, VFC = 0: L = TS∆ (3 ≤ TS∆ ≤ 127). Reverse connections, VFC = 1: L = 128 + TS∆ (–125 ≤ TS∆ ≤ 0). Example: Using the same switching from the example above, TS(37) to TS(1), the delta is –36, so VFC is set to 1 to effect the minimum delay (setting to 0 effects constant delay), and the resulting latency is 128 – 36 = 92 time slots. The relative positions of the end time slots are the same in both minimum and constant delay, i.e., they both switch to TS(1)], but the actual data is delayed by an additional frame in the constant delay case. Use minimum delay for latencies of 3 to 128 time slots, set VFC = 0 for forward connections, set VFC = 1 for reverse connections. Simple summary: Exceptions to Minimum Delay—Up until this point in the discussion, the STR∆s have not been discussed because the to and from streams have been irrelevant in the switching process. Note: The one universally disallowed connection on the device is a TS∆ of 0 and a STR∆ of 0. This is, of course, a stream + time-slot switching to itself! Rather than try to list the exceptions mathematically, a table is provided. The latencies in these cases may exceed two frames due to the interaction of the intrinsic pipeline delays with the double buffering. 140 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix A. Constant and Minimum Delay Connections (continued) A.2 Delay Type Definitions (continued) Table 113. Special Cases (Exceptions) VFC Value 0 0 1 1 TS∆ +1 +2 –126 –127 Latency for STR∆ < 0 257 258 258 257 Latency for STR∆ ≥ 0 257 2 2 257 Graphically, the minimum delay latency equations are illustrated below. The exceptions to the minimum delay have been included in the diagram, connected to the main function by dashed lines. 127 127 VF C =0 2 APPLIED DELTA (TIME SLOTS) SPECIAL LONG LATENCY CONNECTIONS (SEE TEXT) 258 2 0 0 RESULTING LATENCY (TIME SLOTS) =1 128......256 C VF –126 –127 2 257 5-6224 Figure 34. Minimum Delay Connection Latency Lower Stream Rates—The discussion has centered on 128 time-slot frames which correspond to 8.192 Mbits/s data rates. How does one make similar predictions for lower stream rates? For 4.096 Mbits/s, multiply the to and from time-slot values by two, i.e., time slot 0 at 4.096 Mbits/s corresponds to time slot 0 at 8.192 Mbits/s, and time slot 63 at 4.096 Mbits/s corresponds to time slot 126 at 8.192 Mbits/s. Similarly, multiply values by four to convert 2.048 Mbits/s values. The latency equations can then be applied directly. Agere Systems Inc. 141 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary Key to using the table below: ! ! Five character alphanumeric designation Character 4 indicates the general register type as follows: — Divide = load value for divider — Enable = bit or bits to enable a function — Load = load value, typically for counter — Output = output only — Select = bit or bits select multiple functions Character 5 indicates the size as follows: — B = bit — N = nibble — P = partial register (2, 3, 5, 6, or 7 bits) — R = register Position column identifies the bit position in the register: — 0, 1, 2, 3, 4, 5, 6, 7 for bits — L for lower nibble — U for upper nibble — n-m for bit positions in a partial register ! ! 142 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name Mnemonic ABOEN ACRSN AIOEB BCRSN C2FEB C2LOB C2TOB C2WEB C4FEB C4LOB C4TOB C4WEB CAFEB CALOB CATOB CAWEB CAWSN CBFEB CBLOB CBTOB CBWEB CBWSN CCOEN CCSEN CFBOB CFHLN CFLLR CFPOB CFSEN CFSOB CKMDR CKMSR CKRDR CMFEB CMLOB CMTOB CMWEB CPFEB CPLOB CPTOB CPWEB CSASR D1FEB D1ISR Description A and B clocks output A clocks rate All I/O (master) B clocks rate C2 fallback trigger C2 latched error C2 transient error C2 watchdog /C4 fallback trigger C4 latched error C4 transient error /C4 watchdog C8A fallback trigger C8A latched error C8A transient error C8A watchdog C8A watchdog C8B fallback trigger C8B latched error C8B transient error C8B watchdog C8B watchdog C clocks output C clocks separate Fallback status Diag sync-to-frame high Diag sync-to-frame low CLEAR_FALLBACK pending Diag sync-to-frame EN Failsafe status Clock main Clock main Clock resource /C16– fallback trigger /C16– latched error /C16– transient error /C16– watchdog /C16+ fallback trigger /C16+ latched error /C16+ transient error /C16+ watchdog Clock set access DPLL1 sync trigger DPLL1 input Type Enable Select Enable Select Enable Output Output Enable Enable Output Output Enable Enable Output Output Enable Select Enable Output Output Enable Select Enable Enable Output Load Load Output Enable Output Divide Select Divide Enable Output Output Enable Enable Output Output Enable Select Enable Select Register 0x00220 0x00223 0x00103 0x00223 0x0010A 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00120 0x0010E 0x0010C 0x0010A 0x00122 0x00120 0x0010E 0x0010C 0x00220 0x00224 0x00127 0x0014B 0x0014A 0x00124 0x0014B 0x00127 0x00201 0x00200 0x00205 0x0010A 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00120 0x0010E 0x00106 0x0010B 0x0020A Bit Position U L 7 U 5 5 5 5 4 4 4 4 0 0 0 0 L 1 1 1 1 U L L 6 L — 1 U 7 — — — 3 3 3 3 2 2 2 2 — 5 — 143 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic D1LOB D1RSR D1TOB D1WEB D2FEB D2ISR D2LOP D2RSR D2TOB D2WEB DMMSP F0DSB F0IOB F0ISB F0LLR F0MEB F0RSR F0ULR F0WSP F1DSB F1IOB F1ISB F1LLR F1MEB F1RSR F1ULR F1WSP F2DSB F2IOB F2ISB F2LLR F2MEB F2RSR F2ULR F2WSP F3DSB F3IOB F3ISB F3LLR F3MEB F3RSR F3ULR F3WSP 144 Description DPLL1 sync latched error DPLL1 rate DPLL1 sync transient error DPLL1 sync watchdog DPLL2 sync trigger DPLL2 input DPLL2 lock status DPLL2 rate DPLL2 sync transient error DPLL2 sync watchdog Data memory mode FGIO 0 R/W direction FGIO 0 data Frame 0 pulse inversion Frame 0 lower start time FGIO 0 read mask Frame 0 pulse width rate Frame 0 upper start time Frame 0 pulse width FGIO 1 R/W direction FGIO 1 data Frame 1 pulse inversion Frame 1 lower start time FGIO 1 read mask Frame 1 pulse width rate Frame 1 upper start time Frame 1 pulse width FGIO 2 R/W direction FGIO 2 data Frame 2 pulse inversion Frame 2 lower start time FGIO 2 read mask Frame 2 pulse width rate Frame 2 upper start time Frame 2 pulse width FGIO 3 R/W direction FGIO 3 data Frame 3 pulse inversion Frame 3 lower start time FGIO 3 read mask Frame 3 pulse width rate Frame 3 upper start time Frame 3 pulse width Type Output Select Output Enable Enable Select Output Select Output Enable Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Register 0x00123 0x0020B 0x00121 0x0010F 0x0010B 0x0020E 0x00125 0x0020F 0x00121 0x0010F 0x00105 0x00482 0x00480 0x00402 0x00400 0x00481 0x00403 0x00401 0x00402 0x00482 0x00480 0x00412 0x00410 0x00481 0x00413 0x00411 0x00412 0x00482 0x00480 0x00422 0x00420 0x00481 0x00423 0x00421 0x00422 0x00482 0x00480 0x00432 0x00430 0x00481 0x00433 0x00431 0x00432 Bit Position 5 — 5 5 6 — 3:2 — 6 6 6:0 0 0 7 — 0 — — 6:0 1 1 7 — 1 — — 6:0 2 2 7 — 2 — — 6:0 3 3 7 — 3 — — 6:0 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic F4DSB F4IOB F4ISB F4LLR F4MEB F4RSR F4ULR F4WSP F5DSB F5IOB F5ISB F5LLR F5MEB F5RSR F5ULR F5WSP F6DSB F6IOB F6ISB F6LLR F6MEB F6RSR F6ULR F6WSP F7DSB F7IOB F7ISB F7LLR F7MEB F7MSR F7RSR F7SSP F7ULR F7WSN F7WSP FAFEB FALOB FATOB FAWEB FB1SB FB2SB FBCSR FBFEB Description FGIO 4 R/W direction FGIO 4 data Frame 4 pulse inversion Frame 4 lower start time FGIO 4 read mask Frame 4 pulse width rate Frame 4 upper start time Frame 4 pulse width FGIO 5 R/W direction FGIO 5 data Frame 5 pulse inversion Frame 5 lower start time FGIO 5 read mask Frame 5 pulse width rate Frame 5 upper start time Frame 5 pulse width FGIO 6 R/W direction FGIO 6 data Frame 6 pulse inversion Frame 6 lower start time FGIO 6 read mask Frame 6 pulse width rate Frame 6 upper start time Frame 6 pulse width FGIO 7 R/W direction FGIO 7 data Frame 7 pulse inversion Frame 7 lower start time FGIO 7 read mask Frame 7 mode Frame 7 pulse width rate FG7 timer pulse shape Frame 7 upper start time FG7 timer pulse width Frame 7 pulse width /FRAMEA fallback trigger /FRAMEA latched error /FRAMEA transient error /FRAMEA watchdog APLL1 feedback reset APLL2 feedback reset Fallback control /FRAMEB fallback trigger Type Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Load Select Select Load Enable Load Enable Select Select Select Load Select Select Enable Output Output Enable Select Select Select Enable Register 0x00482 0x00480 0x00442 0x00440 0x00481 0x00443 0x00441 0x00442 0x00482 0x00480 0x00452 0x00450 0x00481 0x00453 0x00451 0x00452 0x00482 0x00480 0x00462 0x00460 0x00481 0x00463 0x00461 0x00462 0x00482 0x00480 0x00472 0x00470 0x00481 0x00476 0x00473 0x00477 0x00471 0x00477 0x00472 0x0010B 0x00123 0x00121 0x0010F 0x00146 0x00146 0x00108 0x0010B Bit Position 4 4 7 — 4 — — 6:0 5 5 7 — 5 — — 6:0 6 6 7 — 6 — — 6:0 7 7 7 — 7 — — — — L 6:0 0 0 0 0 1 2 — 1 145 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic FBFOB FBLOB FBSOP FBTOB FBWEB FCFEB FCISB FCLLR FCLOB FCTOB FCULR FCWEB FFPOB FGREB FPASR FRMSB FRSEN FRWSR FSCSR FSEER FSLOB FSMSN FSSSR FSTOB FSWEB FT0EB FT1EB FT2EB FT3EB FT4EB FT5EB FT6EB FT7EB FTPSR FTRSN G0DSB G0IOB G0MEB G0OEB G1DSB G1IOB G1MEB G1OEB 146 Description Fallback enable status /FRAMEB latched error Fallback states /FRAMEB transient error /FRAMEB watchdog /FR_COMP fallback trigger FG7 timer invert output Frame group 7 lower count /FR_COMP latched error /FR_COMP transient error Frame group 7 upper count /FR_COMP watchdog FORCE_FALLBACK pending Frame group Frame phase alignment Diag /FR_COMP input /FR_COMP separate /FR_COMP width Failsafe return command Failsafe enable Failsafe latched error Fallback secondary mode Failsafe sensitivity Failsafe transient error Failsafe watchdog FG0 testpoint FG1 testpoint FG2 testpoint FG3 testpoint FG4 testpoint FG5 testpoint FG6 testpoint FG7 testpoint FG testpoint MUX Fallback type GPIO 0 R/W direction GPIO 0 data GPIO 0 read mask GPIO 0 override GPIO 1 R/W direction GPIO 1 data GPIO 1 read mask GPIO 0 override Type Output Output Output Output Enable Enable Select Load Output Output Load Enable Output Enable Select Select Enable Select Select Enable Output Select Select Output Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Load Enable Enable Select Load Enable Enable Register 0x00124 0x00123 0x00124 0x00121 0x0010F 0x0010B 0x00477 0x00474 0x00123 0x00121 0x00475 0x0010F 0x00124 0x00103 0x00107 0x00145 0x00224 0x00222 0x00114 0x00115 0x00123 0x00109 0x00116 0x00121 0x0010F 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00141 0x00109 0x00502 0x00500 0x00501 0x00503 0x00502 0x00500 0x00501 0x00503 Bit Position 7 1 6:4 1 1 2 7 — 2 2 — 2 0 5 — 4 U — — — 7 L — 7 7 0 1 2 3 4 5 6 7 — U 0 0 0 0 1 1 1 1 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic G2DSB G2IOB G2MEB G3DSB G3IOB G3MEB G4DSB G4IOB G4MEB G5DSB G5IOB G5MEB G6DSB G6IOB G6MEB G7DSB G7IOB G7MEB GOPOB GPIEB GSREB GT0EB GT1EB GT2EB GT3EB GT4EB GT5EB GT6EB GT7EB GTPSR HARSN HBRSN HCKEB HCRSN HDBEB HDRSN HERSN HFRSN HGRSN HHRSN HRBEB IASLR ICDSP Description GPIO 2 R/W direction GPIO 2 data GPIO 2 read mask GPIO 3 R/W direction GPIO 3 data GPIO 3 read mask GPIO 4 R/W direction GPIO 4 data GPIO 4 read mask GPIO 5 R/W direction GPIO 5 data GPIO 5 read mask GPIO 6 R/W direction GPIO 6 data GPIO 6 read mask GPIO 7 R/W direction GPIO 7 data GPIO 7 read mask Go clocks pending General purpose I/O Global subrate GP0 testpoint GP1 testpoint GP2 testpoint GP3 testpoint GP4 testpoint GP5 testpoint GP6 testpoint GP7 testpoint GP testpoint MUX H1x0 group A rate H1x0 group B rate H1x0 clocks H1x0 group C rate H1x0 data bus H1x0 group D rate H1x0 group E rate H1x0 group F rate H1x0 group G rate H1x0 group H rate Hard reset of back end Diag, SYSERR assertion Diag, internal control mode Type Select Load Enable Select Load Enable Select Load Enable Select Load Enable Select Load Enable Select Load Enable Output Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Enable Select Enable Select Select Select Select Select Enable Load Select Register 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00502 0x00500 0x00501 0x00124 0x00103 0x00105 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00143 0x00300 0x00300 0x00103 0x00301 0x00103 0x00301 0x00302 0x00302 0x00303 0x00303 0x00101 0x00149 0x00148 Bit Position 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 2 4 7 0 1 2 3 4 5 6 7 — L U 3 L 2 U L U L U 1 — 7:6 147 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic ICKLP ICMSB IDHOR IDLOR IEXLP IF0SB IF1SB IF2SB IF3SB IF4SB IF5SB IF6SB IF7SB IG0SB IG1SB IG2SB IG3SB IG4SB IG5SB IG6SB IG7SB IR0SB IR1SB IR2SB IR3SB IR4SB IR5SB IR6SB IR7SB ISYLP JAMSR JC0EB JC0OB JC1EB JC1OB JC2EB JC2OB JC3EB JC3OB JC4EB JC4OB JC5EB Description Diag, internal control CLKERR Invert clock main Device ID high Device ID low Diag, internal control EXTERR Invert interrupt FGIO 0 Invert interrupt FGIO 1 Invert interrupt FGIO 2 Invert interrupt FGIO 3 Invert interrupt FGIO 4 Invert interrupt FGIO 5 Invert interrupt FGIO 6 Invert interrupt FGIO 7 Invert interrupt GPIO 0 Invert interrupt GPIO 1 Invert interrupt GPIO 2 Invert interrupt GPIO 3 Invert interrupt GPIO 4 Invert interrupt GPIO 5 Invert interrupt GPIO 6 Invert interrupt GPIO 7 Invert local reference 0 Invert local reference 1 Invert local reference 2 Invert local reference 3 Invert local reference 4 Invert local reference 5 Invert local reference 6 Invert local reference 7 Diag, internal control SYSERR Interrupt arbitration mode Interrupt from CLKERR 0 Interrupt pending CLKERR 0 Interrupt from CLKERR 1 Interrupt pending CLKERR 1 Interrupt from CLKERR 2 Interrupt pending CLKERR 2 Interrupt from CLKERR 3 Interrupt pending CLKERR 3 Interrupt from CLKERR 4 Interrupt pending CLKERR 4 Interrupt from CLKERR 5 Type Load Select Output Output Load Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Load Select Enable Output Enable Output Enable Output Enable Output Enable Output Enable Register 0x00148 0x00204 0x0012B 0x0012A 0x00148 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x00148 0x00610 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060E Bit Position 5:4 4 — — 1:0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 3:2 — 0 0 1 1 2 2 3 3 4 4 5 148 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic JC5OB JC6EB JC6OB JC7EB JC7OB JC8EB JC8OB JC9EB JC9OB JCAEB JCAOB JCBEB JCBOB JCCEB JCCOB JCDEB JCDOB JCEEB JCEOB JCFEB JCFOB JCOSR JCWSR JF0EB JF0OB JF1EB JF1OB JF2EB JF2OB JF3EB JF3OB JF4EB JF4OB JF5EB JF5OB JF6EB JF6OB JF7EB JF7OB JG0EB JG0OB JG1EB JG1OB JG2EB Description Interrupt pending CLKERR 5 Interrupt from CLKERR 6 Interrupt pending CLKERR 6 Interrupt from CLKERR 7 Interrupt pending CLKERR 7 Interrupt from CLKERR 8 Interrupt pending CLKERR 8 Interrupt from CLKERR 9 Interrupt pending CLKERR 9 Interrupt from CLKERR A Interrupt pending CLKERR A Interrupt from CLKERR B Interrupt pending CLKERR B Interrupt from CLKERR C Interrupt pending CLKERR C Interrupt from CLKERR D Interrupt pending CLKERR D Interrupt from CLKERR E Interrupt pending CLKERR E Interrupt from CLKERR F Interrupt pending CLKERR F Interrupt CLKERR output mode Interrupt CLKERR pulse width Interrupt from FGIO 0 Interrupt pending FGIO 0 Interrupt from FGIO 1 Interrupt pending FGIO 1 Interrupt from FGIO 2 Interrupt pending FGIO 2 Interrupt from FGIO 3 Interrupt pending FGIO 3 Interrupt from FGIO 4 Interrupt pending FGIO 4 Interrupt from FGIO 5 Interrupt pending FGIO 5 Interrupt from FGIO 6 Interrupt pending FGIO 6 Interrupt from FGIO 7 Interrupt pending FGIO 7 Interrupt from GPIO 0 Interrupt pending GPIO 0 Interrupt from GPIO 1 Interrupt pending GPIO 1 Interrupt from GPIO 2 Type Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Select Select Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Register 0x0060C 0x0060E 0x0060C 0x0060E 0x0060C 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x0060F 0x0060D 0x00613 0x00617 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00601 0x00600 0x00605 0x00604 0x00605 0x00604 0x00605 Bit Position 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 — — 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 149 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic JG2OB JG3EB JG3OB JG4EB JG4OB JG5EB JG5OB JG6EB JG6OB JG7EB JG7OB JISOR JS0EB JS0OB JS1EB JS1OB JS2EB JS2OB JS3EB JS3OB JS4EB JS4OB JS5EB JS5OB JS6EB JS6OB JS7EB JS7OB JS8EB JS8OB JS9EB JS9OB JSAEB JSAOB JSBEB JSBOB JSCEB JSCOB JSDEB JSDOB JSEEB JSEOB JSFEB Description Interrupt pending GPIO 2 Interrupt from GPIO 3 Interrupt pending GPIO 3 Interrupt from GPIO 4 Interrupt pending GPIO 4 Interrupt from GPIO 5 Interrupt pending GPIO 5 Interrupt from GPIO 6 Interrupt pending GPIO 6 Interrupt from GPIO 7 Interrupt pending GPIO 7 Interrupt in-service Interrupt from SYSERR 0 Interrupt pending SYSERR 0 Interrupt from SYSERR 1 Interrupt pending SYSERR 1 Interrupt from SYSERR 2 Interrupt pending SYSERR 2 Interrupt from SYSERR 3 Interrupt pending SYSERR 3 Interrupt from SYSERR 4 Interrupt pending SYSERR 4 Interrupt from SYSERR 5 Interrupt pending SYSERR 5 Interrupt from SYSERR 6 Interrupt pending SYSERR 6 Interrupt from SYSERR 7 Interrupt pending SYSERR 7 Interrupt from SYSERR 8 Interrupt pending SYSERR 8 Interrupt from SYSERR 9 Interrupt pending SYSERR 9 Interrupt from SYSERR A Interrupt pending SYSERR A Interrupt from SYSERR B Interrupt pending SYSERR B Interrupt from SYSERR C Interrupt pending SYSERR C Interrupt from SYSERR D Interrupt pending SYSERR D Interrupt from SYSERR E Interrupt pending SYSERR E Interrupt from SYSERR F Type Output Enable Output Enable Output Enable Output Enable Output Enable Output Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Register 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x00605 0x00604 0x006FC 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060A 0x00608 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B 0x00609 0x0060B Bit Position 2 3 3 4 4 5 5 6 6 7 7 — 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 150 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic JSFOB JSOSR JSWSR LARSN LBRSN LC0SR LC1SR LC2SR LC3SR LCKEB LCRSN LDBEB LDRSN LERSN LFRSN LGRSN LHRSN LRISR N1DSB N1DSN N1FEB N1ISN N1LOB N1LSR N1OEN N1SSB N1TOB N1WEB N1WSN N2DSB N2DSN N2FEB N2ISN N2LOB N2LSR N2OEN N2SSB N2TOB N2WEB N2WSN Description Interrupt pending SYSERR F Interrupt SYSERR output mode Interrupt SYSERR pulse width Local group A rate Local group B rate Local clock 0 output Local clock 1 output Local clock 2 output Local clock 3 output Local clocks Local group C rate Local data bus Local group D rate Local group E rate Local group F rate Local group G rate Local group H rate Local reference input NR1 divider inversion NETREF1 divider input NETREF1 fallback trigger NETREF1 main input NETREF1 latched error NETREF1 local reference NETREF1 output NR1 selector inversion NETREF1 transient error NETREF1 watchdog NETREF1 watchdog NR2 divider inversion NETREF1 divider input NETREF2 fallback trigger NETREF1 main input NETREF2 latched error NETREF1 local reference NETREF1 output NR2 selector inversion NETREF2 transient error NETREF2 watchdog NETREF2 watchdog Type Output Select Select Select Select Select Select Select Select Enable Select Enable Select Select Select Select Select Select Select Select Enable Select Output Select Enable Select Output Enable Select Select Select Enable Select Output Select Enable Select Output Enable Select Register 0x00609 0x00612 0x00616 0x00320 0x00320 0x00228 0x00229 0x0022A 0x0022B 0x00103 0x00321 0x00103 0x00321 0x00322 0x00322 0x00323 0x00323 0x00208 0x00204 0x00210 0x0010B 0x00210 0x00123 0x00212 0x00221 0x00204 0x00121 0x0010F 0x0010D 0x00204 0x00214 0x0010B 0x00214 0x00123 0x00216 0x00221 0x00204 0x00121 0x0010F 0x0010D Bit Position 7 — — L U — — — — 1 L 0 U L U L U — 1 U 3 L 3 — L 0 3 3 L 3 U 4 L 4 — U 2 4 4 U Agere Systems Inc. 151 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 114. Mnemonic Summary, Sorted by Name (continued) Mnemonic NR1DR NR2DR OLHLR OLLLR OOLER OOLOB P1ISR P1RSR P2RSR PAFSR S2FEB S2LOB S2TOB S2WEB SCFEB SCLOB SCLSB SCMLR SCMSB SCRSR SCTOB SCULP SCWEB SRBEB SRESR TCOSR VEROR XYSOB Description NETREF1 NETREF2 Out-of-lock threshold, high Out-of-lock threshold, low Out-of-lock monitor Out-of-lock status APLL1 input APLL1 rate APLL2 rate Phase align frame /SCLKx2 fallback trigger /SCLKx2 latched error /SCLKx2 transient error /SCLKx2 watchdog SCLK fallback trigger SCLK latched error Diag state counter mode EN Diag state counter mode low Diag state counter carry SCLK/SCLKx2 rate SCLK transient error Diag state counter mode high SCLK watchdog Soft reset of back end Soft reset T clock output Version ID register Active clock set Type Divide Divide Load Load Enable Output Select Select Select Enable Enable Output Output Enable Enable Output Select Load Select Select Output Load Enable Enable Select Select Output Output Register 0x00211 0x00215 0x00119 0x00118 0x0011A 0x00125 0x00202 0x00203 0x00207 0x00107 0x0010A 0x00122 0x00120 0x0010E 0x0010A 0x00122 0x00145 0x00144 0x00145 0X00227 0x00120 0x00145 0x0010E 0x00101 0x00100 0x00226 0x00128 0x00124 Bit Position — — — — — 6 — — — — 7 7 7 7 6 6 3 — 5 — 6 2:0 6 0 — — — 3 152 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register Mnemonic SRESR SRBEB HRBEB LDBEB LCKEB HDBEB HCKEB GPIEB FGREB AIOEB GSREB DMMSP CSASR FPASR PAFSR FBCSR FSMSN FTRSN CAFEB CBFEB CPFEB CMFEB C4FEB C2FEB SCFEB S2FEB FAFEB FBFEB FCFEB N1FEB N2FEB D1FEB D2FEB CAWSN CBWSN N1WSN N2WSN CAWEB CBWEB CPWEB Description Soft reset Soft reset of back end Hard reset of back end Local data bus Local clocks H1x0 data bus H1x0 clocks General-purpose I/O Frame group All I/O (master) Global subrate Data memory mode Clock set access Frame phase alignment Phase align frame Fallback control Fallback secondary mode Fallback type C8A fallback trigger C8B fallback trigger /C16+ fallback trigger /C16– fallback trigger /C4 fallback trigger C2 fallback trigger SCLK fallback trigger /SCLKx2 fallback trigger /FRAMEA fallback trigger /FRAMEB fallback trigger /FR_COMP fallback trigger NETREF1 fallback trigger NETREF2 fallback trigger DPLL1 sync trigger DPLL2 sync trigger C8A watchdog C8B watchdog NETREF1 watchdog NETREF2 watchdog C8A watchdog C8B watchdog /C16+ watchdog Type Select Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Enable Select Select Select Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Enable Enable Enable Register 0x00100 0x00101 0x00101 0x00103 0x00103 0x00103 0x00103 0x00103 0x00103 0x00103 0x00105 0x00105 0x00106 0x00107 0x00107 0x00108 0x00109 0x00109 0x0010A 0x0010A 0x0010A 0x0010A 0x0010A 0x0010A 0x0010A 0x0010A 0x0010B 0x0010B 0x0010B 0x0010B 0x0010B 0x0010B 0x0010B 0x0010C 0x0010C 0x0010D 0x0010D 0x0010E 0x0010E 0x0010E Bit Position — 0 1 0 1 2 3 4 5 7 7 6:0 — — — — L U 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 L U L U 0 1 2 Agere Systems Inc. 153 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic CMWEB C4WEB C2WEB SCWEB S2WEB FAWEB FBWEB FCWEB N1WEB N2WEB D1WEB D2WEB FSWEB FSCSR FSEER FSSSR OLLLR OLHLR OOLER CATOB CBTOB CPTOB CMTOB C4TOB C2TOB SCTOB S2TOB FATOB FBTOB FCTOB N1TOB N2TOB D1TOB D2TOB FSTOB CALOB CBLOB CPLOB CMLOB C4LOB C2LOB SCLOB S2LOB FALOB 154 Description /C16– watchdog /C4 watchdog C2 watchdog SCLK watchdog /SCLKx2 watchdog /FRAMEA watchdog /FRAMEB watchdog /FR_COMP watchdog NETREF1 watchdog NETREF2 watchdog DPLL1 sync watchdog DPLL2 sync watchdog Failsafe watchdog Failsafe return command Failsafe enable Failsafe sensitivity Out-of-lock threshold, low Out-of-lock threshold, high Out-of-lock monitor C8A transient error C8B transient error /C16+ transient error /C16– transient error C4 transient error C2 transient error SCLK transient error /SCLKx2 transient error /FRAMEA transient error /FRAMEB transient error /FR_COMP transient error NETREF1 transient error NETREF2 transient error DPLL1 sync transient error DPLL2 sync transient error Failsafe transient error C8A latched error C8B latched error /C16+ latched error /C16– latched error C4 latched error C2 latched error SCLK latched error /SCLKx2 latched error /FRAMEA latched error Type Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Enable Select Load Load Enable Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Register 0x0010E 0x0010E 0x0010E 0x0010E 0x0010E 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x0010F 0x00114 0x00115 0x00116 0x00118 0x00119 0x0011A 0x00120 0x00120 0x00120 0x00120 0x00120 0x00120 0x00120 0x00120 0x00121 0x00121 0x00121 0x00121 0x00121 0x00121 0x00121 0x00121 0x00122 0x00122 0x00122 0x00122 0x00122 0x00122 0x00122 0x00122 0x00123 Bit Position 3 4 5 6 7 0 1 2 3 4 5 6 7 — — — — — — 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic FBLOB FCLOB N1LOB N2LOB D1LOB D2LOB FSLOB FFPOB CFPOB GOPOB XYSOB FBFOB FBSOP CFBOB CFSOB VEROR IDLOR IDHOR FT0EB FT1EB FT2EB FT3EB FT4EB FT5EB FT6EB FT7EB FTPSR GT0EB GT1EB GT2EB GT3EB GT4EB GT5EB GT6EB GT7EB GTPSR SCMLR SCLSB FRMSB SCMSB SCULP FB1SB Description /FRAMEB latched error /FR_COMP latched error NETREF1 latched error NETREF2 latched error DPLL1 sync latched error DPLL2 sync latched error Failsafe latched error FORCE_FALLBACK pending CLEAR_FALLBACK pending Go clocks pending Active clock set Fallback enable status Fallback states Fallback status Failsafe status Version ID register Device ID low Device ID high FG0 testpoint FG1 testpoint FG2 testpoint FG3 testpoint FG4 testpoint FG5 testpoint FG6 testpoint FG7 testpoint FG testpoint MUX GP0 testpoint GP1 testpoint GP2 testpoint GP3 testpoint GP4 testpoint GP5 testpoint GP6 testpoint GP7 testpoint GP testpoint MUX Diagnostic, state counter mode low Diagnostic, state counter mode EN Diagnostic, /FR_COMP input Diagnostic, state counter carry Diagnostic, state counter mode high APLL1 feedback reset Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Select Enable Enable Enable Enable Enable Enable Enable Enable Select Load Select Select Select Load Select Register 0x00123 0x00123 0x00123 0x00123 0x00123 0x00123 0x00123 0x00124 0x00124 0x00124 0x00124 0x00124 0x00124 0x00127 0x00127 0x00128 0x0012A 0x0012B 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00140 0x00141 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00142 0x00143 0x00144 0x00145 0x00145 0x00145 0x00145 0x00146 Bit Position 1 2 3 4 5 6 7 0 1 2 3 7 6:4 6 7 — — — 0 1 2 3 4 5 6 7 — 0 1 2 3 4 5 6 7 — — 3 4 5 2:0 1 Agere Systems Inc. 155 Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic FB2SB IEXLP ISYLP ICKLP ICDSP IASLR CFLLR CFHLN CFSEN CKMSR CKMDR P1ISR P1RSR N1SSB N1DSB N2SSB N2DSB ICMSB CKRDR P2RSR LRISR D1ISR D1RSR IR0SB IR1SB IR2SB IR3SB IR4SB IR5SB IR6SB IR7SB D2ISR D2RSR N1ISN N1DSN NR1DR N1LSR N2ISN N2DSN NR2DR N2LSR CCOEN Description APLL2 feedback reset Diagnostic, interrupt control EXTERR Diagnostic, interrupt control SYSERR Diagnostic, interrupt control CLKERR Diagnostic, interrupt control mode Diagnostic, SYSERR assertion Diagnostic sync-to-frame low Diagnostic sync-to-frame high Diagnostic sync-to-frame EN Clock main Clock main APLL1 input APLL1 rate NR1 selector inversion NR1 divider inversion NR2 selector inversion NR2 divider inversion Invert clock main Clock resource APLL2 rate Local reference input DPLL1 input DPLL1 rate Invert local reference 0 Invert local reference 1 Invert local reference 2 Invert local reference 3 Invert local reference 4 Invert local reference 5 Invert local reference 6 Invert local reference 7 DPLL2 input DPLL2 rate NETREF1 main input NETREF1 divider input NETREF1 NETREF1 local reference NETREF1 main input NETREF1 divider input NETREF2 NETREF1 local reference C clocks output Type Select Load Load Load Select Load Load Load Enable Select Divide Select Select Select Select Select Select Select Divide Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Divide Select Select Select Divide Select Enable Register 0x00146 0x00148 0x00148 0x00148 0x00148 0x00149 0x0014A 0x0014B 0x0014B 0x00200 0x00201 0x00202 0x00203 0x00204 0x00204 0x00204 0x00204 0x00204 0x00205 0x00207 0x00208 0x0020A 0x0020B 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020C 0x0020E 0x0020F 0x00210 0x00210 0x00211 0x00212 0x00214 0x00214 0x00215 0x00216 0x00220 Bit Position 2 1:0 3:2 5:4 7:6 — — L U — — — — 0 1 2 3 4 — — — — — 0 1 2 3 4 5 6 7 — — L U — — L U — — L 156 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic ABOEN N1OEN N2OEN FRWSR ACRSN BCRSN CCSEN FRSEN TCOSR SCRSR LC0SR LC1SR LC2SR LC3SR HARSN HBRSN HCRSN HDRSN HERSN HFRSN HGRSN HHRSN LARSN LBRSN LCRSN LDRSN LERSN LFRSN LGRSN LHRSN F0LLR F0ULR F0ISB F0WSP F0RSR F1LLR F1ULR F1ISB F1WSP F1RSR F2LLR F2ULR F2ISB Description A and B clocks output NETREF1 output NETREF1 output /FR_COMP width A clocks rate B clocks rate C clocks separate /FR_COMP separate T clock output SCLK/SCLKx2 rate Local clock 0 output Local clock 1 output Local clock 2 output Local clock 3 output H1x0 group A rate H1x0 group B rate H1x0 group C rate H1x0 group D rate H1x0 group E rate H1x0 group F rate H1x0 group G rate H1x0 group H rate Local group A rate Local group B rate Local group C rate Local group D rate Local group E rate Local group F rate Local group G rate Local group H rate Frame 0 lower start time Frame 0 upper start time Frame 0 pulse inversion Frame 0 pulse width Frame 0 pulse width rate Frame 1 lower start time Frame 1 upper start time Frame 1 pulse inversion Frame 1 pulse width Frame 1 pulse width rate Frame 2 lower start time Frame 2 upper start time Frame 2 pulse inversion Type Enable Enable Enable Select Select Select Enable Enable Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Register 0x00220 0x00221 0x00221 0x00222 0x00223 0x00223 0x00224 0x00224 0x00226 0x00227 0x00228 0x00229 0x0022A 0x0022B 0x00300 0x00300 0x00301 0x00301 0x00302 0x00302 0x00303 0x00303 0x00320 0x00320 0x00321 0x00321 0x00322 0x00322 0x00323 0x00323 0x00400 0x00401 0x00402 0x00402 0x00403 0x00410 0x00411 0x00412 0x00412 0x00413 0x00420 0x00421 0x00422 Bit Position U L U — L U L U — — — — — — L U L U L U L U L U L U L U L U — — 7 6:0 — — — 7 6:0 — — — 7 157 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic F2WSP F2RSR F3LLR F3ULR F3ISB F3WSP F3RSR F4LLR F4ULR F4ISB F4WSP F4RSR F5LLR F5ULR F5ISB F5WSP F5RSR F6LLR F6ULR F6ISB F6WSP F6RSR F7LLR F7ULR F7ISB F7WSP F7RSR FCLLR FCULR F7MSR FCISB F7WSN F7SSP F0IOB F1IOB F2IOB F3IOB F4IOB F5IOB F6IOB F7IOB F0MEB F1MEB F2MEB 158 Description Frame 2 pulse width Frame 2 pulse width rate Frame 3 lower start time Frame 3 upper start time Frame 3 pulse inversion Frame 3 pulse width Frame 3 pulse width rate Frame 4 lower start time Frame 4 upper start time Frame 4 pulse inversion Frame 4 pulse width Frame 4 pulse width rate Frame 5 lower start time Frame 5 upper start time Frame 5 pulse inversion Frame 5 pulse width Frame 5 pulse width rate Frame 6 lower start time Frame 6 upper start time Frame 6 pulse inversion Frame 6 pulse width Frame 6 pulse width rate Frame 7 lower start time Frame 7 upper start time Frame 7 pulse inversion Frame 7 pulse width Frame 7 pulse width rate Frame group 7 lower count Frame group 7 upper count Frame 7 mode FG7 timer invert output FG7 timer pulse width FG7 timer pulse shape FGIO 0 data FGIO 1 data FGIO 2 data FGIO 3 data FGIO 4 data FGIO 5 data FGIO 6 data FGIO 7 data FGIO 0 read mask FGIO 1 read mask FGIO 2 read mask Type Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Enable Select Select Load Load Select Select Select Select Load Load Load Load Load Load Load Load Enable Enable Enable Register 0x00422 0x00423 0x00430 0x00431 0x00432 0x00432 0x00433 0x00440 0x00441 0x00442 0x00442 0x00443 0x00450 0x00451 0x00452 0x00452 0x00453 0x00460 0x00461 0x00462 0x00462 0x00463 0x00470 0x00471 0x00472 0x00472 0x00473 0x00474 0x00475 0x00476 0x00477 0x00477 0x00477 0x00480 0x00480 0x00480 0x00480 0x00480 0x00480 0x00480 0x00480 0x00481 0x00481 0x00481 Bit Position 6:0 — — — 7 6:0 — — — 7 6:0 — — — 7 6:0 — — — 7 6:0 — — — 7 6:0 — — — — 7 L — 0 1 2 3 4 5 6 7 0 1 2 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic F3MEB F4MEB F5MEB F6MEB F7MEB F0DSB F1DSB F2DSB F3DSB F4DSB F5DSB F6DSB F7DSB G0IOB G1IOB G2IOB G3IOB G4IOB G5IOB G6IOB G7IOB G0MEB G1MEB G2MEB G3MEB G4MEB G5MEB G6MEB G7MEB G0DSB G1DSB G2DSB G3DSB G4DSB G5DSB G6DSB G7DSB G0OEB G1OEB JF0OB JF1OB JF2OB JF3OB JF4OB Description FGIO 3 read mask FGIO 4 read mask FGIO 5 read mask FGIO 6 read mask FGIO 7 read mask FGIO 0 R/W direction FGIO 1 R/W direction FGIO 2 R/W direction FGIO 3 R/W direction FGIO 4 R/W direction FGIO 5 R/W direction FGIO 6 R/W direction FGIO 7 R/W direction GPIO 0 data GPIO 1 data GPIO 2 data GPIO 3 data GPIO 4 data GPIO 5 data GPIO 6 data GPIO 7 data PIO 0 read mask GPIO 1 read mask GPIO 2 read mask GPIO 3 read mask GPIO 4 read mask GPIO 5 read mask GPIO 6 read mask GPIO 7 read mask GPIO 0 R/W direction GPIO 1 R/W direction GPIO 2 R/W direction GPIO 3 R/W direction GPIO 4 R/W direction GPIO 5 R/W direction GPIO 6 R/W direction GPIO 7 R/W direction GPIO 0 override GPIO 1 override Interrupt pending FGIO 0 Interrupt pending FGIO 1 Interrupt pending FGIO 2 Interrupt pending FGIO 3 Interrupt pending FGIO 4 Type Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Load Load Load Load Load Load Load Load Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Enable Enable Output Output Output Output Output Register 0x00481 0x00481 0x00481 0x00481 0x00481 0x00482 0x00482 0x00482 0x00482 0x00482 0x00482 0x00482 0x00482 0x00500 0x00500 0x00500 0x00500 0x00500 0x00500 0x00500 0x00500 0x00501 0x00501 0x00501 0x00501 0x00501 0x00501 0x00501 0x00501 0x00502 0x00502 0x00502 0x00502 0x00502 0x00502 0x00502 0x00502 0x00503 0x00503 0x00600 0x00600 0x00600 0x00600 0x00600 Bit Position 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 0 1 2 3 4 159 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic JF5OB JF6OB JF7OB JF0EB JF1EB JF2EB JF3EB JF4EB JF5EB JF6EB JF7EB IF0SB IF1SB IF2SB IF3SB IF4SB IF5SB IF6SB IF7SB JG0OB JG1OB JG2OB JG3OB JG4OB JG5OB JG6OB JG7OB JG0EB JG1EB JG2EB JG3EB JG4EB JG5EB JG6EB JG7EB IG0SB IG1SB IG2SB IG3SB IG4SB IG5SB IG6SB IG7SB 160 160 Description Interrupt pending FGIO 5 Interrupt pending FGIO 6 Interrupt pending FGIO 7 Interrupt from FGIO 0 Interrupt from FGIO 1 Interrupt from FGIO 2 Interrupt from FGIO 3 Interrupt from FGIO 4 Interrupt from FGIO 5 Interrupt from FGIO 6 Interrupt from FGIO 7 Invert interrupt FGIO 0 Invert interrupt FGIO 1 Invert interrupt FGIO 2 Invert interrupt FGIO 3 Invert interrupt FGIO 4 Invert interrupt FGIO 5 Invert interrupt FGIO 6 Invert interrupt FGIO 7 Interrupt pending GPIO 0 Interrupt pending GPIO 1 Interrupt pending GPIO 2 Interrupt pending GPIO 3 Interrupt pending GPIO 4 Interrupt pending GPIO 5 Interrupt pending GPIO 6 Interrupt pending GPIO 7 Interrupt from GPIO 0 Interrupt from GPIO 1 Interrupt from GPIO 2 Interrupt from GPIO 3 Interrupt from GPIO 4 Interrupt from GPIO 5 Interrupt from GPIO 6 Interrupt from GPIO 7 Invert interrupt GPIO 0 Invert interrupt GPIO 1 Invert interrupt GPIO 2 Invert interrupt GPIO 3 Invert interrupt GPIO 4 Invert interrupt GPIO 5 Invert interrupt GPIO 6 Invert interrupt GPIO 7 Type Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Select Select Select Register 0x00600 0x00600 0x00600 0x00601 0x00601 0x00601 0x00601 0x00601 0x00601 0x00601 0x00601 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00603 0x00604 0x00604 0x00604 0x00604 0x00604 0x00604 0x00604 0x00604 0x00605 0x00605 0x00605 0x00605 0x00605 0x00605 0x00605 0x00605 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 0x00607 Bit Position 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic JS0OB JS1OB JS2OB JS3OB JS4OB JS5OB JS6OB JS7OB JS8OB JS9OB JSAOB JSBOB JSCOB JSDOB JSEOB JSFOB JS0EB JS1EB JS2EB JS3EB JS4EB JS5EB JS6EB JS7EB JS8EB JS9EB JSAEB JSBEB JSCEB JSDEB JSEEB JSFEB JC0OB JC1OB JC2OB JC3OB JC4OB JC5OB JC6OB JC7OB JC8OB JC9OB JCAOB Description Interrupt pending SYSERR 0 Interrupt pending SYSERR 1 Interrupt pending SYSERR 2 Interrupt pending SYSERR 3 Interrupt pending SYSERR 4 Interrupt pending SYSERR 5 Interrupt pending SYSERR 6 Interrupt pending SYSERR 7 Interrupt pending SYSERR 8 Interrupt pending SYSERR 9 Interrupt pending SYSERR A Interrupt pending SYSERR B Interrupt pending SYSERR C Interrupt pending SYSERR D Interrupt pending SYSERR E Interrupt pending SYSERR F Interrupt from SYSERR 0 Interrupt from SYSERR 1 Interrupt from SYSERR 2 Interrupt from SYSERR 3 Interrupt from SYSERR 4 Interrupt from SYSERR 5 Interrupt from SYSERR 6 Interrupt from SYSERR 7 Interrupt from SYSERR 8 Interrupt from SYSERR 9 Interrupt from SYSERR A Interrupt from SYSERR B Interrupt from SYSERR C Interrupt from SYSERR D Interrupt from SYSERR E Interrupt from SYSERR F Interrupt pending CLKERR 0 Interrupt pending CLKERR 1 Interrupt pending CLKERR 2 Interrupt pending CLKERR 3 Interrupt pending CLKERR 4 Interrupt pending CLKERR 5 Interrupt pending CLKERR 6 Interrupt pending CLKERR 7 Interrupt pending CLKERR 8 Interrupt pending CLKERR 9 Interrupt pending CLKERR A Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Output Output Output Output Output Output Output Output Output Output Output Register 0x00608 0x00608 0x00608 0x00608 0x00608 0x00608 0x00608 0x00608 0x00609 0x00609 0x00609 0x00609 0x00609 0x00609 0x00609 0x00609 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060A 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060B 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060C 0x0060D 0x0060D 0x0060D Bit Position 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 161 Agere Systems Inc. Ambassador T8110L H.100/H.110 Switch Data Sheet February 2004 Appendix B. Register Bit Field Mnemonic Summary (continued) Table 115. Mnemonic Summary, Sorted by Register (continued) Mnemonic JCBOB JCCOB JCDOB JCEOB JCFOB JC0EB JC1EB JC2EB JC3EB JC4EB JC5EB JC6EB JC7EB JC8EB JC9EB JCAEB JCBEB JCCEB JCDEB JCEEB JCFEB JAMSR JSOSR JCOSR JSWSR JCWSR JISOR Description Interrupt pending CLKERR B Interrupt pending CLKERR C Interrupt pending CLKERR D Interrupt pending CLKERR E Interrupt pending CLKERR F Interrupt from CLKERR 0 Interrupt from CLKERR 1 Interrupt from CLKERR 2 Interrupt from CLKERR 3 Interrupt from CLKERR 4 Interrupt from CLKERR 5 Interrupt from CLKERR 6 Interrupt from CLKERR 7 Interrupt from CLKERR 8 Interrupt from CLKERR 9 Interrupt from CLKERR A Interrupt from CLKERR B Interrupt from CLKERR C Interrupt from CLKERR D Interrupt from CLKERR E Interrupt from CLKERR F Interrupt arbitration mode Interrupt SYSERR output mode Interrupt CLKERR output mode Interrupt SYSERR pulse width Interrupt CLKERR pulse width Interrupt in-service Type Output Output Output Output Output Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Select Select Select Select Select Output Register 0x0060D 0x0060D 0x0060D 0x0060D 0x0060D 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E 0x0060E 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x0060F 0x00610 0x00612 0x00613 0x00616 0x00617 0x006FC Bit Position 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 — — — — — — 162 162 Agere Systems Inc. Data Sheet February 2004 Ambassador T8110L H.100/H.110 Switch Significant Changes Between the June 2003 and November 2003 Release Changes that were made to this document (since Revision 3) are listed below. Table 116. Changes Page page 11 page 17 page 126 page 133 page 141 Description Added PEN, TESTMODE Interface Signals to Table 6. Added PEN, TESTMODE pins to Table 8. Added Thermal Parameters definitions and values. Removed signals listed as no connects. Changed boundary of Constant Delay Rev Connections. Agere Systems Inc. 163 Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. AT&T is a registered trademark of AT&T Corporation. CompactPCI is a registered trademark of the PCI Industrial Computer Manufacturers Group. MVIP is a trademark of Natural MicroSystems Corporation. IEEE is a registered trademark of The Institute of Electrical and Electronic Engineers, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-91386 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-54614688 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, the Agere logo are trademarks and Ambassador is a registered trademark of Agere Systems Inc. Copyright © 2004 Agere Systems Inc. All Rights Reserved February 2004 DS04-024SWCH (Replaces DS03-132SWCH and AY03-020SWCH)