TAAD08JU2

Preliminary Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features s s System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station (BTS), base station controller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC) applications. IC provides an integrated octal framer that supports T1/E1/J1 formats. Supports inverse multiplexing for ATM (IMA) over selected group and link mappings ranging from four two-link groups up to one eight-link group per ATM Forum AF-PHY-0086.001. Integrates an ATM adaptation layer 2 (AAL2) segmentation and reassembly (SAR) function for support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier (CID) multiplexing per ITU I.366.1. Enables ATM layer user network interface (UNI) or IMA mode, selectable on a per-link basis for flexible transport of delay critical voice and data traffic. Guarantees QoS for a variety of traffic types (including delay-sensitive voice, real-time data, non-real-time data, and signaling information) through an advanced hierarchical three-level priority scheduler and per-VC queueing. Supports 2032 bidirectional AAL2 CIDs. Supports 2032 bidirectional high-speed data connections or virtual circuits (VCs) via embedded context memory; filters control cells and accepts control cells via a host microprocessor interface. On-board memory is used for connection management and queue data storage. No external memory is needed. s Software package includes the following: — Device manager source code (C-based device manager ready-to-use with host RTOS). — Setup file utility to provision TAAD08JU2. — Firmware for embedded controller (executable binary). — API reference manual available for device manager software. Designed in 0.16 µm, low-power CMOS technology. s s 2 Physical s s s 3.3 V digital I/O compatibility; 1.5 V core power 520 enhanced ball-grid array (EBGA) package –40 oC to +85 oC temperature range s s s 3 Standards ITU I.363.2, ITU I.363.5, ITU I.366.1, ITU I.366.2, ITU I.432, ITU I.361, ITU I.371, ITU G.703, ITU G.704, ITU G.804, ITU G.732, ITU G.706, ITU I.610, ITU G.775, ITU G.733, ITU G.735, ITU G.965, ITU O.162, ANSI® T1.403, ANSI T1.231, ATM Forum AF-PHY-0086.001 ATM Forum AF-PHY-0039.000 ATM Forum AF-TM-0121.000 ETS 300.417-1-1 s s s s s TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table of Contents Contents 1 2 3 4 5 6 7 8 9 Preliminary Data Sheet August 18, 2003 Page 10 11 12 13 Features ............................................................................................................................................................. 1 Physical .............................................................................................................................................................. 1 Standards ........................................................................................................................................................... 1 Description ....................................................................................................................................................... 11 Pin Definitions ..................................................................................................................................................12 Pin Description .................................................................................................................................................12 Package Pin Layout .........................................................................................................................................21 Block Diagram ..................................................................................................................................................27 Software Components ......................................................................................................................................28 9.1 Firmware.................................................................................................................................................29 9.2 Device Manager......................................................................................................................................29 9.3 Setup File Utility (SFU) ...........................................................................................................................30 9.4 TAAD08JU2 Application Code................................................................................................................31 9.5 System Software.....................................................................................................................................32 9.6 Software Development Environment ......................................................................................................32 9.7 Notes ......................................................................................................................................................33 Functional Overview.........................................................................................................................................34 10.1 Receive Direction Data Flow ..................................................................................................................34 10.1.1 PHY Layer ................................................................................................................................34 10.1.2 Low-Speed PHY Links ..............................................................................................................34 10.1.3 High-Speed PHY Links .............................................................................................................35 10.1.4 TC and IMA Layers...................................................................................................................35 10.1.5 ATM Layer ................................................................................................................................36 10.1.6 AAL Engine...............................................................................................................................36 10.1.7 Embedded Device Controller....................................................................................................37 10.2 Transmit Direction Data Flow..................................................................................................................37 10.2.1 SSCS/AAL Layer Interaction ....................................................................................................37 10.2.2 ATM Layer ................................................................................................................................37 10.2.3 IMA/TC Layer............................................................................................................................38 10.2.4 PHY Layer ................................................................................................................................38 Modes of Operation..........................................................................................................................................39 11.1 Interface Modes ......................................................................................................................................39 11.1.1 UTOPIA-2 Expansion Port Multiplexing Modes ........................................................................39 11.1.2 System Interface Port Multiplexing Modes ...............................................................................39 11.1.3 Line-Interface Modes ................................................................................................................40 11.2 Device Operating Modes ........................................................................................................................40 11.2.1 Operating Mode 1: Internal PHY Mode.....................................................................................40 11.2.2 Operating Mode 2: External PHY Mode ...................................................................................42 11.2.3 Operating Mode 3: SAR-Only Mode .........................................................................................43 11.2.4 Operating Mode Summary........................................................................................................43 Applications ......................................................................................................................................................44 12.1 BTS Network Interface Termination ........................................................................................................44 12.2 VToA Trunking Application......................................................................................................................46 12.3 Low-Speed ATM Access.........................................................................................................................47 12.4 AAL2 Cross Connect ..............................................................................................................................47 Embedded Device Controller (EDC) ................................................................................................................48 13.1 Introduction .............................................................................................................................................48 13.2 Features..................................................................................................................................................48 13.3 EDC Functional Description....................................................................................................................48 13.4 Host Interface .........................................................................................................................................48 13.5 Host Interface Signals and Timing ..........................................................................................................49 Agere Systems - Proprietary Agere Systems Inc. 2 Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table of Contents (continued) Contents Page 13.6 Host Interactions.....................................................................................................................................49 14 Framer Block ....................................................................................................................................................53 14.1 Introduction .............................................................................................................................................53 14.2 Features..................................................................................................................................................53 14.3 Framer-to-Line Interface Unit Physical Interface ....................................................................................54 14.3.1 Line Interface References/Standards .......................................................................................54 14.3.2 Clocking Modes ........................................................................................................................54 14.3.3 Frame Formats .........................................................................................................................55 14.3.4 Transmit Framer Functions.......................................................................................................55 14.4 DS1 Transparent Framing Format ..........................................................................................................55 14.5 CEPT 2.048 Basic Frame Structure Transparent Framing Format.........................................................56 14.6 Receive Framer Nonalignment Mode (DS1/E1) .....................................................................................57 14.6.1 Loss of Frame Alignment Criteria .............................................................................................57 14.6.1.1 Frame Bit Errors .........................................................................................................57 14.6.1.2 CRC Errors.................................................................................................................57 14.7 Frame Alignment Criteria........................................................................................................................57 14.8 Performance-Monitoring Functional Integration Into Framer ..................................................................58 14.9 Performance Report Message................................................................................................................61 14.10 ESF Data Link.........................................................................................................................................62 14.11 Facility Data Link ....................................................................................................................................62 14.11.1 Facility Data Link References/Standards ..................................................................................62 14.11.2 Receive Data Link Functional Description ................................................................................63 14.11.3 SLC-96 Superframe Receive Data Link....................................................................................63 14.11.4 DDS Receive Data Link Stack ..................................................................................................63 14.11.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack .....63 14.11.6 Receive Data Link Stack Idle Modes ........................................................................................64 14.11.7 Transmit Facility Data Link Functional Description ...................................................................64 14.11.8 SLC-96 Superframe Transmit Data Link...................................................................................64 14.11.9 DDS Transmit Data Link Stack .................................................................................................64 14.11.10 Transmit ESF Data Link Bit-Oriented Messages ......................................................................64 14.11.11 CEPT, CEPT Multiframe Transmit Data Link Sa Bits Stack ......................................................65 14.11.12 Transmit Data Link Stack Idle Modes .......................................................................................66 14.11.13 SLC-96, DDS, or CEPT ESF Frame Alignment ........................................................................66 14.12 Concentration Highway Interface (CHI) ..................................................................................................66 14.12.1 CHI References/Standards .......................................................................................................66 14.12.2 Transmit/Receive CHI Features................................................................................................66 14.12.3 Double NOTFAS System Time-Slot Mode................................................................................67 14.12.4 Transparent Mode.....................................................................................................................67 14.12.5 Loopbacks ................................................................................................................................67 14.12.6 Nominal CHI Timing..................................................................................................................68 14.12.7 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled ................................69 14.12.8 Clocking Scheme......................................................................................................................69 15 Transmission Convergence (TC) Block ............................................................................................................70 15.1 Introduction .............................................................................................................................................70 15.2 Features..................................................................................................................................................70 15.3 TC—Receive Direction ...........................................................................................................................71 15.4 TC—Transmit Direction ..........................................................................................................................71 15.4.1 HEC Generation/Checking .......................................................................................................72 15.5 Cell Delineation.......................................................................................................................................72 15.6 Cell Payload Scrambling/Descrambling..................................................................................................72 15.7 Cell Mapping...........................................................................................................................................72 15.8 Facility Maintenance ...............................................................................................................................72 Agere Systems Inc. Agere Systems - Proprietary Use pursuant to Company instructions 3 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 Table of Contents (continued) Contents Page 15.9 Cell Rate Decoupling ..............................................................................................................................73 15.10 Functionality............................................................................................................................................73 16 Inverse Multiplexing for ATM (IMA) Block.........................................................................................................74 16.1 Introduction .............................................................................................................................................74 16.2 Features..................................................................................................................................................75 16.3 Multi-PHY UTOPIA Slave Interface ........................................................................................................76 16.4 Link Processor ........................................................................................................................................76 16.5 Group Processor.....................................................................................................................................77 16.6 Delay Compensation Buffer (DCB).........................................................................................................78 16.7 Programming the DCB............................................................................................................................85 16.7.1 Link Start-Up Guardband Field .................................................................................................85 16.7.2 Link Maximum Operational Delay.............................................................................................85 16.8 Features Not Supported in IMA ..............................................................................................................85 17 ATM Port Controller (APC) Block .....................................................................................................................87 17.1 Introduction .............................................................................................................................................87 17.2 Architecture.............................................................................................................................................88 17.3 Features..................................................................................................................................................89 17.4 Summary of Commands .........................................................................................................................90 17.5 Buffer Management ................................................................................................................................90 17.6 Scheduling ..............................................................................................................................................92 17.6.1 Ingress Scheduling ...................................................................................................................92 17.6.2 Fabric Backpressure.................................................................................................................93 17.6.3 Egress Scheduling....................................................................................................................93 17.7 ABR Flow Control ...................................................................................................................................93 17.8 Control Plane Functions .........................................................................................................................94 17.8.1 APC Support for Control Plane Functions ................................................................................94 17.9 Management Plane Functions ................................................................................................................94 17.9.1 Operation Administration and Maintenance (OAM) ..................................................................94 17.10 Statistics Counters ..................................................................................................................................95 17.11 Ingress Enqueue Operations ..................................................................................................................95 17.11.1 Connection Look-Up .................................................................................................................96 17.11.2 OAM Processing.......................................................................................................................97 17.11.3 Policing .....................................................................................................................................98 17.11.4 Buffer Thresholding ..................................................................................................................98 17.11.5 Egress—APC VC Queueing Structure......................................................................................98 17.12 Connection Management........................................................................................................................99 17.12.1 Connection Admission Control .................................................................................................99 17.12.1.1 CBR............................................................................................................................99 17.12.1.2 rt-VBR ........................................................................................................................99 17.12.1.3 nrt-VBR ......................................................................................................................99 17.12.1.4 ABR............................................................................................................................99 17.12.1.5 UBR............................................................................................................................99 18 ATM Adaptation Layer (AAL) Block ................................................................................................................100 18.1 Introduction ...........................................................................................................................................100 18.2 Features................................................................................................................................................100 18.3 Definitions .............................................................................................................................................101 18.4 Architecture...........................................................................................................................................102 18.4.1 Datapath Flows .......................................................................................................................102 18.4.2 Subblock Architecture.............................................................................................................105 18.4.3 Subblock Definition .................................................................................................................106 18.4.4 Subblock Flows.......................................................................................................................107 18.4.5 Address Translation ................................................................................................................108 4 Agere Systems - Proprietary Use pursuant to Company instructions Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table of Contents (continued) Contents 18.4.6 18.4.7 18.4.8 18.4.9 18.4.10 18.4.11 18.4.12 18.4.13 18.4.14 18.4.15 18.4.16 18.4.17 18.4.18 Page Queueing and Scheduling ......................................................................................................109 Modes .....................................................................................................................................109 User Data Types (UDT) and AAL Types ................................................................................. 110 UDT: ATM Cell ........................................................................................................................ 111 AAL Type: AAL0 ..................................................................................................................... 111 AAL Type: AAL2 ..................................................................................................................... 111 AAL2 Subtype: SPAAL2 (Single-Packet AAL2) ...................................................................... 112 CPS-AAL0 .............................................................................................................................. 113 AAL Type: AAL5 ..................................................................................................................... 113 UDT: Packet ATM (PATM)....................................................................................................... 114 UDT: HPF................................................................................................................................ 115 AAL Type: NPAAL (No Particular AAL)................................................................................... 116 Nonuser Data Types: ESI Messages ...................................................................................... 116 18.4.18.1 ESI Message Format ............................................................................................... 116 18.4.18.2 ESI Violation Code ................................................................................................... 117 18.4.18.3 ESI Packet Length ................................................................................................... 117 18.4.19 Service Types ......................................................................................................................... 117 18.4.20 CPS_SERVICE....................................................................................................................... 118 18.4.21 SEG_AAL2_SSSAR_SERVICE ............................................................................................. 119 18.4.22 SEG_AAL2_SSTED_SERVICE.............................................................................................. 119 18.4.23 SEG_AAL5_SERVICE............................................................................................................ 119 18.4.24 TRANSPARENT_SERVICE....................................................................................................120 18.4.25 REASS_AAL2_SSSAR_SERVICE .........................................................................................120 18.4.26 REASS_AAL2_SSTED_SERVICE .........................................................................................120 18.4.27 REASS_AAL5_SERVICE .......................................................................................................120 18.5 Provisioning ..........................................................................................................................................122 18.5.1 Some Notes on Terminology and Command Referencing......................................................122 18.5.2 System Interface.....................................................................................................................122 18.5.3 Port Table................................................................................................................................123 18.5.4 MEMI Shared Memory............................................................................................................124 18.5.4.1 MEMI-SM Provisioning Constraints..........................................................................125 18.5.4.2 VC Table...................................................................................................................125 18.5.4.3 AAL2 VC Table .........................................................................................................126 18.5.4.4 Connection Table .....................................................................................................127 18.5.4.5 Level 0 Queue Descriptor ........................................................................................129 18.5.4.6 ICID Table ................................................................................................................129 18.5.5 SQASE Shared Memory .........................................................................................................129 18.6 Configuration ........................................................................................................................................130 18.6.1 Connection and Channel Setup..............................................................................................130 18.6.1.1 AAL2 Data Flow (CPS/SSSAR/SSTED) ..................................................................133 18.6.1.2 CPS-AAL0 Data Flow...............................................................................................133 18.6.1.3 AAL0/AAL5 Data Flow..............................................................................................133 18.6.1.4 HPF Data Flow .........................................................................................................133 18.6.2 Configuration for QoS .............................................................................................................134 18.6.2.1 Packet Scheduling ...................................................................................................134 18.6.2.2 IL1Q Scheduler Algorithm ........................................................................................134 18.6.2.3 IL2Q Scheduler Algorithm ........................................................................................134 18.6.2.4 Latency Policing .......................................................................................................136 18.6.2.5 Latency-Sensitive Data Discard ...............................................................................136 18.6.2.6 Internal Queue Housekeeping .................................................................................136 18.6.2.7 Reference Clock Generation ....................................................................................136 18.6.2.8 Latency Timer Enable/Disable Functions.................................................................137 Agere Systems Inc. Agere Systems - Proprietary Use pursuant to Company instructions 5 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 Table of Contents (continued) Contents Page 18.6.2.9 Queue Length Policing.............................................................................................137 18.6.2.10 Connection Queue Length Policing..........................................................................138 18.6.2.11 IL1Q and L1Q Length Policing .................................................................................139 18.6.2.12 IL2Q Length Policing................................................................................................140 18.6.3 Configuration for Exceptions...................................................................................................140 18.7 Interface Timing Diagrams....................................................................................................................143 18.7.1 SIF UT2/UT2+ Interface .........................................................................................................143 18.7.2 Polling Algorithms for UTOPIA 2 and UT2+ Modes................................................................152 18.7.2.1 Receive Interface Polling .........................................................................................152 18.7.2.2 Transmit Interface Polling.........................................................................................153 18.7.3 NIF ..........................................................................................................................................153 18.7.4 ESI ..........................................................................................................................................153 19 Absolute Maximum Ratings............................................................................................................................154 20 Power Requirements ......................................................................................................................................154 21 Handling Precautions .....................................................................................................................................155 22 Electrical Characteristics ................................................................................................................................155 22.1 Logical Interface Electrical Characteristics, Version 2.1 .......................................................................155 22.2 Logical Interface Electrical Characteristics, Version 3.1 .......................................................................156 23 Timing Characteristics ....................................................................................................................................157 23.1 Input Clocks, Versions 2.1 and 3.1 .......................................................................................................157 23.2 Host Interface Timing............................................................................................................................158 23.3 Reset Timing.........................................................................................................................................160 23.4 Concentration Highway (CHI) Timing, Versions 2.1 and 3.1 ................................................................161 23.5 Fabric Interface—Ports A and B, Versions 2.1 and 3.1 ........................................................................162 23.6 Expansion UTOPIA2 Interface..............................................................................................................164 23.6.1 Receive Interface Timing ........................................................................................................164 23.6.2 Transmit Interface Timing .......................................................................................................164 23.7 Enhanced Services Interface (ESI), Versions 2.1 and 3.1....................................................................164 23.8 JTAG.....................................................................................................................................................165 23.9 System Interface, Version 2.1...............................................................................................................165 23.9.1 Receive Interface Timing, Version 2.1 ....................................................................................165 23.9.2 Transmit Interface Timing, Version 2.1 ...................................................................................165 23.10 System Interface, Version 3.1...............................................................................................................166 23.10.1 Receive Interface Timing, Version 3.1 (SUCLK Is an Input.) ..................................................166 23.10.2 Transmit Interface Timing, Version 3.1 (SUCLK Is an Input.) .................................................166 24 Referenced Documents..................................................................................................................................167 25 Glossary .........................................................................................................................................................169 Appendix A. Revision History ................................................................................................................................172 6 Agere Systems - Proprietary Use pursuant to Company instructions Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 List of Figures Figure Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Page Pin Configuration Diagram ................................................................................................................21 Architecture of the TAAD08JU2 Device ............................................................................................27 Software Components .......................................................................................................................28 Device Manager APIs and TAAD08JU2 Communications ................................................................30 TAAD08JU2 Software Development Environment ............................................................................32 TAAD08JU2 Interfaces......................................................................................................................39 Mode 1: Internal PHY Mode Operation .............................................................................................40 Example of Sharing Span Line with TDM and ATM Data..................................................................41 Mode 2: External PHY Mode .............................................................................................................42 Mode 3: SAR-Only Mode...................................................................................................................43 BTS Application .................................................................................................................................44 BTSs Require ADM Functions...........................................................................................................45 Gateway Controller............................................................................................................................45 Remote Access Concentrator Application .........................................................................................46 Edge/Access Switch Application .......................................................................................................46 AAL2 Cross Connect .........................................................................................................................47 Stand-Alone AAL2 Cross Connect ....................................................................................................47 Standard Host Interface Timing.........................................................................................................49 DS1 Transparent Frame Structure ....................................................................................................56 CEPT Transparent Frame Structure..................................................................................................56 System Loopbacks ............................................................................................................................67 Nominal Concentration Highway Interface Timing ............................................................................68 CHIDTS Mode Concentration Highway Interface Timing ..................................................................69 IMA Application..................................................................................................................................74 IMA High-Level Interconnect Block Diagram.....................................................................................75 Logical View of Three-Link Group’s DCB Shortly After Starting to Receive Data from the Line .......78 Logical View of Three-Link Group’s DCB When It Starts Reading DCB ...........................................79 Logical View of Three-Link Group’s DCB After It Starts Reading DCB .............................................80 DCB During Normal Operation ..........................................................................................................81 Starting to Add a Link to a Group ......................................................................................................82 Link Now Being Read ........................................................................................................................83 Effects of Link #3 and Link #4 Faults.................................................................................................84 APC Block Integrated Memory Configuration....................................................................................87 Switch Fabric Connections for Dual TAAD08JU2 Switch Mode........................................................88 AAL Engine Block Diagram .............................................................................................................100 SIF-to-NIF, NIF-to-SIF .....................................................................................................................102 SIF Loopback, NIF Loopback ..........................................................................................................103 NIF Adaptation Loopback ................................................................................................................103 Host-to-SIF, SIF-to-Host..................................................................................................................104 Host-to-NIF, NIF-to-Host .................................................................................................................104 SAR Subblock Diagram...................................................................................................................105 Logical View of the Enqueue (Left) and Dequeue (Right) Address Translation Procedure.............108 Simplified Diagram of SQASE Queueing Structure.........................................................................109 User Data Types and AAL Types at the Interfaces .........................................................................110 User Data Type (UDT) vs. AAL Type Mapping ...............................................................................111 SPAAL2 Data Format ......................................................................................................................112 CPS-AAL0 Data Format ..................................................................................................................113 PATM Format ..................................................................................................................................114 HPF Format .....................................................................................................................................115 Transferring an HPF Packet over the Host Interface Example........................................................118 Port Table ........................................................................................................................................123 VC Table..........................................................................................................................................125 Agere Systems - Proprietary Use pursuant to Company instructions 7 Agere Systems Inc. TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 List of Figures (continued) Figures Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Page AAL2 VC Table................................................................................................................................126 Connection Table ............................................................................................................................127 SQASE Queueing Structure ............................................................................................................131 Connection Queue Length Policing .................................................................................................138 IL1Q/L1Q Length Policing ...............................................................................................................139 IL2Q Length Policing .......................................................................................................................140 UT2/UT2+ Header at the SIF Interface ...........................................................................................143 Cell Transmission on the SIF Interface ...........................................................................................144 Packet Transmission on the SIF Interface with No Stalls................................................................145 Packet Transmission on the SIF Interface with the PHY Stalling ....................................................146 Packet Transmission on the SIF Interface with the Master Stalling ................................................147 Reception of a Cell on the SIF Interface..........................................................................................148 Reception of a Packet on the SIF Interface with No Stalls ..............................................................149 Reception of a Packet on the SIF Interface with the PHY Stalling ..................................................150 Reception of a Packet on the SIF Interface with the Master Stalling...............................................151 ESI Functional Timing Diagram.......................................................................................................153 Data Read from TAAD08JU21 ........................................................................................................158 Data Written to TAAD08JU2............................................................................................................159 Power-On Reset ..............................................................................................................................160 Stable Reset ....................................................................................................................................160 CHI Transmit I/O Timing..................................................................................................................161 CHI Receive I/O Timing...................................................................................................................162 8 Agere Systems - Proprietary Use pursuant to Company instructions Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 List of Tables Table Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Page Pin Definitions................................................................................................................................... 12 Transmission Line Interface Signals (48 Signals) ............................................................................ 13 CHI Interface Signals (20 Signals) ................................................................................................... 14 UTOPIA 2 Expansion Interface Signals (52 Signals) ....................................................................... 14 System Interface Signals (62 Signals).............................................................................................. 15 Switch Fabric Interface Signals (50 Pins)......................................................................................... 17 APC External Statistics Interface Signals (18 Signals) .................................................................... 18 SAR External Statistics Interface Signals (18 Signals)..................................................................... 18 Host Interface Signals (49 Signals) .................................................................................................. 19 JTAG Interface Pins (6 Signals) ...................................................................................................... 19 Global/Miscellaneous Signal Pins (10 Signals) ................................................................................ 19 Power Supply Pins (4 Analog Power Pins, 120 Digital Power Pins) ............................................... 20 Signal-to-Ball Mapping ..................................................................................................................... 22 Host Registers .................................................................................................................................. 50 Frame Alignment Criteria.................................................................................................................. 58 Performance Monitor Functional Descriptions.................................................................................. 59 Performance Report Message Format ............................................................................................. 61 Performance Report Message Field Definition................................................................................. 62 Shared Tx Stack Format for CEPT Frame ....................................................................................... 65 Cell Headers of Idle, Unassigned, and Invalid Cells......................................................................... 73 TC Functionality................................................................................................................................ 73 TAAD08JU2 Exceptions to the IMA PICS Proforma ........................................................................ 85 PATM Fields ................................................................................................................................... 114 HPF Fields...................................................................................................................................... 115 ESI Message Format (AALXDATA[15:0])....................................................................................... 116 ESI Violation Codings..................................................................................................................... 117 AAL Type vs. Service Type Compatibility....................................................................................... 118 Transport of Congestion Indication and Loss Priority..................................................................... 121 PortIndex to Enqueue Block Port Mapping..................................................................................... 123 MEMI-SM Resources ..................................................................................................................... 124 SQASE-SM Resources .................................................................................................................. 130 L1Q and IL2Q Scheduling .............................................................................................................. 135 Example Stage-Two Divider Settings ............................................................................................. 137 Exceptions ...................................................................................................................................... 141 Absolute Maximum Ratings............................................................................................................ 154 Power Requirements ...................................................................................................................... 154 Operating Conditions...................................................................................................................... 154 Handling Precautions ..................................................................................................................... 155 Version 2.1 Logic Interface Characteristics .................................................................................... 155 Version 3.1 Logic Interface Characteristics .................................................................................... 156 Versions 2.1 and 3.1 Main System Clock (GCLK) Timing Specifications....................................... 157 Version 2.1 UTOPIA Input Clocks (UCLK) Timing Specifications .................................................. 157 Version 3.1 UTOPIA Input Clocks (UCLK_A[B]) Timing Specifications ......................................... 157 Host Read Timing Characteristics .................................................................................................. 158 Host Write Timing Characteristics .................................................................................................. 159 Version 2.1 CHI Transmit Timing Characteristics........................................................................... 161 Version 3.1 CHI Transmit Timing Characteristics........................................................................... 161 CHI Receive Timing Characteristics............................................................................................... 162 Version 2.1 Fabric Interface Timing Specifications (Transmit Interface) ........................................ 162 Version 3.1 Fabric Interface Timing Specifications (Transmit Interface) ........................................ 163 Version 2.1 Fabric Interface Timing Specifications (Receive Interface) ......................................... 163 Version 3.1 Fabric Interface Timing Specifications (Receive Interface) ......................................... 163 Agere Systems - Proprietary Use pursuant to Company instructions 9 Agere Systems Inc. TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 List of Tables (continued) Table Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table A-1. Page Expansion UTOPIA2 Receive Interface Timing Specifications: 50 MHz ........................................ UTOPIA2 Transmit Interface Timing Specifications: 50 MHz......................................................... Version 2.1 ESI Interface Timing Specifications............................................................................. Version 3.1 ESI Interface Timing Specifications (SAR and APC) .................................................. JTAG Timing Specifications ........................................................................................................... Version 2.1 Receive Interface Timing............................................................................................. Version 2.1 Transmit Interface Timing............................................................................................ Version 3.1 Receive Interface Timing (SUCLK Input) .................................................................... Version 3.1 Transmit Interface Timing (SUCLK Input) ................................................................... Revision History.............................................................................................................................. 164 164 164 164 165 165 165 166 166 172 10 Agere Systems - Proprietary Use pursuant to Company instructions Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 4 Description TAAD08JU2 provides a flexible network-interface solution for next-generation applications in which efficient transport of narrowband voice and broadband data information is critical to guaranteeing network QoS for the user and transmission efficiency for the network operator. Constructed using Agere’s 0.16 µm CMOS technology, the chip has an integrated octal framer, IMA processor, cell scheduler and router, and AAL2/5 SAR functions. TAAD08JU2 operates in either UNI or IMA mode (selectable on a per-span line basis). The complete AF-PHY0086.001 management information base (MIB) is supported. Flexible provisioning of link and group combinations enables a mix of IMA and UNI mappings to various AAL services. Support for AAL2 is provided via an AAL/CPS function that maps/demaps variable-sized CPS packets to/from ATM-SDU. A total of 2032 bidirectional CIDs are supported. These CIDs can be transported within a programmable number of VCs per direction. TAAD08JU2 supports up to 124 AAL2 VCs, which may be allocated between ingress and egress traffic. Support for high-speed data switching is provided whereby AAL5 VCs are routed through to the system interface toward their destinations. TAAD08JU2 provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory. TAAD08JU2 provides the following: ! ! ! ! Integrated policing F4/F5 operations, administration, and maintenance (OAM) Cell processing Statistics collection for performance monitoring Communication with TAAD08JU2 is accomplished through a 32-bit microprocessor interface. The system interface is through two choices: a UTOPIA 2 interface with support for both 8-bit and 16-bit data bus width and a UTOPIAderived packet interface with support for both 8-bit and 16-bit data bus widths. TAAD08JU2 provides a complete ATM access function from AAL/CPS mapping functions (for AAL2 and 5) through ATM/TC/PHY layers. The highly integrated, flexible architecture results in unified OAM features, simpler operation, and best-in-class operation with respect to area, power, and function. Agere Systems Inc. Agere Systems - Proprietary 11 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 5 Pin Definitions Table 1. Pin Definitions Type I Iu Id O O-6 I/O P Description Input only. All 3.3 V inputs are designed to be TTL compatible. Input with high-value pull-up resistor internal to TAAD08JU2. Input with high-value pull-down resistor internal to TAAD08JU2. Output only. These outputs have IOL/IOH = 10 mA. Output only. These outputs have IOL/IOH = 6 mA. Bidirectional input and output. Power or ground. 6 Pin Description Many of the pins of the TAAD08JU2 device are multiplexed for different functions. In these cases, both functions are shown in the same row of Table 2. 12 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 6 Pin Description (continued) Table 2. Transmission Line Interface Signals (48 Signals) Signal LRXCLK(0:7) LRXPDATA(0:7)/ LRXDATA(0:7) Type Id Id Description Line Interface Receive Clocks. Receive path clock from the LIU. Line Interface Receive Positive Rail Data/Line Interface Receive Data. When the TAAD08JU2 device is configured to operate in a dual-rail line interface mode, this pin is the positive receive data from the external LIU. When the TAAD08JU2 device is configured to operate in a single-rail line interface mode, this pin is the receive data from the external LIU. Line Interface Receive Negative Rail Data/Line Interface Receive Bipolar Violations. When the TAAD08JU2 device is configured to operate in a dual-rail line interface mode, this pin is the negative receive data from the external LIU. When the TAAD08JU2 device is configured to operate in a single-rail line interface mode, this pin is the receive bipolar violations signal from the external LIU. Line Interface Transmit Clock. These pins can be individually programmed as either a clock input or output in one of three modes: 1. Global clock mode. All the LTXCLK signals are outputs derived from a global clock input signal (see CHI interface CRXCLK in Table 3). 2. All of the LTXCLK signals are outputs of the corresponding LRXCLK signals looped back internally. 3. Independent transmit clock mode. Each LTXCLK pin is an input from the line interface. The clock rates, when used as either inputs or outputs, are 1.544 MHz or 2.048 MHz. When the CHI interface is active, these pins must be configured in the global clock mode. Line Interface Transmit Positive Rail Data/Line Interface Transmit Data. When the TAAD08JU2 device operates in a dual-rail line interface mode, this pin is the positive transmit data sent to the external LIU. When the TAAD08JU2 device operates in a single-rail line interface mode, this pin is the transmit data sent to the external LIU. Line Interface Transmit Negative Rail Data. When the TAAD08JU2 device operates in a dual-rail line interface mode, this pin is the negative transmit data sent to external LIU. When the TAAD08JU2 device operates in a single-rail line interface mode, this pin outputs an 8 kHz frame sync pulse. LRXNDATA(0:7)/ LRXBPV(0:7) Id LTXCLK(0:7) Id/O LTXPDATA(0:7)/ LTXDATA(0:7) O LTXNDATA(0:7) O Agere Systems Inc. Agere Systems - Proprietary 13 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 6 Pin Description (continued) Table 3. CHI Interface Signals (20 Signals) Signal CRXCLK Type I Description CHI Receive Clock. This signal is used to perform two basic functions: 1) this pin is used to clock the CHI receive interface; 2) depending on transmit line clock mode, the clock on this pin can be used to drive the Tx line clock (of which there are several suboptions). These suboptions are as follows: ! When the receive CHI interface is used, then 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz can be supplied. Internally, TAAD08JU2 will derive 1.544 MHz and 2.048 MHz to support T1, E1, or a mix of T1 and E1 lines. If the CHI is not used, this pin can be used to drive the line clocks in two submodes, as follows: — This pin would directly drive the Tx interface. In this mode, 1.544 MHz (T1) or 2.048 MHz (E1) is applied to CRXCLK, and all eights links run at this line rate. — A 2.048 MHz reference is applied to CRXCLK and TAAD08JU2 internally derives 1.544 MHz and 2.048 MHz to support either T1, E1, or a mix of T1/E1 transmit lines. This mode is essentially a subset of option 1 above, except the CHI is not used. This pin is not used when the TAAD08JU2 is programmed into independent transmit clock mode or receive loop timing mode. ! ! ! CRXDATA(0:7) CRXFS CTXCLK CTXDATA(0:7) CTXFS I I I O I The CRXCLK pin does not require a clock to be connected if that pin is not being used for any framer or CHI clocking modes. However, if a clock is required, this can be easily accommodated by connecting GCLK to this pin. CHI Receive Data. These are the received CHI data inputs at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. CHI Receive Frame Sync. Global 8 kHz frame sync for the receive CHI ports. CHI Transmit Clock. Global system clock for transmit defined as a 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz global input clock. CHI Transmit Data. These are the transmitted CHI data outputs clocked by the CTXCLK at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. CHI Transmit Frame Sync. Input global 8 kHz frame sync for the transmit system. Table 4. UTOPIA 2 Expansion Interface Signals (52 Signals) Signal UMODE Type I Description UTOPIA Expansion Interface Mode. This pin sets the mode of operation for this interface. The modes are described below: 0: Master Mode: This signal is set low when TAAD08JU2 is programmed to operate in either internal or external PHY mode. In this case, the internal APC block controls the expansion interface pins as a UTOPIA master. 1: Slave Mode: This is set high when the TAAD08JU2 is programmed into SAR-only mode. In this mode, this interface connects to the SAR block as a UTOPIA slave. UTOPIA Expansion Clock. This is the UTOPIA clock input for both the transmit and receive UTOPIA. The clock frequency applied to this pin should be less than or equal to GCLK. A clock must be supplied on this pin at all times. Even if this interface is not otherwise used, a clock must still be provided. Typically, this can be easily accommodated by connecting GCLK to this pin. Agere Systems - Proprietary Agere Systems Inc. UCLK I 14 Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 6 Pin Description (continued) Table 4. UTOPIA 2 Expansion Interface Signals (52 Signals) (continued) Signal URXDATA[15:0] Type Description d UTOPIA Expansion Receive Data. In master mode, these signals are the parMaster: I Slave: O allel 16-bit data input bus from an external PHY device. In slave mode, these signals are a data output bus to an external PHY device. These signals are clocked in/out on the rising edge of UCLK. Bit URXDATA[15] is the MSB. Master: Id UTOPIA Expansion Receive Data Parity. This signal either receives (master Slave: O mode) or sends (slave mode) the receive data parity signal. When a master, TAAD08JU2’s APC block can be configured to check for odd parity or can be disabled. When a slave, this can be configured to odd, even, or no parity. d UTOPIA Expansion Receive Start of Cell. Active-high signal asserted when Master: I Slave: O URXDATA contains the first word of a cell. Master: O UTOPIA Expansion Receive Enable. Active-low signal asserted by the ATM Slave: Iu layer to signal that a transfer will occur at the next rising edge of UCLK. Master: O UTOPIA Expansion Receive Address. 5-bit address used by the UTOPIA Slave: Id master to select the UTOPIA slave for the receive signal path. Bit 4 is the MSB. Master: I UTOPIA Expansion Receive Cell Available. Active-high signal asserted when Slave: O a complete cell is available in the FIFO of the device selected by URXADDR. Master: O UTOPIA Expansion Transmit Data. In master mode, these signals are a paralSlave: Id lel 16-bit data output bus to an external PHY device. In slave mode, these signals are a parallel 16-bit data input bus from an external PHY device. Data is clocked out/in on the rising edge of UCLK. Bit UTXDATA[15] is the MSB. Master: O UTOPIA Expansion Transmit Data Parity. This signal either sends (master Slave: Id mode) or receives (slave mode) the transmit data parity signal. In slave mode, this can be configured to odd, even, or no parity on UTXDATA bus. In master mode, transmit parity can be either odd or disabled. The default is odd. Master: O UTOPIA Expansion Transmit Start of Cell. Active-high signal asserted when Slave: Id UTXDATA contains the first word of a cell. Master: O UTOPIA Expansion Transmit Enable. Active-low signal asserted by the ATM Slave: Iu layer to signal that UTXDATA and UTXSOC contain valid data. Master: O UTOPIA Expansion Transmit Address. 5-bit address used by the master to Slave: Id select the UTOPIA slave for the transmit signal path. Bit 4 is the MSB. Master: Id UTOPIA Expansion Transmit Cell Available. Active-high signal asserted Slave: O when the polled slave is ready to receive complete cell can be stored in the FIFO of the device selected by UTXADDR. URXPRTY URXSOC URXENB URXADDR[4:0] URXCLAV UTXDATA[15:0] UTXPRTY UTXSOC UTXENB UTXADDR[4:0] UTXCLAV Table 5. System Interface Signals (62 Signals) Signal SMODE[2:0] Type Id Description System Interface Mode. The two LSBs (SMODE[1:0]) determine the operating mode of the interface, while SMODE[2] determines the clock mode in UTOPIA cell and packet modes. SMODE[1:0] Description 00: UTOPIA mode 01: Packet (UT2+) mode 10: Unused 11: Unused SMODE[2] sets the clock mode for the system interface. A low on this pin causes TAAD08JU2 to input SUCLK, and a high sets TAAD08JU2 to generate SUCLK. Agere Systems Inc. Agere Systems - Proprietary 15 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 6 Pin Description (continued) Table 5. System Interface Signals (62 Signals) (continued) Signal SUCLK STXDATA[15:0] STXADDR[4:0] STXSOC/STXSOP Type Id/O O O O Description System Interface Clock. Pin programmable to be an input or output. The clock frequency applied to this pin should be less than or equal to GCLK. System Interface Transmit Data. Parallel data bus to the ATM layer clocked out on the rising edge of SUCLK. Bit 15 is the MSB. System Transmit Address. 5-bit address used to select the external UTOPIA slave for the transmit signal path. System Transmit Start of Cell/Packet. In cell or packet mode, when STXSOC is high, the first word of the packet is present on the STXDATA bus. STXSOC is considered valid only when STXENB is asserted and is updated on the rising edge of SUCLK. System Transmit Data Parity. This signal sends the parity bits for the STXDATA bus. System Transmit Enable. Active-low signal asserted by the ATM layer to signal that STXDATA contains valid data. System UT2+ Transmit End of Packet. This signal is high when the last word of a packet is on the STXDATA bus. STXEOP is valid only when STXENB is asserted and is updated on the rising edge of SUCLK (UT2+ mode only). System UT2+ Transmit Size. This signal indicates the size of the current word on STXDATA. STXSIZ is valid only when STXEOP is asserted. If the last word contains two valid bytes, STXSIZ is high while that word is on the STXDATA bus (16-bit UT2+ mode only). System UT2+ Transmit Error. SRXERR is an active-high signal that indicates when the current packet is to be aborted and discarded, if possible. STXERR is valid only when STXEOP and STXENB are asserted and is sampled on the rising edge of SUCLK (UT2+ mode only). System Transmit Cell/Packet Available. Active-high signal asserted when a complete cell/packet can be stored in the FIFO of the external device selected by STXADDR. System UT2+ Transmit Selected Multi-PHY Packet Available. While STXCLAV shows the polled status of the external UTOPIA slave, this signal indicates the status of the current selected external slave. When asserted, this signal indicates that the current selected slave has more space than the predefined space in its FIFO (UT2+ mode only). System Receive Data. This signal is the parallel 16-bit data bus to the ATM layer clocked out on the rising edge of SUCLK. Bit SRXDATA[15] is the MSB. System Receive Address. 5-bit address used to select the external UTOPIA slave for the receive signal path. SRXADDR[4] is the MSB. System Receive Start of Cell/Packet. Active-high signal asserted when SRXDATA contains the first word of a cell or packet. System Receive Data Parity. Programmable for odd, even, or no parity over SRXDATA. System Receive Enable. Active-low signal asserted by the ATM layer to signal that a transfer will occur at the next rising edge of SUCLK. System UT2+ Receive End of Packet. This signal is active-high, and it indicates that the last word of a packet is on the SRXDATA bus. SRXEOP is valid when SRXENB is asserted and is sampled on the rising edge of SUCLK. (UT2+ mode only.) Agere Systems - Proprietary Agere Systems Inc. STXPRTY STXENB STXEOP O O O STXSIZ O STXERR Id STXCLAV/STXPA Id STXSPA Id SRXDATA[15:0] SRXADDR[4:0] SRXSOC/SRXSOP SRXPRTY SRXENB SRXEOP Id O Id Id O Id 16 Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 6 Pin Description (continued) Table 5. System Interface Signals (62 Signals) (continued) Signal SRXSIZ Type Id Description System UT2+ Receive Size. This signal indicates the size of the current word on SRXDATA. SRXSIZ is valid when SRXEOP is asserted. A logic one indicates that SRXDATA[15:0] are valid, and a logic zero indicates that SRXDATA[15:8] are valid. (UT2+ mode only.) System UT2+ Receive Error. This is an active-high signal that indicates that the current packet is to be aborted and discarded, if possible. SRXERR is only valid when SRXEOP and SRXENB are asserted and is sampled on the rising edge of SUCLK. (UT2+ mode only.) System Receive Cell/Packet Available. In cell mode, when asserted, this signal indicates that a subsequent cell is available after the current transfer. In packet mode, when asserted, it indicates that more data than the predefined amount is available. System UT2+ Receive Data Valid. This is an active-high signal asserted by a slave device when in UT2+ mode to indicate that data is valid on the current clock cycle. This signal allows for the slave device to control data flow by deasserting this signal, thus pausing the current packet transmission. When the slave has valid data to put on the data bus, it will resume transmission of the current packet by asserting SRXVAL. For every clock cycle that there is valid data on the data bus, SRXVAL must be asserted. SRXVAL is a shared 3-state signal between all active MPHYs and only the currently selected MPHY may drive this signal. SRXERR Id SRXCLAV/SRXPA Id SRXVAL Id Table 6. Switch Fabric Interface Signals (50 Pins) Signal Type Switch Fabric A Port AATXDATA[7:0] O-6 AATXPRTY AATXSOC AATXCLKP O-6 O-6 O-6 Description APC Port A Transmit Data. Parallel data bus used to transfer cells from TAAD08JU2 to the switch fabric. APC Port A Transmit Parity. Odd parity calculated over AATXDATA. Odd parity means an odd number of ones including the parity bit. APC Port A Transmit Start of Cell. Active-high signal asserted when AATXDATA contains the first word of a cell. APC Port A Transmit Differential Clock Positive. This clock is the reference that is sent with the AATXDATA and is used by the receiving APC or switch fabric to clock in the data. This clock is derived from GCLK and is twice the GCLK frequency. APC Port A Transmit Differential Clock Negative. This clock is the reference that is sent with the AATXDATA and is used by the receiving APC or switch fabric to clock in the data. This clock is derived from GCLK and is twice the GCLK frequency. APC Port A Receive Data. Parallel data bus used to transfer cells from the switch fabric to TAAD08JU2. APC Port A Receive Parity. Odd parity calculated over AARXDATA. Odd parity means an odd number of ones including the parity bit. APC Port A Receive Start of Cell. Active-high signal asserted when AARXDATA contains the first word of a cell. APC Port A Receive Differential Clock Positive. This clock is used by TAAD08JU2 to clock AARXDATA into the device. This clock is typically twice GCLK. Agere Systems - Proprietary 17 AATXCLKN O-6 AARXDATA[7:0] AARXPRTY AARXSOC AARXCLKP Id Id Id Id Agere Systems Inc. TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 6 Pin Description (continued) Table 6. Switch Fabric Interface Signals (50 Pins) (continued) Signal AARXCLKN Type Id Description APC Port A Receive Differential Clock Negative. This clock is used by TAAD08JU2 to clock AARXDATA into the device. This clock is typically twice GCLK. Switch Fabric B Port ABTXDATA[7:0] APC Port B Transmit Data. Parallel data bus used to transfer cells from TAAD08JU2 to the switch fabric. ABTXPRTY O-6 APC Port B Transmit Parity. Odd parity calculated over ABTXDATA. Odd parity means an odd number of ones including the parity bit. ABTXSOC O-6 APC Port B Transmit Start of Cell. Active-high signal asserted when ABTXDATA contains the first word of a cell. ABTXCLKP O-6 APC Port B Transmit Differential Clock Positive. The frequency is derived from GCLK. Maximum frequency is 100 MHz. ABTXCLKN O-6 APC Port B Transmit Differential Clock Negative. The frequency is derived from GCLK. Maximum frequency is 100 MHz. d ABRXDATA[7:0] I APC Port B Receive, bits 7:0. Parallel data bus used to transfer cells from the switch fabric to TAAD08JU2. ABRXPRTY Id APC Port B Receive Parity. Odd parity calculated over ABRXDATA. Odd parity means an odd number of ones, including the parity bit. d ABRXSOC I APC Port B Receive Start of Cell. Active-high signal asserted when ABRXDATA contains the first word of a cell. ABRXCLKP Id APC Port B Receive Clock Positive. This clock is used by TAAD08JU2 to clock the ABRXDATA into the device. This clock is typically twice GCLK. d ABRXCLKN I APC Port B Receive Clock Negative. This clock is used by TAAD08JU2 to clock the ABRXDATA into the device. This clock is typically twice GCLK. Switch Fabric Miscellaneous Signals AGTSYNC O Global Time-Slot (Cell Time) Synchronization Pulse. Asserted high once every 68 cycles of internal APC clock (which is 2 x GCLK). AHPSWF Id Agere Test Mode Pin. Should be tied to ground. Table 7. APC External Statistics Interface Signals (18 Signals) Signal AEDATA[15:0] AECLK AESYNC Type O O O Description APC External Statistics Data. A 16-bit data bus used to transfer data between the APC and an optional external adjunct device. APC External Statistics Clock. Used as a reference to transfer data between the APC and an external adjunct. APC External Statistics Sync. A single-cycle pulse signaling the beginning of the 34 clock cycle (AECLK) external statistics interface time slot. The absence of this synchronization pulse indicates that cell processing is disabled. O-6 Table 8. SAR External Statistics Interface Signals (18 Signals) Signal REDATA[15:0] RECLK Type O O Description SAR External Statistics Data. A 16-bit data bus used to transfer data between the SAR and an optional external adjunct device. SAR External Statistics Clock. Used as reference to transfer data between the SAR and an external adjunct. Agere Systems - Proprietary Agere Systems Inc. 18 Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 6 Pin Description (continued) Table 8. SAR External Statistics Interface Signals (18 Signals) Signal RESYNC Type O Description SAR External Statistics Sync. A single-cycle pulse signaling the beginning of the (RECLK) SAR statistics interface time slot. The absence of this synchronization pulse indicates that cell processing is disabled. Table 9. Host Interface Signals (49 Signals) Signal HMODE[1:0] HCLK Type Id I Description Host Interface Mode Select. Selects the mode of operation of the microprocessor interface. These pins must be connected to ground. Host Interface Clock. This interface is rising edge clocked. Data written to TAAD08JU2 is latched on the rising edge of clock, and address information and data outputs on the rising edge of clock. The maximum speed for this clock is 66 MHz. Host Data Bus. This is a bidirectional 32-bit data bus used to transfer data to/from TAAD08JU2. Host Address Inputs. 10-bit address for register read or write operations. This addressing is by 32-bit word. Host Chip Select. The active-low signal validates HA[9:0] for read and write transfers. Host Write Enable. 0 causes an active-low write, and 1 causes a read. Host Advance. A high signal on this pin causes TAAD08JU2 to increment a previous host address by one. Host Slave Mode Interrupt. Active-low interrupt request signal from TAAD08JU2. HD[31:0] HA[9:0] HCEN HWEN HADV HIRQ I/O Id Iu Iu Id O Table 10. JTAG Interface Pins (6 Signals) Signal TMODE TMS TDI TRSTN TDO TCK Type Id Iu Iu Iu O Iu Description JTAG Test Mode. This pin is an input with an internal pull-down. TMODE = 1 is reserved for Agere testing. Test Mode Select. This pin enables JTAG test mode. Pin has an internal pull-up. Test Data Input. Serial test input during JTAG testing. Test Reset. This signal must be asserted low on powerup. Test Data Output. Serial test output during JTAG testing. Test Clock. An internal pull-up exists on this pin. This pin is used to clock state and test data into and out of the TAAD08JU2 during JTAG testing. Table 11. Global/Miscellaneous Signal Pins (10 Signals) Signal GOE Type Iu Description Global Output Enable. When GOE is 0, all TAAD08JU2 outputs assume a highimpedance state except TDO. When GOE is 1, all outputs operate normally. An internal pull-up is provided on this pin. Global Clock. Maximum clock frequency is 52 MHz. All output clocks are derived from this clock. GCLK should have a minimum 60/40 duty cycle and a maximum frequency tolerance of ±0.05%. GCLKs frequency can range from 25 MHz to 50 MHz. When running slower than 50 MHz, the maximum throughput of TAAD08JU2 (which is 155 Mbits/s at 50 MHz) is degraded proportionately. GCLK I Agere Systems Inc. Agere Systems - Proprietary 19 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 6 Pin Description (continued) Table 11. Global/Miscellaneous Signal Pins (10 Signals) (continued) Signal GRESET Type Iu Description Global Reset. Active-low reset signal. On initial powerup, GRESET must be asserted for at least 250 µs after stable clocks are provided to TAAD08JU2, in order to allow the internal PLLs to stabilize. GCLK and HCLK must be continuously applied during reset. When asserted, all internal circuity is reset to its default condition. If TAAD08JU2 has already been powered on and operating, the device can be reset by asserting GRESET for at least 8 clock cycles of GCLK and 8 clock cycles of HCLK. Note that both of these clock signals must be applied for TAAD08JU2 to be properly reset. GRESET must be inactive for 2 ms before boot sequence can commence. Global PLL Bypass. This pin is used to bypass the operation of the global clock synthesizer PLL. This pin is intended for Agere manufacturing testing, and must be tied low for normal operation. Global PLL Output. A reference clock output of the PLL used only for Agere test purposes. Framer PLL Output. A reference clock output of the PLL used only for Agere test purposes. Scan Mode. This pin is used by Agere to scan test this device. Scan Clock 1. This pin enables Agere internal scan testing, and should be tied low for normal operation. Scan Clock 2. This pin enables Agere internal scan testing, and should be tied low for normal operation. IDDQ Test Mode Enable. This pin should be tied high for normal operation. When tied low, this pin is used for IDDQ testing. GPLLBYP Id GPLLOUT FPLLOUT SCANMODE SCANCLK1 SCANCLK2 IDDQ O O Id Id Id I Table 12. Power Supply Pins (4 Analog Power Pins, 120 Digital Power Pins) Signal GVDDA GVSSA FVDDA FVSSA VDD33 VDD15 VSS Type P P P P P P P Description Global PLL Power Supply. Separate dedicated 3.3 V power supply to power the global clock synthesizer PLL. This power supply should be a low-noise supply. Global PLL Ground. Separate 3.3 V ground to power the global clock synthesizer PLL. This should be a low-noise ground. Framer PLL Power Supply. Separate dedicated 3.3 V power supply to power the framer PLL. This power supply should be a low-noise supply. Framer PLL Ground. Separate dedicated 3.3 V ground to power the framer PLL. This should be a low-noise ground. 3.3 V Digital Power Pins. 1.5 V Digital Power Pins. Digital Ground Pins. 20 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 7 Package Pin Layout TAAD08JU2 uses the SuperBGATM EBGA-520 package (1.27 mm. pitch). ! ! ! ! Body size: 40 x 40 x 0.78 mm Maximum height off-board: 1.67 mm Solder ball pitch: 1.27 mm Thermal, ΘJA: 11 oC/W 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1.5 VSS VSS VSS 394 VSS 386 381 376 374 VSS 366 361 356 351 VSS 350 345 340 335 VSS 327 325 320 315 VSS 307 VSS VSS VSS 1.5 VSS 1.5 VSS 399 396 391 388 383 378 3.3 371 367 362 357 352 VSS 349 344 339 334 330 3.3 323 318 313 310 305 302 VSS 1.5 VSS VSS VSS 1.5 3.3 398 393 389 384 379 3.3 372 368 363 358 353 1.5 348 343 338 333 329 3.3 322 317 312 308 303 3.3 1.5 VSS VSS VSS 2 3.3 1.5 400 395 390 385 380 375 373 369 364 359 354 1.5 347 342 337 332 328 326 321 316 311 306 301 1.5 3.3 299 VSS 7 5 3 8 1 6 1.5 397 392 387 382 377 3.3 370 365 360 355 1.5 346 341 336 331 3.3 324 319 314 309 304 1.5 300 298 296 294 VSS 10 4 9 297 295 293 291 VSS 292 290 289 288 286 287 285 284 283 281 282 280 279 278 276 15 13 12 11 20 18 17 16 14 25 23 22 21 19 27 3.3 3.3 26 24 VSS 30 29 28 3.3 TOP VIEW VSS 277 275 3.3 3.3 274 3.3 273 272 271 VSS 35 34 33 32 31 40 39 38 37 36 45 44 43 42 41 50 49 48 47 46 VSS VSS 1.5 1.5 1.5 270 269 268 267 266 265 264 263 262 261 VDD15 (1.5 V) 260 259 258 257 256 255 254 253 252 251 VDD33 (3.3 V) 1.5 1.5 1.5 VSS VSS 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 VSS 71 72 73 3.3 246 247 248 249 250 SIGNAL PIN/SPECIAL VDD-VSS 241 242 243 244 245 236 237 238 239 240 231 232 233 234 235 3.3 228 229 230 VSS 74 3.3 3.3 75 77 76 78 79 80 82 81 83 84 85 87 86 88 89 90 92 VSS 91 93 95 97 224 226 3.3 3.3 227 219 221 222 223 225 214 216 217 218 220 209 211 212 213 215 204 206 208 210 VSS 94 96 98 100 1.5 104 109 114 119 124 3.3 131 136 141 146 1.5 155 160 165 170 3.3 177 182 187 192 197 1.5 201 203 205 207 VSS 99 3.3 1.5 101 106 111 116 121 126 128 132 137 142 147 1.5 154 159 164 169 173 175 180 185 190 195 200 1.5 3.3 202 VSS VSS VSS 1.5 3.3 103 108 112 117 122 3.3 129 133 138 143 148 1.5 153 158 163 168 172 3.3 179 184 189 193 198 3.3 1.5 VSS VSS VSS 1.5 VSS 102 105 110 113 118 123 3.3 130 134 139 144 149 VSS 152 157 162 167 171 3.3 178 183 188 191 196 199 VSS 1.5 VSS 1.5 VSS VSS VSS 107 VSS 115 120 125 127 VSS 135 140 145 150 VSS 151 156 161 166 VSS 174 176 181 186 VSS 194 VSS VSS VSS 1.5 5-9957(F) Figure 1. Pin Configuration Diagram Agere Systems Inc. Agere Systems - Proprietary 21 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 7 Package Pin Layout (continued) (Pins shown as Reserved must be left unconnected). Table 13. Signal-to-Ball Mapping Ball E4 D2 E3 F5 E2 F4 E1 F3 G5 F2 G4 G3 G2 H5 G1 H4 H3 H2 J5 H1 J4 J3 J2 K5 J1 K4 K1 L4 L3 L2 M5 M4 M3 M2 M1 N5 N4 N3 Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Data Sheet Ball Name AEDATA[15] AEDATA[14] AEDATA[13] AEDATA[12] AEDATA[11] AEDATA[10] AEDATA[9] AEDATA[8] AEDATA[7] AEDATA[6] AEDATA[5] AEDATA[4] AEDATA[3] AEDATA[2] AEDATA[1] AEDATA[0] URXDATA[15] URXDATA[14] URXDATA[13] URXDATA[12] URXDATA[11] URXDATA[10] URXDATA[9] URXDATA[8] URXDATA[7] URXDATA[6] URXDATA[5] URXDATA[4] URXDATA[3] URXDATA[2] URXDATA[1] URXDATA[0] URXENB URXPRTY URXSOC URXCLAV URXADDR[0] URXADDR[1] Preliminary Data Sheet August 18, 2003 Table 13. Signal-to-Ball Mapping (continued) Ball N2 N1 P5 P4 P3 P2 P1 R5 R4 R3 R2 R1 U1 U2 U3 U4 U5 V1 V2 V3 V4 V5 W1 W2 W3 W4 W5 Y1 Y2 Y3 Y4 Y5 AA2 AA3 AA4 AB1 AB4 AC1 AB5 AC2 Pad Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Data Sheet Ball Name URXADDR[2] URXADDR[3] URXADDR[4] UCLK UTXADDR[4] UTXADDR[3] UTXADDR[2] UTXADDR[1] UTXADDR[0] UTXCLAV UTXSOC UTXPRTY UTXENB UTXDATA[15] UTXDATA[14] UTXDATA[13] UTXDATA[12] UTXDATA[11] UTXDATA[10] UTXDATA[9] UTXDATA[8] UTXDATA[7] UTXDATA[6] UTXDATA[5] UTXDATA[4] UTXDATA[3] UTXDATA[2] UTXDATA[1] UTXDATA[0] UMODE STXDATA[15] STXDATA[14] STXDATA[13] STXDATA[12] STXDATA[11] STXDATA[10] STXDATA[9] STXDATA[8] STXDATA[7] STXDATA[6] 22 Agere Systems Inc. Preliminary Data Sheet August 18, 2003 7 Package Pin Layout (continued) Table 13. Signal-to-Ball Mapping (continued) Ball AC3 AC4 AD1 AC5 AD2 AD3 AD4 AE1 AD5 AE2 AE3 AE4 AF2 AE5 AF3 AG1 AF4 AG2 AF5 AG3 AH2 AG4 AH5 AK4 AJ5 AG6 AK5 AH6 AL5 AJ6 AG7 AK6 AH7 AJ7 AK7 AG8 AL7 AH8 AJ8 AK8 Pad Number 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Data Sheet Ball Name STXDATA[5] STXDATA[4] STXDATA[3] STXDATA[2] STXDATA[1] STXDATA[0] STXCLAV/STXPA/ STXSPA STXSOC/STXSOP STXPRTY STXSIZ STXENB STXERR STXEOP RESERVED STXADDR[0] STXADDR[1] STXADDR[2] STXADDR[3] STXADDR[4] SRXADDR[4] SRXADDR[3] SRXADDR[2] SRXADDR[1] SRXADDR[0] SUCLK SRXVAL SRXCLAV SRXSOC SRXPRTY SRXEOP SRXERR SRXENB SRXSIZ SRXDATA[15] SRXDATA[14] SRXDATA[13] SRXDATA[12] SRXDATA[11] SRXDATA[10] TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table 13. Signal-to-Ball Mapping (continued) Ball AG9 AL8 AH9 AJ9 AK9 AG10 AL9 AH10 AL10 AH11 AJ11 AK11 AG12 AH12 AJ12 AK12 AL12 AG13 AH13 AJ13 AK13 AL13 AG14 AH14 AJ14 AK14 AL14 AG15 AH15 AJ15 AK15 AL15 AL17 AK17 AJ17 AH17 AG17 AL18 AK18 AJ18 Pad Number 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 Data Sheet Ball Name SRXDATA[9] SRXDATA[8] SRXDATA[7]7 SRXDATA[6] SRXDATA[5] SRXDATA[4] SRXDATA[3] SRXDATA[2] SRXDATA[1] SRXDATA[0] SMODE2 SMODE1 SMODE0 REDATA[15] REDATA[14] REDATA[13] REDATA[12] REDATA[11] REDATA[10] REDATA[9] REDATA[8] REDATA[7] REDATA[6] REDATA[5] REDATA[4] REDATA[3] REDATA[2] REDATA[1] REDATA[0] RESYNC RECLK HIRQ HADV HWEN HCEN HCLK HA[9] HA[8] HA[7] HA[6] Agere Systems - Proprietary 23 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 7 Package Pin Layout (continued) Table 13. Signal-to-Ball Mapping (continued) Ball AH18 AG18 AL19 AK19 AJ19 AH19 AG19 AL20 AK20 AJ20 AH20 AG20 AK21 AJ21 AH21 AL22 AH22 AL23 AG22 AK23 AJ23 AH23 AL24 AG23 AK24 AJ24 AH24 AL25 AG24 AK25 AJ25 AH25 AK26 AG25 AJ26 AL27 AH26 AK27 AG26 AJ27 Pad Number 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 Data Sheet Ball Name HA[5] HA[4] HA[3] HA[2] HA[1] HA[0] HMODE1 HMODE0 HD[31] HD[30] HD[29] HD[28] HD[27] HD[26] HD[25] HD[24] HD[23] HD[22] HD[21] HD[20] HD[19] HD[18] HD[17] HD[16] HD[15] HD[14] HD[13] HD[12] HD[11] HD[10] HD[9] HD[8] HD[7] HD[6] HD[5] HD[4] HD[3] HD[2] HD[1] HD[0] Preliminary Data Sheet August 18, 2003 Table 13. Signal-to-Ball Mapping (continued) Ball AK28 AH27 AG28 AH30 AG29 AF27 AG30 AF28 AG31 AF29 AE27 AF30 AE28 AE29 AE30 AD27 AE31 AD28 AD29 AD30 AC27 AD31 AC28 AC29 AC30 AB27 AC31 AB28 AB31 AA28 AA29 AA30 Y27 Y28 Y29 Y30 Y31 W27 W28 W29 W30 W31 Pad Number 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Data Sheet Ball Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TCK TDO TRSTN TDI TMS TMODE GOE IDDQ SCANMODE SCANCLK2 SCANCLK1 GPLLOUT GRESET GCLK GPLLBYP GVSSA GVDDA FPLLOUT FVSSA FVDDA RESERVED 24 Agere Systems Inc. Preliminary Data Sheet August 18, 2003 7 Package Pin Layout (continued) Table 13. Signal-to-Ball Mapping (continued) Ball V27 V28 V29 V30 V31 U27 U28 U29 U30 U31 R31 R30 R29 R28 R27 P31 P30 P29 P28 P27 N31 N30 N29 N28 N27 M31 M30 M29 M28 M27 L30 L29 L28 K31 K28 J31 K27 J30 J29 J28 Pad Number 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Data Sheet Ball Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table 13. Signal-to-Ball Mapping (continued) Ball H31 J27 H30 H29 H28 G31 H27 G30 G29 G28 F30 G27 F29 E31 F28 E30 F27 E29 D30 E28 D27 B28 C27 E26 B27 D26 A27 C26 E25 B26 D25 C25 B25 E24 A25 D24 C24 B24 E23 A24 Pad Number 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Data Sheet Ball Name LRXNDATA7/LRXBPV7 LRXNDATA6/LRXBPV6 LRXNDATA5/LRXBPV5 LRXNDATA4/LRXBPV4 LRXNDATA3/LRXBPV3 LRXNDATA2/LRXBPV2 LRXNDATA1/LRXBPV1 LRXNDATA0/LRXBPV0 LRXPDATA7/LRXDATA7 LRXPDATA6/LRXDATA6 LRXPDATA5/LRXDATA5 LRXPDATA4/LRXDATA4 LRXPDATA3/LRXDATA3 LRXPDATA2/LRXDATA2 LRXPDATA1/LRXDATA1 LRXPDATA0/LRXDATA0 LRXCLK7 LRXCLK6 LRXCLK5 LRXCLK4 LRXCLK3 LRXCLK2 LRXCLK1 LRXCLK0 LTXNDATA7 LTXNDATA6 LTXNDATA5 LTXNDATA4 LTXNDATA3 LTXNDATA2 LTXNDATA1 LTXNDATA0 LTXPDATA7/LTXDATA7 LTXPDATA6/LTXDATA6 LTXPDATA5/LTXDATA5 LTXPDATA4/LTXDATA4 LTXPDATA3/LTXDATA3 LTXPDATA2/LTXDATA2 LTXPDATA1/LTXDATA1 LTXPDATA0/LTXDATA0 Agere Systems - Proprietary 25 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 7 Package Pin Layout (continued) Table 13. Signal-to-Ball Mapping (continued) Ball D23 C23 B23 E22 A23 D22 A22 D21 C21 B21 E20 D20 C20 B20 A20 E19 D19 C19 B19 A19 E18 D18 C18 B18 A18 E17 D17 C17 B17 A17 A15 B15 C15 D15 E15 A14 B14 C14 D14 E14 Pad Number 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 Data Sheet Ball Name LTXCLK7 LTXCLK6 LTXCLK5 LTXCLK4 LTXCLK3 LTXCLK2 LTXCLK1 LTXCLK0 CTXDATA7 CTXDATA6 CTXDATA5 CTXDATA4 CTXDATA3 CTXDATA2 CTXDATA1 CTXDATA0 CTXFS CTXCLK CRXDATA7 CRXDATA6 CRXDATA5 CRXDATA4 CRXDATA3 CRXDATA2 CRXDATA1 CRXDATA0 CRXFS CRXCLK ABRXDATA[7] ABRXDATA[6] ABRXDATA[5] ABRXDATA[4] ABRXDATA[3] ABRXDATA[2] ABRXDATA[1] ABRXDATA[0] ABRXCLKN ABRXCLKP ABRXSOC ABRXPRTY Preliminary Data Sheet August 18, 2003 Table 13. Signal-to-Ball Mapping (continued) Ball A13 B13 C13 D13 E13 A12 B12 C12 D12 E12 B11 C11 D11 A10 D10 A9 E10 B9 C9 D9 A8 E9 B8 C8 D8 A7 E8 B7 C7 D7 B6 E7 C6 A5 D6 B5 E6 C5 B4 D5 Pad Number 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Data Sheet Ball Name ABTXDATA[7] ABTXDATA[6] ABTXDATA[5] ABTXDATA[4] ABTXDATA[3] ABTXDATA[2] ABTXDATA[1] ABTXDATA[0] ABTXCLKN ABTXCLKP ABTXSOC ABTXPRTY AARXDATA[7] AARXDATA[6] AARXDATA[5] AARXDATA[4] AARXDATA[3] AARXDATA[2] AARXDATA[1] AARXDATA[0] AARXCLKN AARXCLKP AARXSOC AARXPRTY AATXDATA[7] AATXDATA[6] AATXDATA[5] AATXDATA[4] AATXDATA[3] AATXDATA[2] AATXDATA[1] AATXDATA[0] AATXCLKN AATXCLKP AATXSOC AATXPRTY AGTSYNC AHPSWF AESYNC AECLK 26 Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 8 Block Diagram UTOPIA EXPANSION INTERFACE TAAD08JU2 LINE INTERFACE B TC FRAMER A IMA APC AAL ENGINE CHI TDM INTERFACE EDC HOST PROCESSOR INTERFACE SYSTEM INTERFACE SWITCH FABRIC BUS 0145(F) Figure 2. Architecture of the TAAD08JU2 Device As seen in Figure 2, TAAD08JU2 provides a complete ATM low-speed access function. In comparison to current alternative devices, TAAD08JU2 provides framing, transmission convergence, inverse multiplexing for ATM, ATM port management, and AAL SARing functions in a single, highly integrated device. Furthermore, TAAD08JU2 is architected to be flexible and scalable to effectively handle alternative higher-rate physical interfaces. TAAD08JU2 provides the following features as a highly integrated system on a chip (SOC): ! ! ! A complete, integrated, low-speed ATM access device solution. Flexible solution for transporting mixed traffic classes with QoS guarantees. System-on-a-chip performance with a simpler OAMP API to enhance time-to-market. TAAD08JU2 terminates a variety of low-speed physical link protocols (T1/E1/J1) via an integrated framer. Each link can carry ATM cell streams corresponding to multiple connections. Transmission convergence (TC) provides cell delineation through HEC generation and checking. TC also provides cell rate decoupling between the ATM and PHY layers through insertion/discard of idle ATM cells. The IMA block provides for inverse multiplexing over ATM using one to four groups with two to eight links per group. The ATM port controller (APC) block provides all of the functionality of the Agere APC device, such as switching, traffic shaping, and policing. The AAL engine provides a number of segmentation and reassembly options based on AAL2 and AAL5 standards while maintaining multiple traffic classes and qualities of service. Agere Systems Inc. Agere Systems - Proprietary 27 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 9 Software Components This section discusses the software that is used to initialize, configure, and operate TAAD08JU2. The purpose of this section is to introduce these important software components, to familiarize the user with them, and to provide links to the appropriate documentation. TAAD08JU2 is a highly integrated SOC. The numerous functional blocks (see chapter 8) that the system comprises are connected together and controlled by an internal 32 bit ARM® processor. This processor runs software (known as firmware) that controls all the internal workings of TAAD08JU2 and all the external communications with the user's system. Control of the TAAD08JU2 system occurs via a communications protocol between the firmware running on the internal ARM and software running on an external microprocessor (host processor). Commands are sent to the firmware and responses are returned using this protocol. A library of C functions translates high-level API function calls into the command format expected by firmware and implements the communications protocol. This library of software is known as device manager (DevMan for short). A separate utility is also used to create a binary setup file that configures TAAD08JU2's operating modes and initializes tables. This utility is the TAAD08JU2 setup file utility (formerly known as Newport Setup File Utility, NSFU for short). End users of TAAD08JU2 write application code that, through the device manager, controls the TAAD08JU2 in their systems. Many levels of software are used to abstract the user from the internal details of the hardware in TAAD08JU2. (There is no direct access to the internal registers in TAAD08JU2. Control is strictly through firmware commands and indications.) The user's view of TAAD08JU2 is through the high-level device manager API calls. Figure 3 shows the scope of software components surrounding the TAAD08JU2 device. SYSTEM SOFTWARE APPLICATION CODE SFU DEVICE MANAGER FIRMWARE NP Figure 3. Software Components The rectangular block at the center of the figure refers to the physical TAAD08JU2 (formerly known as Newport, NP for short) hardware device. The physical device has a set of control registers, an input buffer, and an output buffer. These registers and buffers are known as the embedded device controller (EDC) registers. All control and data transfer is done through these registers and buffers. From the software point of view, TAAD08JU2 is a memory-mapped device with interface registers used to send commands and exchange data with the internal devices. See chapter 13 for details on the TAAD08JU2 registers that are visible to the host processor. 28 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 9 Software Components (continued) 9.1 Firmware The TAAD08JU2 chip contains an embedded ARM processor to manage the internal devices and communicate with the host processor. The ARM processor has no software permanently stored in TAAD08JU2. The user's host processor must load the ARM’s instructions into RAM located inside the TAAD08JU2 before the TAAD08JU2 can operate. These instructions are known as firmware. The ARM firmware files are supplied with the TAAD08JU2 software release. The firmware can be viewed as the assembly language of TAAD08JU2. All user-controllable functions of TAAD08JU2 are implemented as firmware commands (i.e., assembly-language statements in a microprocessor). To execute a command, the binary parameters of the command are loaded into the TAAD08JU2 EDC input buffer by the host processor. The command word is then written to the EDC command register. The ARM receives an interrupt, and the firmware then reads the command word from the command register and interprets the command parameters. The firmware executes the command. The firmware places the results of executing the command into the EDC output buffer and writes an indication word into the EDC indication register. TAAD08JU2 hardware then generates an external interrupt to the host processor notifying it that firmware has made data available. This is the handshaking that occurs to exchange commands and data between the external processor and TAAD08JU2 firmware. In summary, the key points of the TAAD08JU2 ARM firmware are: ! ! ! TAAD08JU2 contains an embedded ARM processor—a true SOC. Two binary files contain the ARM instruction code and data. The instruction code for the ARM processor is not permanently stored in TAAD08JU2, and thus must be downloaded into TAAD08JU2 every time the device is powered on or reset. Application software never talks directly to the ARM. Only the device manager sends firmware commands and receives indications from the ARM. ! 9.2 Device Manager The device manager for TAAD08JU2 is an applications programming interface (API) written in C. This software is referred to as device manager software or simply the device manager, and the interface is called the device manager API. Programmers use this interface to access and control TAAD08JU2 from their applications. The device manager is coded using ANSI C and is compiled into a library of functions for the host platform. TAAD08JU2 is a very complex device. Communication with the ARM processor firmware in TAAD08JU2 is somewhat complicated. The API is designed to provide programmers with a level of abstraction that hides the complexity of this device. Figure 4 illustrates how the device manager API is used to communicate with TAAD08JU2. Agere Systems Inc. Agere Systems - Proprietary 29 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 9 Software Components (continued) HOST PROCESSOR APPLICATION CODE DEVICE MANAGER API TAAD08JU2 EDC REGISTERS ARM—FIRMWARE Figure 4. Device Manager APIs and TAAD08JU2 Communications As shown in Figure 4, the host application code (typically high-level management software) is linked with the device manager library. It uses the C functions exported by the library to access and control TAAD08JU2. TAAD08JU2’s host interface provides for the hardware registers that are used to pass information to and from the firmware software. The device manager layer sends commands to the firmware for services. The firmware uses indications to inform the device manager about events that occur on TAAD08JU2. The device manager interprets the indications and, if required, conveys the results to the application. The device manager hides the details of the hardware from the application. The device manager API deals in highlevel functionality, not device registers. It also hides device-specific details where possible. Applications use the device manager’s C function interface to request services provided by the device manager. The return value of the C function indicates whether the called function was successful or not. Refer to the TAAD08JU2 device manager API document for more details on device manager implementation and the available API functions. In summary, the key points of the TAAD08JU2 device manager are as follows: ! ! ! The device manager is a set of C functions that applications use to configure, control, and monitor TAAD08JU2. The device manager library is called by the application code. It is not a separate, stand-alone application. The device manager is the interface between application code and the TAAD08JU2 device. Application code never accesses TAAD08JU2 registers directly. Application code never sends firmware commands or receives firmware indications. The device manager translates application calls into firmware commands, which then are sent to the ARM in TAAD08JU2. The device manager handles alarm recording and statistics reported by TAAD08JU2. The device manager handles downloading the ARM firmware into TAAD08JU2 during start-up. ! ! ! 9.3 Setup File Utility (SFU) The TAAD08JU2 setup file utility (also known as Newport Setup File Utility, NSFU for short) runs on a Windows® PC and guides the user through the initial configuration of TAAD08JU2. The NSFU software package creates a binary setup file containing configuration commands, which are downloaded to TAAD08JU2 using a device manager API. 30 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 9 Software Components (continued) The user is encouraged to use the setup file utility to generate the sequence of setup commands and store them in a setup file. The setup utility allows the user to choose the mode information by simply clicking on the GUI to select options. It ensures that the user selects a valid combination of options by providing appropriate error messages and, where possible, by restricting the available options to the appropriate ones. This methodology brings the great advantage that the firmware is freed from having to perform error checking on all the provisioning parameters, which reduces the embedded code size. In addition, the GUI handles the translation of provisioning parameters into per-block provisioning parameters, also reducing the complexity of the initialization code. Once the host via device manager has downloaded the setup file to TAAD08JU2, the provisioning of the device is complete. The TAAD08JU2 waits for the next command from the host or provides an indication to the host if an interrupt occurs or an alarm goes off. See the TAAD08JU2 setup file utility software for more details on using this utility. 9.4 TAAD08JU2 Application Code The TAAD08JU2 application code performs the actual initialization, configuration, control, and monitoring of TAAD08JU2 through device manager API function calls (configuration that is done by the NSFU can also be accomplished via the application code). This software is written by users to implement TAAD08JU2 in their system. The device manager is not an autonomous program. It is only an interpreter between the user's application code and TAAD08JU2. It is up to the application code to instruct device manager to initialize TAAD08JU2, download the firmware, download the setup file, add connections, monitor alarms and statistics, etc. Therefore, the programmer of TAAD08JU2 should be very familiar with all of the API functions and data types listed in the TAAD08JU2 device manager API document. The following application pseudocode demonstrates control of TAAD08JU2 using device manager API calls: /* Reset the TAAD08JU2 chip - board specific */ lapiInitialize(..); /* Initialize DevMan */ /* User must allocate all memory used by DevMan *. npGetNewportDeviceMemoryRequirement(..); pDev1Handle = malloc(MemoryRequired); lapiInitializeDevice(pDev1Handle, ..); npLoadFirmware(..); /* download the 2 ARM firmware binary files */ lapiSetupDevice(..); /* Download NSFU file */ /* Now add connections, monitor stats, etc. etc. */ npAddConnection(..); ... ... ... /* When all done, shutdown TAAD08JU2 and DevMan */ lapiFinalizeDevice(..); /* Users must free memory they allocated for Device Manager */ free(pDev1Handle); lapiFinalize(); Complete example applications illustrating the proper use of device manager API functions are provided in the TAAD08JU2 software release documentation. Agere Systems Inc. Agere Systems - Proprietary 31 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 9 Software Components (continued) 9.5 System Software The system software is the customer's software controlling the entire system in which a TAAD08JU2 device operates. This software is responsible for configuring peripheral devices around TAAD08JU2 and determining the operating modes of TAAD08JU2. Working examples of system software, running on the Agere TAAD08JU2 evaluation board set, are provided in the Agere software release. 9.6 Software Development Environment Figure 5 is an example of a TAAD08JU2 software development environment. The TAAD08JU2 SOC is totally controlled by software. TAAD08JU2's internal functional blocks are controlled by software (firmware) running on the embedded ARM processor. The firmware must be downloaded by host software into TAAD08JU2 in order for the ARM to boot. Even then, there are no specific directives in the firmware to configure TAAD08JU2 and have it begin executing autonomously. TAAD08JU2 must be initialized, configured, and controlled by an external microprocessor; hence, some form of a software development effort is required in order to use the TAAD08JU2 device. APPLICATION CODE COMPILER DEBUGGER RTOS TARGET BOARD APPLICATION & DEVMAN CPU NSFU TAAD08JU2 SOFTWARE (DEVMAN LIBRARY & FIRMWARE DEVELOPMENT PC SETUP FILE TAAD08JU2 FIRMWARE Figure 5. TAAD08JU2 Software Development Environment Figure 5 details a typical TAAD08JU2 software development environment. The hardware components in the example are the following: ! ! TAAD08JU2: the TAAD08JU2 device. CPU: the external host CPU to which TAAD08JU2 is connected. TAAD08JU2 is usually a memory mapped device on the processor's bus. Target Board: a stand-alone, embedded, single-board computer. The board usually has a real-time operating system (RTOS) running on it to provide resource management (processor start-up, serial communications, networking, etc.). The target board has RAM to hold the TAAD08JU2 DevMan and application code and possibly nonvolatile storage for the firmware and setup file(s). Development PC: a Windows-based PC used for developing the TAAD08JU2 software that will run on the target board. The PC is connected to the target board by some means (serial, network, or other). ! ! 32 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 9 Software Components (continued) The software components are the following: ! Application and DevMan: the executable application and TAAD08JU2 device manager code, linked together to run in the target board's environment and access the TAAD08JU2 EDC registers and interrupt. Firmware: the ARM binary files that must be downloaded into TAAD08JU2 by the application using DevMan calls. Setup file: the binary configuration file created by the NSFU, loaded into TAAD08JU2 by the application using DevMan calls. Compiler/debugger/RTOS: a software development tool kit to compile C code into executable form that will run on the target board CPU. A real-time operating system would probably be included with these tools to manage the target board. A source-level debugger would also assist in debugging application code running on the target board. TAAD08JU2 software: the device manager source code ported to the particular compiler and RTOS being used on the target board. The two binary firmware files that need to be downloaded into TAAD08JU2 are also provided in the software package. NSFU: the TAAD08JU2 setup file utility that runs on a Windows PC and generates the setup file. Application code: the user's code. This code is responsible for initializing DevMan, making the firmware and setup files available to DevMan, and calling DevMan functions to configure and control TAAD08JU2. It is usually linked with DevMan and downloaded to the target board where it runs. ! ! ! ! ! ! 9.7 Notes The following notes apply to initializing, configuring, and operating TAAD08JU2 Version 3.1 only: 1. A minimum number of static queues must be allocated in each of the two enqueue blocks of the SAR (ISIA and ECA). Assuming a default configuration, the minimum number is three. 2. When AAL5/SSSAR/SSTED packet data is reassembled to the host, the user must allocate an IL2Q for each direction in which data is sent to the host. Both of these queues are in the 2—7 range; therefore, they are both ingress queues. Then the user must allocate level 1 queues for egress and ingress to the host. The egress to the host queue must have a source direction of egress. The ID of the egress to host queue is in the 2—7 range. The IL2Q for egress to host traffic is still associated with portID 31. Agere Systems Inc. Agere Systems - Proprietary 33 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 10 Functional Overview Depending upon the provisioned mode of operation, the cell stream associated with a link may be treated as an ATM user network interface (UNI) or combined along with several other links associated with an inverse multiplexing over ATM (IMA) group. The IMA block is provided to terminate the IMA protocol. An ATM service access point (SAP) is effectively provided between the TC and the ATM layers via an internal UTOPIA-2 multi-PHY (MPHY) interface and associated control logic. The ATM layer functions such that connection management, QoS scheduling, buffer management, and statistics gathering are provided by an ATM port controller (APC) block, a modified version of the Agere ATLANTA® APC device. An ATM-SAP is also provided between the ATM and AAL layers via an internal UTOPIA interface and associated control logic. The AAL engine adapts service-specific convergence sublayer (SSCS) packets into ATM cells, supporting both AAL2 and AAL5 protocols. The AAL engine includes class-of-service multiplexing to enable a single AAL2 VC to transport connections of different traffic types. Finally, the SSCS packet is exchanged with the destination SSCS entity via the system interface operating in one of two modes. TAAD08JU2’s system interface supports the following: ! ! Standard UTOPIA level 2 (also known as UT2) cell-based MPHY master port. UTOPIA level 2 plus packet-over-SONET (also known as UT2+) MPHY master port. Underlying this system-on-chip implementation is an embedded device controller (EDC) that provides an intelligent higher-level interface for provisioning and monitoring as well as alarm correlation and statistics gathering. This higher-level, command-based interface simplifies integration of TAAD08JU2 into end systems by reducing firmware development efforts. 10.1 Receive Direction Data Flow This section describes the basic operation of TAAD08JU2 as data is received from the T1/E1/J1 line interface (shown on the left side of Figure 2) and is processed by TAAD08JU2. 10.1.1 PHY Layer TAAD08JU2 may receive cells from either low-speed interfaces (T1, E1, or J1) or high-speed interfaces (155 Mbits/s) via the following: ! ! Eight T1/E1/J1 span line interface ports One UTOPIA-2 16- or 8-bit MPHY port that bypasses the framer, TC, and IMA functions. 10.1.2 Low-Speed PHY Links In the case of low-speed interfaces, TAAD08JU2 enables flexible link assignments for either IMA or UNI mode on a per-link basis. This provisioning capability enables users to isolate delay-sensitive traffic from delay-insensitive traffic by steering time-critical traffic flows onto UNI mode links while carrying other data on IMA mode links. TAAD08JU2’s scheduler views each logical link independently, whether the logical link consists of a single physical link (UNI mode) or multiple physical links (IMA mode group). If IMA mode is selected, the link is also assigned to an IMA group. TAAD08JU2’s scheduler may also guarantee bandwidth to real-time-critical traffic while in IMA mode (since ATM layer processing is independent of the TC and PHY layers). TAAD08JU2’s eight physical ports may be configured in any configuration of links and groups with up to four IMA groups. TAAD08JU2 also provides the capability to switch nxDS0 channels to/from the span lines from/to a concentrated highway interface (CHI) time-division multiplexed (TDM) bus for legacy applications. This provides the ability to share bandwidth on a span line between ATM and TDM traffic. 34 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 10 Functional Overview (continued) 10.1.3 High-Speed PHY Links TAAD08JU2 provides the ability to connect a high-speed external PHY/TC framer device directly to the ATM layer functions via the UTOPIA expansion port. This port can operate at up to 50 MHz. For this path, the internal framer engine, TC, and IMA blocks are bypassed. This high-speed PHY expansion port can be used in combination with the low- and medium-speed PHY links. Note: This expansion port can also be used as an ATM service access point for connections to AAL and system devices. The UTOPIA expansion bus operates at up to 50 MHz and 16-bit data bus widths. 10.1.4 TC and IMA Layers As data is received by the framer, it delineates the data into time slots and bytes and then passes the data to the TC and IMA blocks. The TC determines the proper ATM cell boundaries. The cells are then passed to the IMA block. When receiving data from the TC/IMA blocks, the APC determines which logical link data is received based on the MPHY addressing presented by the IMA block. The IMA block provides the ability to group multiple physical low-speed links into a single logical high-speed link, approximately equal in bandwidth to the sum of individual low-speed links (less IMA protocol overhead). One to four IMA groups may be specified for TAAD08JU2, ranging from a minimum of two links per IMA group to a maximum of eight links per IMA group. The effect of an IMA group is to reduce the transmission latency of long packets (corresponding to high-speed bursts) by increasing the apparent bandwidth available to the data flow. IMA enables a network operator to scale transport capacity for higher bandwidth flows in a more granular way without having to buy more expensive excess capacity. That is, multiple T1/E1 links may be added as demand grows, rather than T3. In the receive direction, the IMA block detects link failures and automatically rebalances the offered load (in the transmit direction) across the remaining good links. The IMA block provides an indication of a failed link to the APC block as a type of backpressure to redistribute the offered load over the smaller bandwidth of the remaining good links. Any data (cells) currently being transmitted over the bad link may necessarily be lost and cannot be retransmitted across the other links. The IMA block removes IMA-protocol-specific cells from the cell stream (in the receive direction) and verifies the IMA protocol across each group’s links. Thus, only data stream cells are transferred between the IMA and APC blocks. TAAD08JU2 provides these protocol checking functions autonomously (via the EDC block) without requiring intervention by an external host device. Agere Systems Inc. Agere Systems - Proprietary 35 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 10 Functional Overview (continued) 10.1.5 ATM Layer Receive ATM layer functions such as connection management, header look-up translation, ingress queueing, OAM, and performance-monitoring processing are provided by the APC block, which is derived from the standardproduct Agere APC device. In the APC receive direction, cells are transferred from the IMA via a UTOPIA-2 interface. In this case, the APC block provides a UTOPIA-2 master function to poll cells from the PHYs. The APC block buffers the cells (so as to prevent cell loss due to buffer overrun in the TC block) and determines the egress destination port for the cell. The APC block may switch the cell to any of several destinations, as follows: ! ! ! Any of 31 APC egress ports The EDC block to be processed or sent out the host interface Any of 40 ATLANTA switch fabric ports connected to the switch fabric interface Within TAAD08JU2, the APC block provides a novel architecture in which ingress and egress internal data buffer space is shared across PHY links and the AAL engine. This enables TAAD08JU2 to route cells from one span line to another span line based on the ATM cell header for an add/drop multiplexer-like ATM-based switch function. The destination port is determined via a header look-up into internal context memory. 10.1.6 AAL Engine The AAL engine receives cells from the ATM layer (APC block) via the UTOPIA-2 bus. The APC is the bus master. Data is transferred from the TC block, the IMA block, or an external source via the UTOPIA expansion interface, into the APC via the UTOPIA-2 bus. Cells are then transferred to the AAL engine. Following AAL processing, cells or packets are forwarded to their destination via the system interface. Alternatively, cells could be received via the switch fabric interface. In this mode, the data enters the APC block via the switch fabric port and then exits via the UTOPIA-2 bus to the AAL engine. From there it is processed and sent out the system interface via the Rx egress system bus as packets, just as in the previously illustrated flow. The AAL engine provides the following types of services, based upon the SSCS entity pertaining to the connection: ! ! ! AAL5 reassembly AAL2/I.366.1 frame reassembly from AAL2 CPS packets AAL2 demultiplexing (in the case of short CPS packets) In addition, if the system interface is the cell-based UTOPIA-2 MPHY, the AAL engine may demultiplex CPS packets from an AAL2 VC into AAL0 cells so that the AAL2 connections can be routed to different destinations within the system. The packets or cells are forwarded to the system interface port operating in one of two modes: ! ! UTOPIA-2 (cell transfer) UTOPIA-2+ (packet transfer) The AAL engine provides class-of-service packet scheduling onto the system interface port to distribute service to different types of traffic via a weighted round-robin scheduler. The AAL engine provides quality-of-service scheduling onto both system and network interfaces to distribute service to different types of traffic via a hierarchy of schedulers. The AAL engine may also detect that certain packets (CPS-SDUs or reassembled AAL5 packets) are destined for the external host device. In this case, the AAL engine transfers the packet to a buffer for access by the external host via TAAD08JU2's device manager. 36 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 10 Functional Overview (continued) 10.1.7 Embedded Device Controller The embedded device controller (EDC) consists of a microcontroller that manages the general operation of the other blocks and communicates with an external CPU via the host interface. 10.2 Transmit Direction Data Flow The transmit direction refers to data transfer from the system interface/switch fabric interface/host microprocessor, through TAAD08JU2, and out through the network interface. 10.2.1 SSCS/AAL Layer Interaction Data to be exchanged with the PHY link may be received from one of the following four sources: ! ! ! ! System interface ATLANTA switch fabric interface External host microprocessor UTOPIA expansion port Data from the system interface may be formatted as cells or packets. In the case of a cell stream, TAAD08JU2's AAL engine may provide AAL0 CPS-packet or AAL2 VC multiplexing; AAL5 cells are passed directly to the ATM layer. In the case of a packet stream, TAAD08JU2's AAL engine may be programmed to provide the following processing (via the AAL engine): ! ! ! ! AAL5 segmentation AAL2/I.366.1 frame SARing into AAL2 CPS packets AAL2 multiplexing (in the case of short CPS packets) AAL2 class-of-service scheduling (when multiple traffic classes share a common AAL2 VC) Data from the ATLANTA switch fabric may be switched to the AAL engine (for AAL0 to AAL2 multiplexing or AAL2 to AAL0 demultiplexing) and then to a PHY link. Also, data may be transferred from the system interface through the AAL engine and routed by the APC to the switch fabric interface. Data from the external host microprocessor may undergo either of the following: ! ! ! AAL5 SARing for an SSCOP service AAL2 multiplexing as a CPS packet AAL2/I.366.1 SARing 10.2.2 ATM Layer The APC block performs normal queue management and scheduling (on a VC basis) corresponding to destination PHY link speed. The APC block moves cells to the IMA block via the APC_TX_Egress UTOPIA bus where the MPHY ID determines the destination for the cell as either one of four IMA group PHYs or one of eight UNI PHYs. The APC UTOPIA-2 bus block acts as a master, while the IMA UTOPIA-2 bus block acts as a slave. Alternatively, the APC block may schedule delivery to an external PHY/TC via the expansion UTOPIA-2 MPHY port. Again, the APC is the UTOPIA master. Agere Systems Inc. Agere Systems - Proprietary 37 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 10 Functional Overview (continued) 10.2.3 IMA/TC Layer The IMA block receives a cell from the APC block via the internal UTOPIA bus and determines the destination port from the MPHY address. If the MPHY address indicates an IMA group, the IMA block routes the cell stream to the appropriate group state machine, which distributes cells in a round-robin fashion across the subtending links. ICP and filler cells are inserted under control of the IMA block, based on IMA frame synchronization and ATM layer traffic rates. In the case of a UNI link, the cells are routed from the ATM layer (APC macrocell) to the TC directly by bypassing the IMA processing. In the IMA transmit direction, the APC block views IMA groups and UNI links as independent logical paths. Thus, the APC block schedules traffic onto the j-th logical PHY as an n x 1.5 Mbits/s (n x 2 Mbits/s) link; n = 1 in the case of a UNI link. Data is transferred between the IMA/TC block and the APC via a UTOPIA-2 MPHY bus where each IMA group or UNI link constitutes a single-destination PHY. The APC block schedules flows onto a maximum of eight PHYs (corresponding to the eight links) or a minimum of one PHY (corresponding to a single eight-link IMA group). The IMA block to framer block interface is via a TC function. Thus, the IMA block provides the ability for the APC block to issue/receive cells directly to/from the framer when links are not provisioned in IMA mode. In this case, each such link is provisioned in UNI mode. 10.2.4 PHY Layer Cells are mapped onto the associated PHY link based on the frame type (T1, E1, or J1). Direct mapping is used to map cells in an octet-aligned fashion into the frame payload. 38 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 11 Modes of Operation This section provides a high-level description of TAAD08JU2’s device operating modes, as well as its interface operating modes. The first section describes the various modes for each interface. The sections following the interface mode section describe the basic modes of operation for TAAD08JU2. 11.1 Interface Modes To provide flexibility, the line interface port, UTOPIA expansion port, and the system interface port pins are multiplexed interfaces sharing different functions that are programmed during device configuration. UTOPIA EXPANSION INTERFACE LINE INTERFACE TAAD08JU2 CHI TDM INTERFACE SWITCH FABRIC BUS SYSTEM INTERFACE HOST PROCESSOR INTERFACE 5-9963(F) Figure 6. TAAD08JU2 Interfaces 11.1.1 UTOPIA-2 Expansion Port Multiplexing Modes The UTOPIA-2 expansion port may be configured in one of the following two operating modes: ! UTOPIA-2 MPHY master, 16-bit mode, 25 MHz or 50 MHz: — Internal or external PHY mode UTOPIA-2 MPHY slave, 16-bit mode, 50 MHz: — SAR-only mode ! 11.1.2 System Interface Port Multiplexing Modes The system interface port may be configured in one of two operating modes: ! ! UTOPIA-2 MPHY master, 8-bit or 16-bit mode, 25 MHz or 50 MHz UT2+ MPHY master, 8-bit or 16-bit mode, 25 MHz or 50 MHz Agere Systems Inc. Agere Systems - Proprietary 39 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 11 Modes of Operation (continued) 11.1.3 Line-Interface Modes The following two line-interface modes of TAAD08JU2 can each be configured in three different areas: ! Line-formatting modes: — T1, E1, or J1 — T1 and E1 can be mixed — IMA groups must be composed of links with the same protocol Transmit-clocking modes: — Loop timing — Common transmit clock (CTC) — Independent transmit clock (ITC) ! 11.2 Device Operating Modes By configuring TAAD08JU2 via pin settings and commands, TAAD08JU2 can be enabled to operate in several modes, as follows: ! ! ! Internal PHY mode External PHY mode SAR-only mode These device operating modes are briefly illustrated on the following pages. 11.2.1 Operating Mode 1: Internal PHY Mode TAAD08JU2 LINE INTERFACE UTOPIA EXPANSION INTERFACE APC IMA CHI TDM INTERFACE FRAMER TC A SYSTEM INTERFACE SYSTEM B AAL ATM SWITCH FABRIC LIU CHI FRAMER DEVICE EDC HOST PROCESSOR INTERFACE HOST CPU/RAM/ ROM, ETC. SWITCH FABRIC BUS 0146(F) Figure 7. Mode 1: Internal PHY Mode Operation The internal PHY mode provides termination of low- or medium-speed span lines carrying ATM cell traffic. Each PHY link may be individually configured as either UNI or IMA mode. In the case of IMA operation, TAAD08JU2 supports up to four IMA groups. A group may comprise two to eight IMA links. 40 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 11 Modes of Operation (continued) TAAD08JU2 implements all IMA group and link state machine behavior within the device with no real-time intervention required by an external host processor. This includes differential delay measurement and mitigation, link synchronization, IMA frame synchronization, and insertion/checking of IMA control protocol (ICP) and filler cells. The IMA virtual link and UNI link cell streams are provided to the ATM layer function within TAAD08JU2 for connection management, buffer management, OAM and PM cell processing, and QoS scheduling. The ATM layer function provides the capability to switch cells from one span line to a different span line for ATM-based grooming. The ATM layer function may also forward cells to the AAL engine function for further processing. If the UTOPIA-2 cell-based system interface is used, the AAL engine may pass AAL5 cells directly to the system interface, while demultiplexing individual packets from AAL2 VCs into individual AAL0 cells. In this mode, TAAD08JU2 provides the ability to route cells onto a cell-based backplane to provide an access function for an ATM switch. The AAL0 and AAL5 cells may be routed through the switch fabric to an egress port, where converging AAL0 cells are remultiplexed into AAL2 VCs. If the UT2+ packet-based system interface is used, the AAL engine provides AAL5 reassembly and AAL2 SARing before forwarding the packet onto the system interface. AAL2 VCs are decomposed into individual CPS packets, prepended with a simple layer 2 packet header, and transmitted over the packet system interface. TAAD08JU2 provides the ability to reassemble frames from multiple AAL2 SDUs in support of ITU I.366.1 SSSAR functionality. TAAD08JU2 also provides the ability to schedule packet transmission onto the system interface via traffic class scheduling to share service across different traffic types. An additional function in the internal framer mode capabilities provides the capability to map ATM traffic into fractional (nx64) logical channels and TDM traffic into the remaining (mx64) logical channels for simultaneous transport of ATM and TDM traffic. This is an enhancement to the internal framer mode in which the CHI interface is enabled. One example of an application where this feature is useful is colocated 2G and 3G base transmission sites (BTS). In this case, the 2G traffic is backhauled on a separate logical channel within a shared physical channel (span line). TAAD08JU2 enables multiplexing (on an nxDS0 basis) of TDM traffic onto a span line along with ATM traffic via logical pipes. ANALOG BTS CHI TDM INTERFACE 3G BTS SPAN LINE BSC LIU TAAD08JU2 ATM CELL MAPPING, 1-n OCTETS TDM CELL MAPPING, n-24/31 OCTETS T1 OR E1 FRAME 5-9966(F) Figure 8. Example of Sharing Span Line with TDM and ATM Data Agere Systems Inc. Agere Systems - Proprietary 41 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 11 Modes of Operation (continued) In Figure 8, the DS0 time slots designated as TDM are multiplexed to/from the CHI bus interface, through the framer block, to/from the T1 or E1 span line. The size of the TDM logical pipe may vary from 0 to N, where N is the number of time slots in the PHY frame structure. The CHI bus is a 32-DS0 frame structure. Regardless of the size of the ATM channel, only 64 kbits/s clear channel span lines are supported. Also, only a single ATM logical channel is supported per span line port; i.e., the logical channel must be composed of consecutive time slots and cannot be split among time slots within a frame. Due to the capacity of the CHI buses, this mode is only available for T1/E1/J1 line interface modes. Other optional traffic routing in this mode includes the use of the switch fabric interface via the APC block instead of the system interface and use of the UTOPIA expansion port in conjunction with the network interface. MPHY addresses not used for the internal connections can be configured for use by the UTOPIA expansion interface. 11.2.2 Operating Mode 2: External PHY Mode OC3/ STS-3 LINK 155 Mbits/s ATM PHY INTERFACE TAAD08JU2 LINE INTERFACE UTOPIA EXPANSION INTERFACE SWITCH FABRIC BUS NOT USED CHI TDM INTERFACE TC FRAMER IMA B APC ATM SWITCH FABRIC AAL A SYSTEM INTERFACE NOT USED SYSTEM EDC HOST PROCESSOR INTERFACE HOST CPU/RAM/ ROM, ETC. 0147(F) Figure 9. Mode 2: External PHY Mode TAAD08JU2 also supports bypass of the low-speed framer/TC and IMA blocks for direct access to the ATM layer and AAL engine functions via a high-speed UTOPIA-2 MPHY interface. In this mode, an external high-speed PHY/TC function may be used to provide access to an OC-3 ring. The ATM layer can filter and process only drop cells. A typical application may be any RAC or BTS that requires access to a high-speed ring, yet terminates only a portion of the total traffic at any particular node. In this mode, TAAD08JU2 may provide SARing or cell switching onto the corresponding system interface. TAAD08JU2 supports up to 155 Mbits/s of data traffic on this interface when operating with a 50 MHz global clock. Even though the switch fabric would not typically be used in this mode, TAAD08JU2 allows full use of this interface. 42 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 11 Modes of Operation (continued) 11.2.3 Operating Mode 3: SAR-Only Mode UTOPIA MASTER DEVICE UTOPIA EXPANSION INTERFACE TAAD08JU2 LINE INTERFACE NOT USED CHI TDM INTERFACE TC FRAMER IMA B APC AAL A SWITCH FABRIC BUS SSCS FUNCTION SYSTEM INTERFACE NOT USED EDC HOST PROCESSOR INTERFACE HOST CPU/RAM/ ROM, ETC. 5-9968(F) Figure 10. Mode 3: SAR-Only Mode The SAR-only mode refers to the capability in which TAAD08JU2 is used as a SAR device only. In this mode, the AAL2 cells entering the UTOPIA expansion interface, which is operating in slave mode, are sent to the AAL engine, bypassing the APC. The AAL engine would provide SARing functions for the supported AAL processing. In this mode, all blocks except SAR and EDC are disabled. When instructed to do so, the AAL engine processes data received on AAL2 connections at the CPS layer. For VCs received from the expansion port, the CPS packets may be queued for either the system interface or looped back to the expansion port. This capability enables the SAR to implement a CID switching capability where data on a given terminated VC/CID may be demultiplexed from the source VC and remultiplexed into a new destination AAL2 VC with a configurable CID. 11.2.4 Operating Mode Summary TAAD08JU2's flexible architecture readily accommodates many ATM access termination challenges while providing open, telecom application-friendly interfaces. The basic modes covered in this document do not represent the only possible operating configurations. The ability to route traffic is not limited to these configurations, and many other combinations are possible by using loopbacks in various blocks and the switching capabilities of the APC. Complementing its APC-based ATM layer architecture with powerful PHY/TC and AAL layer functions, TAAD08JU2 offers a powerful solution to address the convergence of voice and data traffic through a system-onchip approach that minimizes time to market. Agere Systems Inc. Agere Systems - Proprietary 43 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 12 Applications TAAD08JU2 can be used in several applications where low-speed ATM access is required. Target applications include the following: ! ! ! ! BTS network interface termination Voice traffic over ATM (VToA) trunking application Low-speed ATM access AAL2 crossconnect The following subsections describe TAAD08JU2 in each of these applications. 12.1 BTS Network Interface Termination In the BTS network interface termination, TAAD08JU2 provides several useful features. First, third-generation systems require ATM transport for a variety of traffic types, including compressed speech, video, data, and signaling information. TAAD08JU2 supports this through features such as AAL2 and AAL5 transport, AAL2 multiplexing/demultiplexing, and QoS scheduling. AAL2 is especially useful for these wireless systems because most speech packets are short packets, and AAL2 enables multiplexing of several such packets into a single ATM cell, realizing efficient transmission to the BSC. For example, assuming a CDMA-based EVRC speech compression algorithm, from 160 to 200 user connections may be supported on a single T1/E1 span line. Moreover, each of the user connections pertain to a unique channel element (within the BTS) and must be demultiplexed from the ATM VC into individual packets. TAAD08JU2 provides this function by mapping AAL-CIDs into AAL0 cells and forwarding the cells to the destination modem channel card. Third-generation wireless systems also anticipate higher user access speeds, ranging up to 2 Mbits/s. For a 20 ms air frame, this corresponds to ~5000 octets per user. Typically, such data will be transported as ATM/AAL5 flows with different QoS requirements, depending on the source data. IWF N=8 SPANS BSC BTS MODEM CARD CE CE CE CE CE CE RF LOW-SPEED NIC TAAD08JU2 SAR BTS 5-9971(F) Figure 11. BTS Application TAAD08JU2 supports this data traffic by passing through AAL5 cells (which will be reassembled at their destination) with corresponding egress QoS scheduling utilizing the APC scheduling services. Moreover, such traffic tends to be bursty, yet has maximum latency requirements to ensure delivery in time for soft-hand-off diversity combining. TAAD08JU2 supports this need by the use of the IMA block, which reduces the transport latency of long packets while allowing reduced operating costs by not requiring migration to higher-speed transport links (since such traffic is bursty and such pipes may tend to be underutilized). 44 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 12 Applications (continued) Finally, the wireless application necessitates economic and efficient interconnection of microcell or picocell sites so that overall transport costs are minimized. Typically, this may be ensured either by daisy-chaining BTSs or by concentrating traffic in a gateway application. TAAD08JU2 supports this need through the internal prioritizing of passthrough traffic and switching (in the daisy-chain application) through an ATM drop-and-insert feature utilizing the APC’s switching capabilities. TAAD08JU2 further supports such topologies with an egress system interface UTOPIA-2 MPHY bus that enables routing traffic to multiple destinations (in the gateway application). PSTN MSC BSC 5-9972(F) Figure 12. BTSs Require ADM Functions IN-BUILDING PICOCELL CONFIGURATION GATEWAY CONTROLLER 8-T1/E1 SPAN LINES BSC TAAD08JU2S HDLS UTOPIA RP RP RP RP 5-9973(F) Figure 13. Gateway Controller Agere Systems Inc. Agere Systems - Proprietary 45 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 12 Applications (continued) 12.2 VToA Trunking Application Typically, ATM is used to transport CBR services such as voice services via AAL1. However, for low-speed access and PCM traffic, AAL1 is inefficient due to cell header and AAL overhead. ATM/AAL1 may map either multiple samples (n x 64 kbits/s) pertaining to a single connection (with up to 5.875 ms worth of speech) or multiple samples pertaining to multiple connections in a single ATM cell. However, efficient VToA is provided by efficiently transporting compressed speech. In this application, speech is first compressed, possibly utilizing silence-interval suppression. Then the speech packet is multiplexed into an ATM VC utilizing AAL2. TAAD08JU2 supports this application in its normal AAL2 cross connect mode, in which cells are forwarded to TAAD08JU2 from DSPs and compressed into AAL2 by TAAD08JU2. This relieves the DSP from having to provide transport protocol processing. Note: An interworking function may be provided between the DSP and TAAD08JU2 to map the speech packets into ATM. For example, a SAR could be used. However, concentration of the voice packets into a VC should be performed as close to the egress port as possible for maximum statistical multiplexing across many sources. This is why TAAD08JU2 provides an advantage over localized stat-MUXing on a single DSP card. Also, most SARs do not provide AAL2 support. RAC T1/E1 64 Kbits/s PCM PSTN CO FRAMER DSP VARIABLE LENGTH PACKETS OR AAL0 CELLS N = 8 T1/E1 ATM/AAL2 COMPRESSED VOICE FRAMER DSP IWF UTOPIA TAAD08JU2 MUX FRAMER DSP 5-9974(F) Figure 14. Remote Access Concentrator Application EDGE SWITCH LOW-SPEED NIC ATM SWITCH HIGHSPEED NIC C-ATM CPE N=B SPANS TAAD08JU2 C-ATM C-ATM 5-9975(F) Figure 15. Edge/Access Switch Application 46 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 12 Applications (continued) 12.3 Low-Speed ATM Access In this application, data from a variety of sources are multiplexed into AAL2 using I.366.1 QoS MUXing. I.366.1 pertains only to the AAL type 2 and defines SSCS, CPCS, and SAR services necessary for mapping larger packets (e.g., >64 octets) to/from AAL2 VCs. TAAD08JU2 provides support for I.366.1 concentration to enable ATM transport of a variety of low-speed services. 12.4 AAL2 Cross Connect CID switching is provided by the following architecture. One (west) TAAD08JU2 device terminates an AAL2 VC, demultiplexes CIDs from the CID into AAL0 cells, and routes the AAL0 cells through a space switch fabric to a second (east) TAAD08JU2 device. The east TAAD08JU2 device accepts the AAL0 cells, relates them to specific AAL2 VCs, and maps the SSCS into CIDs and subsequently into an AAL2 VC and onto the physical transmission link. In this fashion, TAAD08JU2 may function as a scalable AAL2 cross connect by expansion in ports and (cell) switching fabric. AAL2 VC_1 CIDs: A, C, B TAAD08JU2 (WEST) (SWITCH FABRIC/ ASE) TAAD08JU2 (EAST) AAL2 VC_3 CIDs: A, E, B AAL2 VC_2 CIDs: E, F, G TAAD08JU2 (WEST) AAL0 VC_E AAL0 VC_F AAL0 VC_G TAAD08JU2 (EAST) AAL2 VC_4 CIDs: F, G, B Note: East CIDs need not match west CIDs. 5-9976(F) Figure 16. AAL2 Cross Connect In a fashion similar to the APC stand-alone ATM switching configuration, TAAD08JU2 may provide a stand-alone AAL2 cross connect, as illustrated in Figure 17. AAL2 V C_1 CIDs: A, C, B TAAD08JU2 AAL2 V C_2 CIDs: E, F, G 5-9977(F) Figure 17. Stand-Alone AAL2 Cross Connect Agere Systems Inc. Agere Systems - Proprietary 47 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 13 Embedded Device Controller (EDC) (continued) 13 Embedded Device Controller (EDC) 13.1 Introduction The embedded device controller is based on an ARM9 RISC architecture. The EDC is responsible for the control functions of TAAD08JU2 and is responsible for configuration, on-chip resource management, and compilation of statistical information for performance monitoring. The EDC also provides alarm correlation among the blocks for faster fault detection and isolation. The EDC enables TAAD08JU2 to be controlled via high-level, simple, device-specific commands issued from the external host device. The commands and associated parameters are converted into a series of register-level transactions for OAMP of blocks within the device. The EDC also decouples host signaling insertion/extraction from the dataflow to enable scheduling of service to the external device. Through the use of embedded application code running on the EDC and APIs running on the external host device, the TAAD08JU2 user achieves faster time to market with a powerful software architecture to control the highly integrated system-on-a-chip device. 13.2 Features ! ! ! ! Enables an abstract command/indication interface to TAAD08JU2. Performs alarm correlation and fault isolation without requiring external host intervention to minimize data loss. Contains all necessary application code to provide its functions. Allows data transfers between the host interface and the APC and SAR blocks to support implementation of OAM functions on the host processor. 13.3 EDC Functional Description The EDC contains an ARMT core and a number of peripherals: ! ! ! ! ! The arbiter and decoder. Interfaces to embedded memories including two 32K x 32 SRAMs. A programmable interrupt controller (PIC). A timer block that provides a watchdog timer and seven additional general-purpose timers. The host controller that can transfer between the ARM bus and its own data buffers. 13.4 Host Interface The host interface controller provides the interface between TAAD08JU2 and a host processor. This interface implements the host signal interface and registers through which the host communicates with TAAD08JU2. The interface also provides the synchronization between the host clock (HCLK) and the chips global clock (GCLK). The host registers are located in the HCLK domain to allow for very fast access reads. The input buffer is also written using this clock. Any other signals that must pass to TAAD08JU2’s global clock are appropriately synchronized. The synchronization scheme allows the global chip clock to be completely independent of HCLK. 48 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 13 Embedded Device Controller (EDC) (continued) 13.5 Host Interface Signals and Timing The host interface mimics the timing of a sync-burst SRAM. All inputs and outputs are timed relative to the rising edge of the host interface clock (HCLK). The data is delayed (by two clock cycles) relative to the corresponding address so that reads and writes have exactly the same timing. This allows the user to easily interleave reads and writes to TAAD08JU2. Another feature of the host interface is the HADV input, which allows the user to autoincrement the previously provided address rather than specifying a new address. This may be useful for users who wish to use the input and output buffers in their linearly addressed mode. HCLK HCEN HADV HA WA1 RA1 RA2 WA2 RA3 HWEN HD(31:0) W1 R1 R2 W2A W2B W2C W2D R3A R3 1417 (F) Figure 18. Standard Host Interface Timing 13.6 Host Interactions The host interface controller has several registers and two data buffers that are used for all external host communication. Addresses are shown per 32-bit word. The host registers are shown in Table 14. Agere Systems Inc. Agere Systems - Proprietary 49 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 13 Embedded Device Controller (EDC) (continued) Table 14. Host Registers Register Name CONF (configuration) HA(9:0) 0x000 Bits 0 1 Reset Description Value 0 SOFT_RESET. Places entire TAAD08JU2 device (except for the host interface) into a reset state. 0 ARM_ENABLE. Allows the embedded ARM processor to come out of reset. This bit should remain 0 until the ARM’s firmware has been loaded. 0 DCLK_RATE. Sets the rate of the clock to the framer, TC, and IMA blocks (called DCLK): 0 = DCLK is equal to GCLK. 1 = DCLK is 1/2 of GCLK. Normally, this bit is sent to 0. 0 DCLK_DISABLE. 1 disables the clock to the framer, TC, and IMA blocks. 0 Reserved; should be set to 0. 0 Reserved. 0 IBRI (input buffer ready interrupt). Becomes active when the host can write to the input buffer and the command register. 0 OBRI (output buffer ready interrupt). Becomes active when the output buffer and/or the indication register has data for the host. 0 Reserved. 0 ASI0 (application-specific interrupt). Becomes active when the ARM sets the register. Application-specific interrupts are reserved for future use by the firmware. 0 ASI1 (application-specific interrupt). Becomes active when the ARM sets the register. 0 Reserved. 0 This register contains the same bits as the interrupt status register, after they have been qualified (ANDed) by the corresponding bits in the interrupt enable register. 0 Each bit in this register is an enable for the corresponding bit in the IS register. The IRQN signal becomes active if the OR of each bit of (IS AND IE) is active. — During a write, a 1 in any data bit will cause the corresponding bit in the interrupt enable register to be set. — During a write, a 1 in any data bit will cause the corresponding bit in the interrupt enable register to be cleared. 0 The host should write commands to this register, which will cause an interrupt to the ARM. 2 3 4 31:5 0 IS (interrupt status) 0x001 1 3:2 4 5 31:6 31:0 QIS (qualified interrupt status) IE (interrupt enable) 0x002 0x003 31:0 IES (interrupt enable set) (write only) IEC (interrupt enable clear) (write only) CMD (command register) 0x004 0x005 31:0 31:0 0x006 31:0 50 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 13 Embedded Device Controller (EDC) (continued) Table 14. Host Registers (continued) Register Name AIB (autoincrement input buffer) HA(9:0) 0x007 Bits 31:0 Reset Description Value 0 This address provides an autoincrementing addressing of the input buffer. This can be used in place of the HADV external signal to write multiple 32-bit words to TAAD08JU2’s host input buffer. The first write to this location (after reset and after the input buffer ready interrupt has been sent) will be equivalent to a write-to location 0x100. Subsequent writes will be to subsequent word addresses. 0 This register is used for downloading EDC firmware to the ARM processor. A write to this register initiates a write transfer from the host buffer to the address specified. The AWP register should be programmed before writing to this location. 0 This register is used for downloading EDC firmware to the ARM processor. ARM processor bus transfer size: specifies amount of data (in words) that should be transferred to the ARM processor bus. 0 Input buffer start location. Starting location (in words) of the input buffer from where the transfer should originate. 0 Reserved. 0 Read-only. The host can read this register to determine how much data is present in the input buffer. This is only updated when the host is writing data and after the entire buffer of data has been transferred out of the buffer. 0 Reserved. 0 Read-only. The host can read this register after the ARM has set the output buffer ready interrupt. 0 Read-only. This location provides an autoincrementing addressing of the output buffer. This can be used in place of the HADV external signal to read multiple 32-bit words from TAAD08JU2’s host output buffer. The first read from this location (after reset and after the output buffer ready interrupt has been set) will be equivalent to a read from location 0x200. Subsequent reads will be from subsequent word addresses. 0 This register is a diagnostic register that allows the host to read back the contents of the ARM processor memories. A write to this register initiates an ARM processor bus read transfer from the ARM processor bus address specified to the host output buffer. The AWP register should be programmed before writing to this location. AWA (ARM processor bus write address) 0x008 31:0 AWP (ARM processor bus write parameters) 0x009 8:0 16:9 31:17 8:0 IBL (input buffer level) 0x00A IR (indication register) AOB (autoincrement output buffer) 0x00B 0x00C 31:9 31:0 31:0 ARA (ARM processor bus read address) 0x00D 31:0 Agere Systems Inc. Agere Systems - Proprietary 51 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 13 Embedded Device Controller (EDC) (continued) Table 14. Host Registers (continued) Register Name ARP (ARM processor bus read parameters) HA(9:0) 0x00E Bits 8:0 Reset Description Value 0 This register is a diagnostic register that allows the host to read back the contents of the ARM processor memories. ARM processor bus transfer size: specifies amount of data (in words) that should be transferred from the ARM processor bus. 0 Output buffer start location. Starting location (in words) of the output buffer to where the transfer should go. 0 Reserved. 0 Read-only. The host can read this register to determine how much data is present in the output buffer. This is only updated after the entire transfer of data into the buffer. 0 Reserved. — ID number + LSB of 1. This field value represents the device version ID. The field value is 0x321 (ID number 0x190) for version 3.1 and 0x03B (ID number 0x01D) for version 2.1. 0x5A94 Part number. X Version number. Varies with each mask set. 0 Reserved; must be set to 0. — Linearly addressed input buffer. — Linearly addressed output buffer. 16:9 31:17 8:0 OBL (output buffer level) 0x00F VR (version register) (This entire 32-bit register provides the same value as the device ID accessible through the JTAG.) BIST_INPUT_BUFFER IB (0:255) (input buffer) OB (0:255) (output buffer) 0x010 31:9 11:0 0x011 0x100— 0x1FF 0x200— 0x2FF 27:12 31:28 31:0 31:0 31:0 52 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block 14.1 Introduction The framer block implements the physical layer function in the ATM protocol stack. The block interfaces with the T1/E1/J1 lines on the line side and the TC block on the system side. It also has a CHI interface for carrying TDM traffic. The block receives and transmits data traffic available from the ATM or TDM interfaces over the physical line. It also receives and transmits data link information over the line. The framer block is a flexible framer engine that enables integration of a feature-rich, yet power-efficient framer function into TAAD08JU2. 14.2 Features ! Framer features: — T1 framing modes: ESF, D4, SLC®-96, T1 DM DDS, SF (FT-only) — E1 framing modes: G.704 basic and CRC-4 multiframe consistent with G.706 — J1 framing modes: JESF (Japan) — E1 signaling modes: • Transparent • Register and system access for entire TS16 multiframe structure per ITU G.732 • Alarm reporting and performance monitoring per AT&T, ANSI, ITU-T, NTT, TTC, and ETSI standards Facility data link features: — HDLC or transparent access for either ESF or DDS+ FDL frame formats — Register/stack access for SLC-96 transmit and receive data — Extended superframe (ESF) — Automatic transmission of the ESF performance report messages (PRM) — Automatic transmission of the ANSI T1.403 ESF performance report messages — Automatic detection and transmission of ANSI T1.403 ESF FDL bit-oriented codes — Register/stack access for all CEPT Sa-bits transmit and receive data Framer interface: — Concentration highway interface: • Single clock and frame sync signals • Programmable clock rates at 2.048 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz • Programmable data rates at 2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s • Programmable clock edges and bit/byte offsets — LIU interface: • Eight T1/E1/J1 channels • Line coding: B8ZS, HDB3, AMI, and CMI (JJ20-11) ! ! Agere Systems Inc. Agere Systems - Proprietary 53 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) 14.3 Framer-to-Line Interface Unit Physical Interface The network interface of the framer consists of eight groups of six connections. The six connections for each framer are LTXNDATA, LTXPDATA, and LTXCLK, driven from the transmit framer (receive path), and LRXPDATA, LRXNDATA, and LRXCLK (transmit path), sourced from the external line interface device. The line interface may operate in single-rail or dual-rail mode. The default mode of the line encoder is single-rail. In this mode, the input signals are passed transparently through the line encoder. In single-rail mode, the link’s framer internal bipolar line encoder/decoder is disabled and monitoring of received line format violation is accomplished with the use of the LRXNDATA input. When LRXNDATA = 1 on the rising edge of LRXCLK, the line format violation counter increments by one. The link’s transmit framer transmits data via the LTXPDATA output pin while LTXNDATA is forced to a 0 state. In dual-rail mode, the internal line encoder/decoder and monitoring are enabled. The line code may be selected from the following choices: ! ! ! Alternate mark inversion (AMI). High-density bipolar of order 3—G.703, A.1 (HDB3). Binary 8 zero code suppression—G.703, A.2 (B8ZS). Line format violations due to excessive zeros will be optionally monitored as follows: ! ! B8ZS—eight consecutive zeros cause a violation. HDB3—four consecutive zeros cause a violation. 14.3.1 Line Interface References/Standards 1. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991. 2. ANSI T1.403-1995, Network-to-Customer Installation—DS1 Metallic Interface, March 21, 1995. 14.3.2 Clocking Modes This section lists all the Tx line clocking modes for framer. ! Mode A1: either all E1s or all T1s running off a single clock (just ATM traffic). In this mode, the CRXCLK input will be used to drive the Tx line clocks. The CRXCLK input can be 1.544 MHz (T1) or 2.048 MHz (E1). Only ATM traffic is supported in this mode. Mode A2: a mix of E1s and T1s—all E1s running off a single clock, all T1s running off another single clock (just ATM traffic). In this mode, a reference 2.048 MHz clock input on CRXCLK is used to feed into a PLL that generates 1.544 MHz and 2.048 MHz. The two clocks will then be selected on a per-link basis to run the line at either E1 or T1 rate. Only ATM traffic is supported in this mode. Mode A3: independent timing—eight independent clock inputs will be used to drive the eight lines (just ATM traffic). In this mode, eight independent (mutually asynchronous) clocks will be input to the framer. These clocks will be used to drive the Tx line clocks for each line (LTXCLK). ! ! Note: In this mode, LTXCLK is an input. Only ATM traffic is supported in this mode. ! Mode A4: loop timing—the Rx line clock will be used to drive the Tx line clocks (just ATM traffic). In this mode, the Rx line clocks (LRXCLK) get internally looped to the Tx line clock (LTXCLK). Only ATM traffic is supported in this mode. Mode B1: either all E1s or all T1s running of a single clock or a mix of E1s and T1s—all E1s running off a single clock, all T1s running off another single clock (ATM plus CHI traffic). In this mode, the receive CHI clock (CRXCLK) is used to feed in to the PLL, which generates a 1.544 MHz clock and a 2.048 MHz clock. These clocks are then selected on a per-link basis to run the line at either E1 or T1 rate. Both ATM and CHI traffic are supported. Agere Systems - Proprietary Agere Systems Inc. ! 54 Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) 14.3.3 Frame Formats The eight framers support the following frame formats: ! ! ! ! ! ! ! ! ! ! DS1 superframe D4. DS1 superframe J-D4 with Japanese Remote Alarm. DS1 superframe DDS. DS1 superframe SLC-96. DS1 extended superframe (ESF). Japanese extended superframe J-ESF (J1 standard with different CRC-6 algorithm). Nonaligned DS1 (transparent 193 bits). CEPT basic frame {ITU G.706}. CEPT CRC-4 multiframe with 100 ms timer (ITU G.706). CEPT CRC-4 multiframe with 400 ms timer (automatic CRC-4/non-CRC-4 equipment interworking) (ITU G.706 Annex B). Nonalign E1 (transparent 256 bits). 2.048 coded mark inversion (CMI) coded interface (TTC Standards JJ-20.11). DS1 superframe (FT bits only). ! ! ! 14.3.4 Transmit Framer Functions ! ! Transmits alarm indication signal (AIS) to the line automatically and on demand. Transmits remote alarm indication (RAI) to the line automatically and on demand. Conditions for transmitting RAI include loss of received-frame alignment, CEPT loss of received-time slot 0 multiframe alignment, CEPT CRC-4 timer expiration, CEPT loss of received-time slot 16 signaling multiframe alignment, CEPT received Sa6 = 8, and received Sa6 = C. Transmits auxiliary test pattern (AUXP) to the line automatically and on demand. Transmits CEPT E bits based received CRC-4 errors. Support the CEPT double not-FAS system mode. Transmits line loopback on and off codes to the line on demand (T1.403 Section 9.3.1). When not in frame alignment, to optionally send AIS or transparently pass data. ! ! ! ! ! 14.4 DS1 Transparent Framing Format The transmit framer can be programmed to transparently transmit 193 bits of CHI data to the line. When configured for transparent framing, the transmit framer extracts bit 8 of time slot 1 from the receive CHI data and inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive system time slot 1 are ignored by the transmit framer. The receive framer will insert every 193rd bit of the receive line data into bit 8 of time slot 1 of the CHI data. The other bits of time slot 1 are set to 0. Frame integrity is maintained in both the transmit and receive framer sections. Agere Systems Inc. Agere Systems - Proprietary 55 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) TIME SLOT 1 TIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32 32 TIME-SLOT CHI FRAME (STUFF TIME SLOT) 0 0 0 0 0 0 0 F BIT F BIT TIME SLOT 1 TIME SLOT 2 TIME SLOT 24 TRAMSMIT FRAMER’S 193-bit FRAME DS1 = 125 µs 5-5989(F).ar.1 Figure 19. DS1 Transparent Frame Structure In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. Bit 8 of time slot 1 of the receive system interface is inserted as the 193rd data bit into the transmit line data. In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of receive line data is performed, and data is passed to the transmit CHI as programmed. The receive framer inserts the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The remaining bits in time slot 1 are set to 0. Bit 8 of time slot 1 of the receive system interface is inserted in the transmit line framing bit position. 14.5 CEPT 2.048 Basic Frame Structure Transparent Framing Format The transmit framer can be programmed to transparently transmit 256 bits of CHI data to the line. The transmit framer must be programmed to transparent framing mode 1. In transparent mode, the transmit framer transmits all 256 bits of the system payload unmodified to the line. Time slot 1 of the CHI interface, determined by the system frame sync signal, is inserted into the FAS/NOTFAS time slot of the transmit line interface. Frame integrity is maintained in both the transmit and receive framer sections. TIME SLOT 1 TIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32 32 TIME-SLOT CHI FRAME TIME SLOT 1 TIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32 32 TIME-SLOT LINE FRAME 5-5988(F) Figure 20. CEPT Transparent Frame Structure 56 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The entire receive line payload is transmitted unmodified to the CHI. In transparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitoring of receive line data is performed, and data is transmitted to the CHI as programmed. 14.6 Receive Framer Nonalignment Mode (DS1/E1) In the nonalign framing modes, the receive frame aligner does not frame to the receive line data. Other than bipolar violations, AIS, and AUXP monitoring, there is no processing of the receive line data. The entire receive line frame is given unmodified to the system interface. 14.6.1 Loss of Frame Alignment Criteria There are two criteria for declaring loss of frame: frame bit errors and CRC errors. 14.6.1.1 Frame Bit Errors ! ! ! ! ! ! ! ! ! ! T1: two frame bit errors out of 4 frame bits (FT and FS bits checked). T1: two frame bit errors out of 5 frame bits (FT and FS bits checked). T1: two frame bit errors out of 6 frame bits (FT and FS bits checked). T1: three frame bit errors out of 12 frame bits—DDS only (FT, FS, and time slot 24 F bits). T1: two frame bit errors out of 4 frame bits (only FT bits checked). T1: two frame bit errors out of 5 frame bits (only FT bits checked). T1: two frame bit errors out of 6 frame bits (only FT bits checked). T1: four frame bit errors out of 12 frame bits—DDS only (FT, FS, and time slot 24 FAS pattern). E1: three consecutive incorrect frame alignment signals. E1: three consecutive incorrect frame alignment signals or three consecutive incorrect non-FAS frames as indicated by bit 2 in time slot 0 in frames not containing the frame alignment signal. E1: three consecutive incorrect FAS or non-FAS frames. 2.048 Mbits/s CMI: two consecutive missing code rule violations (CRVs). ! ! 14.6.1.2 CRC Errors ! The use of CRC errors to declare loss of frame is optional. CRC errors are monitored in the performance monitor block. In DS1 mode, ESF and J-ESF formats only, N or more CRC-6 errors in a 1 second interval results in loss-offrame alignment. N is provisionable. N defaults to 320 in DS1 mode. In CEPT mode, N or more CRC-4 errors in a 1 second interval results in loss-of-frame alignment. N is provisionable. N defaults to 915 in CEPT modes. ! ! 14.7 Frame Alignment Criteria Table 15 describes the frame alignment criteria for the formats supported by the framer. Agere Systems Inc. Agere Systems - Proprietary 57 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) Table 15. Frame Alignment Criteria Frame Format SF D4 and J-D4 DDS SLC-96 Alignment Procedure Frame alignment is established when six consecutive error-free superframes are received. Only the FT framing bits are checked (36 bits checked). Frame alignment is established when six consecutive error-free superframes are received (72 bits checked in D4, 66 bits checked in J-D4). Frame alignment is established when six consecutive error-free frames are received (42 bits checked: FT, FS, and time slot 24). The FT frame position is established when four consecutive error-free superframes are received (24 FT bits checked). After establishing the FT frame position, SLC-96 superframe alignment is established on the first valid FS sequence of 000111000111. All the while, the FT frame position must remain error-free. Frame alignment is established when three consecutive error-free superframes are received (18 bits checked). Uses the strategy outlined in G.706 paragraph 4.1.2. Uses the strategy outlined in G.706 paragraphs 4.1.2 and 4.2. Uses the strategy outlined in G.706 paragraph 4.1.2 and Annex B. Frame alignment is established on the first detection of the CRV violation. Multiframe alignment is achieved the first time the 01111111 multiframe alignment pattern is detected. ESF and J-ESF CEPT Basic Frame CEPT CRC-4 100 ms Timer CEPT CRC-4 400 ms Timer 2.048 Mbits/s CMI Coded Interface 14.8 Performance-Monitoring Functional Integration Into Framer The framer monitors the recovered line data for alarm conditions and errored events. To a lesser degree of importance, the framer also monitors the receive system data when in the switching mode and presents the information to the system through the embedded device controller. In the transport mode, both directions are monitored for alarm conditions and error events. Table 16 shows the functions provided by the performance monitor and establishes the functions’ validity in particular framing modes. 58 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) Table 16. Performance Monitor Functional Descriptions Function 1 2 Description Performance report messages (PRMs) as per G.704 Section 2.1.3.1.3.3, G.963, T1.231 Section 6.3, and T1.403 Section 9.4.2. Provides status for errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds at ET, ET-RE, NT, and NT-RE. Maintains a count of errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds at the ET. Provides a status indication for a loss of signaling frame alignment condition. Provides a status indication for an out-of-frame condition. Provides a status indication for a loss of time slot 0 CRC-4 multiframe alignment. Provides a status indication for a time slot 0 CRC-4 multiframe alignment signal bit error. Provides a status indication for auxiliary pattern detection. Provides a status indication for detection of the DS1 idle signal. Provides a status indication for detection of an alarm indication signal. Provides a status indication for detection of remote alarm indication. Provides a status indication for detection of time slot 16 AIS. Provides a status indication for detection of remote multiframe alarm in time slot 16 (RTS16MFA). Provides a status indication for the loss of CEPT biframe alignment (LBFA). Provides a status indication for detection of remote Japanese yellow alarm (RJYA). Provides a status indication for continuous E-bit reception. Provides a status indication for detection of Sa6 states. Provides a status indication for detection of line format violations. Provides a status indication for detection of frame bit errors. Provides a status indication for detection of CRC errors. Valid Framing Modes for Functions ESF and J-ESF only All modes 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 All modes All modes All modes CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only All modes except CEPT CRC-4 All modes All modes CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only J-D4 only CEPT CRC-4 only CEPT CRC-4 only All modes All modes ESF, J-ESF, and CEPT CRC-4 only Provides a status indication for detection of excessive CRC errors. ESF, J-ESF, and CEPT CRC-4 only Provides a status indication for detection of an E bit equal to 0. CEPT CRC-4 only Provides a status indication for expiration of CRC-4 multiframe CEPT CRC-4 only alignment timer. Provides a status indication for new frame alignment. All modes Provides a status indication for detection of Sa7 link identification CEPT CRC-4 only code. Provides a status indication for detection of an SF line loopback on SF only code. Provides a status indication for detection of an SF line loopback off SF only code. Agere Systems - Proprietary 59 Agere Systems Inc. TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) Table 16. Performance Monitor Functional Descriptions (continued) Function 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Description Provides a status indication for detection of an overflow in the receive elastic store. Provides a status indication for detection of an underflow in the receive elastic store. Provides a status indication for detection of loss of signal. Maintains a count of received CRC errors. Maintains a count of received bipolar violations, line code violations, and excessive zeros. Provides a status indication for detection of a bit-oriented message in the ESF data link bits. Provides a status indication of a test pattern detector lock. Provides a status indication for detection of a test-pattern bit error. Provides a status indication for detection of an ESF-FDL RAI/yellow alarm code. Provides a status indication for detection of the ESF-FDL payload loopback enable code. Provides a status indication for detection of the ESF-FDL payload loopback disable code. Provides a status indication for detection of the ESF-FDL line loopback enable code. Provides a status indication for detection of the ESF-FDL line loopback disable code. Maintains a 16-bit count of received framing bit errors. Maintains a 16-bit count of received E bit = 0 events. Maintains a 16-bit count of received Sa6 = 00x1 events. Maintains a 16-bit count of received Sa6 = 001x events. Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (x, x, AIS). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (0, 1, 1111). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (1, 1, 1111). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (x, x, AUXP). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (1, 1, 1000). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (0, 1, 1000). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (0, 1, 1110). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (0, 1, 1100). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = (1, 0, 0000). Agere Systems - Proprietary Valid Framing Modes for Functions All modes All modes All modes ESF/J-ESF and CEPT CRC-4 only All modes ESF only All modes All modes ESF only ESF only ESF only ESF only ESF only All modes CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only CEPT CRC-4 only 60 Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) Table 16. Performance Monitor Functional Descriptions (continued) Function 54 55 56 Valid Framing Modes for Functions Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = CEPT CRC-4 only (1, 1, 1110). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = CEPT CRC-4 only (1, 1, 00xx). Provides a status indication for detection of an (A, Sa5, Sa6[1:4]) = CEPT CRC-4 only (x, 0, xxxx). Description 14.9 Performance Report Message A performance report message is assembled by the performance monitoring block in the framer. This message can be either sent automatically in the ESF data link or sent as a result of a command. The performance monitor block monitors for errored second events and generates the one-second data for the extended superframe (ESF) performance report message (PRM) (G.704 Section 2.1.3.1.3.3, G.963, T1.231 Section 6.3, and T1.403 Section 9.4.2). The form of the PRM message is shown in Table 17 below. The definition of the fields is given in Table 18. A severely errored frame (SEF) defect is determined by examining contiguous time windows for frame bit errors. In ESF, the window size is 3 ms, and only the frame pattern sequence bits are checked. An SEF defect occurs when two or more frame bit errors in a window are detected. An SEF defect is terminated when the signal is in frame and there are less than two frame bit errors in a window. Table 17. Performance Report Message Format Octet Number 1 2 3 4 5 6 7 8 9 10 11 12 13—14 15 PRM B7 PRM B6 PRM B5 PRM B4 PRM B3 Flag SAPI TEI Control U1 U2 G1 R U1 U2 G1 R U1 U2 G1 R U1 U2 G1 R FCS Flag PRM B2 PRM B1 C/R PRM B0 EA EA G6 NI G6 NI G6 NI G6 NI G3 FE G3 FE G3 FE G3 FE LV SE LV SE LV SE LV SE G4 LB G4 LB G4 LB G4 LB G5 G2 G5 G2 G5 G2 G5 G2 SL Nm SL Nm SL Nm SL Nm Agere Systems Inc. Agere Systems - Proprietary 61 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) . Table 18. Performance Report Message Field Definition Field G1 = 1 G2 = 1 G3 = 1 G4 = 1 G5 = 1 G6 = 1 SE = 1 FE = 1 LV = 1 SL = 1 LB = 1 U1, U2 = 0 R=0 Nm, NI = 00, 01, 10, 11 Definition CRC Error Event = 1 1 < CRC Error Event ≤ 5 5 < CRC Error Event ≤10 10 < CRC Error Event ≤100 100 < CRC Error Event ≤ 319 CRC Error Event ≥ 320 Severely Errored Framing Event ≥ 1 (FE will = 0) Frame Synchronization Bit Error Event ≥ 1 (SE will = 0) Line Code Violation Event ≥ 1 (BPV ≥ 1 or EXZ ≥ 1) Slip Event ≥ 1 Payload Loopback Activated Reserved Reserved (default value = 0) One Second Report Modulo 4 Counter 14.10 ESF Data Link When the framer is in ESF mode, several options are available for use of the 4 kbits/s data link that is part of the SF framing structure. The npSetLineAutoPrmConfig1 device manager API allows for the enabling and disabling of automatic sending of the PRM and the selection of threshold levels for the receive and transmit ESF data link FIFOs from two choices programmed using the npSetDataLinkThresholds. If the PRM is set to be transmitted automatically, then the data link cannot be used for other types of messages. If the automatic PRM is disabled, the ESF data link channel can be used to send bit-oriented messages (BOMs), PRM, and any other data message the user wishes to send. Messages to be sent are specified using the npSendData in the case of non-BOM or the npSetLineAutoBomConfig for BOM. Non-BOM messages can be up to 128 bytes long. Received messages can be generated by npGetData for the host to extract the data. 14.11 Facility Data Link The facility data link is available in SLC-96, DDS and CEPT framing formats. FDL messages are sent using the npSendData and received using the npGetData. 14.11.1 Facility Data Link References/Standards ANSI T1.403-1995-Bit-Oriented Messages (BOM). 1. Device manager function calls throughout this document are indicated by boldface type. 62 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) 14.11.2 Receive Data Link Functional Description This block extracts facility data links bits, as follows: ! ! ! D bits from the SLC-96 multi-superframe. Sa bits from time slot 0 in CEPT basic and CRC-4 multiframes. Data link bits from DDS frames. The respective bits will always be extracted from the framed-aligned receive line payload and stored in the facility data link stack regardless of other configuration bits. All frame types support clear-on-read status and interrupt bits based on the setting of the input select signal. 14.11.3 SLC-96 Superframe Receive Data Link ! Delineates the SLC-96 data link in the Fs signaling frame, extracts the 24 D bits, and stores them in word 1 of npGetData. Provides interrupt for stack ready. Provides host access to stack using processor clock. Supports loss-of-frame status. ! ! ! Both basic frame alignment and multiframe alignment must be established before the data can be assumed valid. 14.11.4 DDS Receive Data Link Stack ! ! ! ! Extracts data link bit (bit 6) from time slot 24 and stores it in words 1 and 2 of npGetData. Provides interrupt via indication processing. Provides host access to stack using npGetData. Supports loss-of-frame status. DDS frames are numbered 1 through 12 with the data link bits located in bit 6 of time slot 24 in every frame. Only basic frame alignment must be established for the data link bits to be extracted. 14.11.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack ! ! ! ! Extracts two multiframes of Sa bits from CEPT links and stores them in words 1 through 3 of npGetData. Supports loss-of-frame status. Provides host access to the stack using npGetData. Provides interrupt via indication processing. CEPT frames are numbered 0 through 15 with the Sa bits located in time slot 0 of the odd numbered frames. The Sa bits can only be extracted from CEPT links when the proper alignment has been established. For basic CEPT frames, the Sa bits will be extracted given the arbitrary alignment selected by the frame aligner block when basic frame alignment is established. For CEPT CRC-4 links the Sa bits will be extracted based on the alignment determined by the frame aligner block when multiframe frame alignment is established. Optionally, the Sa bits will be extracted from CEPT CRC-4 links only after basic frame alignment is established (RxCRCSM). Agere Systems Inc. Agere Systems - Proprietary 63 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) 14.11.6 Receive Data Link Stack Idle Modes ! No data link stack features for the following frame formats: — D4 — J-D4 — ESF — J-ESF — CMI 14.11.7 Transmit Facility Data Link Functional Description This block performs the transmission of D bits into SLC-96 superframes, Sa bits into CEPT multiframes, and datalink bits into DDS frames using npSendData. 14.11.8 SLC-96 Superframe Transmit Data Link ! ! ! Provides for sending D bits and delineator bits on SLC-96 bits via npSendData. Provides interrupt and initiates npGetData process using a Tx threshold. Performs retransmission of stack when update is yet to be performed. The 12 frame SLC-96 superframe is composed of a terminal frame (FT) alternating with a subframe that consists of a combined signaling (FS) frame and data link. The subframe shares establishing the signaling frame (FS) and SLC-96 data link. The FDL stack bits are inserted into the signaling and data link subframe position in the superframe. Seventy-two frames (six superframes) are required to deliver the 24 D bits and 12-bit delineator. The frontend delineator is 00111, which is followed by 24 D bits and trailed by 0001110. The alignment of the FS bits within the superframe is determined and indicated by the frame aligner block. The transmission of the SLC-96 stack will take 9 ms to complete, during which time the host should refill the stack using the npSendData if the D bits need to change. 14.11.9 DDS Transmit Data Link Stack ! ! ! ! Provides for sending three superframes of data link bits via npSendData. Provides interrupt and initiates npGetData process using a Tx threshold. Performs retransmission of stack when update has yet to be performed. Provides host access to stack using npSendData. The transmission of the SLC-96 stack will take 9 ms to complete, during which time the host should refill the stack using the npSendData if the D bits need to change. 14.11.10 Transmit ESF Data Link Bit-Oriented Messages ! Provides capability to transmit bit-oriented messages. When enabled, bit-oriented messages will be transmitted on the data link channel of the frame bit for ESF links. The ESF superframe is numbered 1 through 24 with the data link channel transmitted in the odd numbered frames (4 kbits/s). The BOM is a 16-bit message defining an alarm or command and response action, and sent repeatedly for a period of time determined by the event. The message consists of eight 1s, a 0, a 6-bit code to identify the alarm or action, and a 0 (1111_1111_0 in front and 0 behind the 6-bit code). 64 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) The message can occur at any point in the extended superframe without respect to boundaries. The BOM format is as follows: 0 X X X _ X X X 0 _ 1111_1111 (right-most bit being transmitted first). When the BOM pattern is enabled, it will be transmitted until disabled. When disabled, the pattern will cease to be transmitted immediately. When enabled, the BOMs should only be inserted when the proper alignment has been reached. For ESF links, both BFA and MFA are required for insertion. This condition affects the insertion of BOMs bits and the reporting of stack empty to the host. 14.11.11 CEPT, CEPT Multiframe Transmit Data Link Sa Bits Stack ! ! ! ! Provides two multiframes of Sa-bit storage for transmission on CEPT links. Provides interrupt for stack empty. Performs retransmission of stack when update has yet to be performed. Provides capability to source Sa bits from blocks other than the data link block. This block will always present the Sa bits stored in the Tx stack to the TDM data stream. In CEPT, the Sa bits are located in time slot 0 of the NOTFAS frames (odd-numbered frames). CEPT multiframe format frames are numbered 0 through 15 with the Sa bits located in time slot 0 of the odd-numbered frames (NOTFAS frames). The Sa bits are stored in the Tx stack as follows. Table 19. Shared Tx Stack Format for CEPT Frame Word 0 1 2 3 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA41 SA43 SA45 SA47 SA49 SA411 SA413 SA415 SA41 SA43 SA45 SA47 SA49 SA411 SA413 SA415 SA51 SA53 SA55 SA57 SA59 SA511 SA513 SA515 SA51 SA53 SA55 SA57 SA59 SA511 SA513 SA515 SA61 SA63 SA65 SA67 SA69 SA611 SA613 SA615 SA61 SA63 SA65 SA67 SA69 SA611 SA613 SA615 SA71 SA73 SA75 SA77 SA79 SA711 SA713 SA715 SA71 SA73 SA75 SA77 SA79 SA711 SA713 SA715 SA81 SA83 SA85 SA87 SA89 SA811 SA813 SA815 SA81 SA83 SA85 SA87 SA89 SA811 SA813 SA815 Transmission of the Sa stack will take 4 ms, during which time the host should refill the system stack if the Sa bits need to change. Near the beginning of each CEPT double multiframe, the Tx data link block will determine whether a new set of Sa bits is available to be transmitted. If this is the case, the new Sa bits will be transmitted; otherwise, the previous Sa bits will be retransmitted. When enabled, the Sa bits will only be inserted when the proper alignment has been reached. For CEPT with no CRC-4 links, only biframe alignment (BFA) is required for insertion. For CEPT with CRC-4 links, both biframe alignment (BFA) and CRC-4 multiframe alignment (MFA) are required for insertion for the insertion of Sa bits. Before enabling a link for CEPT format, the host should initialize the stack. If not, the data link block will transmit the reset state of the stack, which is arbitrary. Agere Systems Inc. Agere Systems - Proprietary 65 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) 14.11.12 Transmit Data Link Stack Idle Modes ! ! ! ! D4 J-D4 CMI No data link features 14.11.13 SLC-96, DDS, or CEPT ESF Frame Alignment For CEPT, DDS, or SLC-96 frames, loss-of-frame alignment is not an issue since the framer is the source of timeslot 0 or the F bits. Once a link is enabled, the frame sequence always starts at the beginning. In the case of the system being the source of multiframe alignment, the data link block will simply deliver what is requested. 14.12 Concentration Highway Interface (CHI) The CHI can be programmed to operate at 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz clock rates (data rates up to 8.192 Mbits/s only). A pair of global system clock and system frame sync (one for the transmit and one for the receive direction) are required. The offset between the frame sync and bit 0 of time slot 0 is programmable. This interface can be used, for example, to interface with the Agere TSI devices. 14.12.1 CHI References/Standards 1. ITU G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks. 2. ITU Q.511 Exchange Interfaces Towards Other Exchanges. 14.12.2 Transmit/Receive CHI Features The features supported on the CHI are summarized below: ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Data rates of 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s. Clock rates of 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz. A global input clock and frame sync. Byte offset—2.048 Mbits/s, 0—31 bytes. Byte offset—4.096 Mbits/s, 0—63 bytes. Byte offset—8.192 Mbits/s, 0—127 bytes. Bit offset. 1/2-bit offset. 1/4-bit offset. Clock mode select. Double time-slot mode, CHIDTS. Double NOTFAS system time slot, FRM_DNOTFAS. Sampled clock edge for transmit system frame sync. Global programmable stuffed time-slot position in DS1 mode. Global programmable stuffed byte in DS1 mode. Agere Systems - Proprietary Agere Systems Inc. 66 Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) ! ! ! ! Global single time-slot loopback address for system or line. Programmable automatic system AIS (loss-of-frame alignment). Programmable automatic system AIS (CEPT CRC-4 multiframe alignment timer expiration). On-demand transmission of system AIS. 14.12.3 Double NOTFAS System Time-Slot Mode In the default case (FRM_DNOTFAS = 0), both the FAS and NOTFAS time slots are transmitted by the transmit system interface and expected by the receive system interface. Setting FRM_DNOTFAS to 1 enables the NOTFAS time slot to be transmitted twice on the transmit system interface in the NOTFAS and FAS time-slot (TS0) positions. Similarly, the receive system interface assumes time slot 0 to carry NOTFAS data that is repeated twice. 14.12.4 Transparent Mode In the transparent DS1 mode, the transmit system interface inserts the 193rd bit of the DS1 frame in bit 7 (LSB) of the first stuffed time slot. The receive system interface takes bit 7 of the first stuffed time slot and inserts it into the framing bit position (193rd bit on the TDM data bus). In the transparent E1 mode, the transmit system maps 32 received time slots into the CHI time slots. Similarly, the receive system maps the CHI time slots into the TDM bus time slots. The transmit frame formatter inserts TS0 of the CHI (FAS/NOTFAS) into the TS0 of the frame based on the biframe alignment. 14.12.5 Loopbacks Two forms of loopbacks are supported: single time-slot system loopback and single time-slot line loopback, as shown in Figure 21. When in single time-slot system loopback, a single time slot from the receive system interface is looped back to the system. An idle code is transmitted to the line in place of the looped-back time slot. When in single time-slot line loopback, a single time slot from the transmit system interface is looped back to the line. The programmable idle code is transmitted to the system in place of the looped-back time slot. LINE ES SYSTEM SINGLE TIME-SLOT SYSTEM LOOPBACK LINE ES SYSTEM SINGLE TIME-SLOT LINE LOOPBACK ES = ELASTIC STORE 5-9030(F)r.1 Figure 21. System Loopbacks Agere Systems Inc. Agere Systems - Proprietary 67 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 14 Framer Block (continued) 14.12.6 Nominal CHI Timing Figure 22 illustrates nominal CHI frame timing. Double time-slot mode (CHIDTS) is disabled. The frames are 125 µs long and consist of 32 contiguous time slots when the 2.048 MHz data rate mode is selected. In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots. In CEPT frame modes, the CHI frame consists of 32 payload time slots. ! ! ! ! CTXDATA: output data to system. CRXDATA: input data to system. CTXFS: transmit CHI frame sync. CRXFS: receive CHI frame sync. 125 µs CTXFS/ CRXFS DS1 FORMAT 2.048 Mbits/s CHI: CTXDATA 1 STUFFED SLOT CRXDATA CEPT FORMAT 2.048 Mbits/s CHI: 32 VALID TIME SLOTS CTXDATA or CRXDATA FRAME 1 FRAME 2 24 VALID TIME SLOTS FRAME 1 24 VALID TIME SLOTS 7 STUFFED SLOTS* FRAME 2 FRAME 2 4.096 Mbits/s CHI: CTXDATA FRAME 1 HIGH IMPEDANCE FRAME 2 CRXDATA FRAME 1 FRAME 2 8.192 Mbits/s CHI: FRAME 1 HIGH IMPEDANCE FRAME 2 CTXDATA CRXDATA FRAME 1 FRAME 2 5-8978(F) * The position of the stuffed time is controlled by register bit FRM_STUFFL. FRM_STUFF = 1 is shown. Figure 22. Nominal Concentration Highway Interface Timing 68 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 14 Framer Block (continued) 14.12.7 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled Figure 23 illustrates the CHI frame timing when CHIDTS is enabled. In the CHIDTS mode, valid CHI payload time slots are alternated with high-impedance intervals of one time-slot duration. This mode is valid only for 4.096 Mbits/s and 8.192 Mbits/s CHI data transfer rates. 125 µs CTXFS/ CRXFS 4.096 Mbits/s CHI TIME TIME SLOT SLOT CTXDATA TS0 8 bits CRXDATA TS0 FRAME 1 FRAME 2 TS1 TS2 TS3 TS4 TS30 TS31 TS0 TS1 TS2 TS3 TS4 T30 TS31 TS0 8.192 Mbits/s CHI CTXDATA TS0 TS1 TS2 TS30 TS31 HIGH IMPEDANCE TS0 CRXDATA TS0 TS1 TS2 TS30 TS31 TS0 5-8979(F) Figure 23. CHIDTS Mode Concentration Highway Interface Timing 14.12.8 Clocking Scheme LTXCLK—Line Transmit Clock. This can be either input or output. When programmed as output, it is used to generate line clock for each tx line. The clock source for this clock is either the LRXCLK when lines are set in Rx CLK loop mode, or the CRXCLK pin. When programmed as input, the system designer must provide the Tx line clocks to . It is assumed that these clocks will also drive the Tx LIUs. Typically, LTXCLK is set as an input to implement independent transmit clock (ITC) mode. This pin either inputs or outputs 1.544 MHz or 2.048 MHz. CRXCLK—CHI Receive Clock. This pin is an input, but also has multiple functions as listed below: ! It can be set up as a CHI clock in which 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz can be applied. In this case, transmit clock must be generated either by line Rx clock in loop timing mode, or LTXCLK in input mode. This pin can also be set to REF2M048 mode. In this mode, a fixed 2.048 MHz is applied and generates both 1.544 MHz and 2.048 MHz clocks that drive the various framer ports based on user-programmed setup. This pin can be set as a common transmit clock (CTC) for all lines. In this mode, this pin could have 1.544 MHz or 2.048 MHz, and this will be the clock reference for all eight lines. ! The LRXCLK and the CTXCLK each have the one function as defined in the pinout. Agere Systems Inc. Agere Systems - Proprietary 69 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 15 Transmission Convergence (TC) Block 15.1 Introduction The transmission convergence (TC) block provides the cell delineation function and physical layer mapping of ATM cells to/from the PHY link. In the receive direction, the TC receives cells as a byte-aligned payload from the framer. The TC locates the ATM cell boundary via the common I.432-based cell delineation technique. The TC then passes ATM cells to the ATM layer for subsequent processing and routing. In the transmit direction, the TC receives cells from the ATM layer via an internal UTOPIA-2 MPHY interconnection. The TC inserts a correct HEC in the ATM cell header and maps the cell in a byte-aligned fashion into a data stream toward the framer. If the link is configured for ATM UNI mode, the TC performs cell rate decoupling between the physical layer and the ATM layer by discarding idle cells in the receive direction and by inserting idle cells in the transmit direction. The TC also discards ATM cells with uncorrectable HEC errors. If the link is configured for ATM IMA mode, the TC does not discard any cells for rate decoupling. ATM cells with a bad header are discarded and an indication is provided to the IMA sublayer in order to preserve IMA frame synchronization. 15.2 Features ! ! ! ! ! ! ! ! ! ! ! ! ! Supports up to eight PHY channels. Provides cell delineation per ITU I.432. ATM UNI mode support for idle cell discard. ATM IMA mode support by detecting and/or discarding errored cells. Performs ATM cell HEC checking in the receive direction. Optional support for error detect/correct mode. Performs ATM cell HEC generation in the transmit direction. Optional support for x55 coset addition to ATM header. Optional support for cell payload scrambling. Supports TC onto T1, E1, and J1 PHY links. Supports fractional ATM logical channels on T1, E1, and J1 links. Mapping of ATM cells onto DS1 per direct mapping scheme of G.804. Mapping of ATM cells onto E1 per G.704 and G.804. 70 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 15 Transmission Convergence (TC) Block (continued) 15.3 TC—Receive Direction The receive section consists of the following blocks: ! Receive line interface. This block interfaces to the framer. It determines which channel is to be processed next and provides the receive cell delineator with the data word to process. Receive cell delineator. This block implements the cell delineation state machine and generates the loss of cell delineation event. Receive cell processor. This block implements the header error control state machine, includes a self-synchronizing descrambler, and writes passed (unfiltered) cells into the receive data buffer. Transmit IMA interface. This implements the interface to the IMA block. Cell data is written into the transmit data buffer from the IMA block. Receive IMA interface. This block implements the interface to the IMA block. Cell data is read from the receive data buffer and output to the IMA block from this interface. Parity is generated for each byte read out of the receive data buffer. Receive line side context RAM. This block, indexed by the channel number from the receive line interface block, stores the state variables (generated on the line clock) for the receive cell delineator, receive processor, and receive buffer manager. Receive UTOPIA side context RAM. This block, which is indexed by the port number from the receive UTOPIA slave interface block, stores the state variables (generated on the UTOPIA clock) for the buffer manager. Receive data buffer. This block stores received ATM cells together with the start-of-cell (SOC) signal. ! ! ! ! ! ! ! 15.4 TC—Transmit Direction The transmit section consists of the following blocks: ! Transmit line interface. This block interfaces to the framer; it determines which channel is to be processed next and gets the data from the transmit cell processor. Transmit cell processor. This block reads cells from the transmit data buffer and performs the payload scrambling and HEC generation. If no cells are available in the buffer, the transmit cell processor generates idle cells. Transmit buffer manager. This block manages the read and write pointers for each channel (which are generated on separate clocks), as well as the various FIFO flags. Transmit UTOPIA slave interface. This block implements the MPHY transmit UTOPIA-2 interface. Cell data and the SOC bit from the UTOPIA interface are written into the transmit data buffer and output on the UTOPIA interface. Parity is checked for each byte input from the UTOPIA interface. Transmit line-side context RAM. This block, which is indexed by the channel number from the transmit line interface block, stores the state variables (generated on the line clock) for the transmit cell processor and buffer manager. Transmit UTOPIA side context RAM. This block, which is indexed by the port number from the transmit UTOPIA slave interface block, stores the state variables (generated on the UTOPIA clock) for the buffer manager. Transmit data buffer. This block stores transmit ATM cells together with the start-of-cell (SOC) signal. ! ! ! ! ! ! Agere Systems Inc. Agere Systems - Proprietary 71 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 15 Transmission Convergence (TC) Block (continued) 15.4.1 HEC Generation/Checking The HEC octet is generated in the transmit direction by calculating a CRC with the polynomial x8 + x2 + x + 1 over the first four header octets and then adding the coset 01010101. In the receive direction, the HEC is checked by calculating the CRC according to the above method on the received header octets and subsequently adding the received HEC. The syndrome thus generated is equal to 0 if no errors are in the header. The CRC provides the capability of single error correction and multiple error detection. The error control mechanism can be in one of two states: correction or detection. When an error occurs, a cell may be corrected or discarded depending on the state of operation. 15.5 Cell Delineation Cell delineation means finding the cell boundaries in a cell stream with a good degree of confidence. The TC implements HEC-based cell delineation. Initially, the cell delineation state machine is in hunt. When a correct HEC is found, it is assumed that a candidate cell delineation is found and the state machine goes to presync. In presync, if an incorrect HEC occurs, the hunt state is resumed. Otherwise, if delta (normally = 6) consecutive correct HECs occur, it is assumed that the cell delineation is correct and the state machine goes to the sync state. The state machine remains in sync unless alpha (normally = 7) consecutive incorrect HECs are found—in which case the state machine goes back to the hunt state. 15.6 Cell Payload Scrambling/Descrambling In the transmit direction, each cell payload is scrambled by a self-synchronizing scrambler using the polynomial x43 + 1. Cell payloads are scrambled in order to avoid repeating fixed bit patterns and improve the robustness of the cell delineation algorithm. In the receive direction, the cell payload is descrambled by a descrambler using the same polynomial (x43 + 1). The descrambler is only active when the cell delineation state machine is in presync or sync. 15.7 Cell Mapping The direct cell mapping method is used with most line framing formats. In this method, cells are octet aligned (with respect to the line framing and overhead) and consecutive with no gaps between cells. 15.8 Facility Maintenance Two maintenance functions are defined: detection of the out-of-cell delineation (OCD) condition and detection of the loss-of-cell delineation (LCD) condition. OCD is declared when hunt state is entered and it is cleared when sync state is entered. ! LCD is declared when OCD persists continuously for a time greater than that set in a programmable timer. The timer can be programmed for up to 1 s. The default timer setting is 4 ms. LCD is cleared when OCD is cleared continuously for the same programmed time. 72 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 15 Transmission Convergence (TC) Block (continued) 15.9 Cell Rate Decoupling Cell rate decoupling, in the transmit direction, means inserting idle or unassigned cells to keep the cell stream continuous when no other cells are available for transmission. In the receive direction, it means discarding idle, unassigned, or invalid cells. These types of cells are defined in Table 20. Cell rate decoupling is a physical layer function according to the International Telecommunication Union (ITU) I.432 standard and an ATM layer function according to the ATM Forum's User-Network Interface (UNI) Specification Version 3.1*. * When transmitting idle or unassigned cells, the correct HEC must be generated. In addition, I.432 requires that the payload of an idle cell be 48 octets equal to 01101010. Table 20. Cell Headers of Idle, Unassigned, and Invalid Cells Cell Type Cell Header Definition Idle (ITU I.432) 00000000 00000000 00000000 00000001 Unassigned (ATM Forum UNI 3.1) 00000000 00000000 00000000 0000XXX0 Invalid (ATM Forum UNI 3.1) XXXX0000 00000000 00000000 0000XXX1 Note: X means don't care. 15.10 Functionality Table 21 lists the functions and requirements met by the TC block. . Table 21. TC Functionality Function HEC Generation/ Verification Subfunction Error detection Error correction Specification Multiple-bit, cell optionally discarded. Single-bit, cell header corrected and accepted if in correction mode. Cell discarded if in detection mode. x8 + x2 + x + 1. 01010101. Programmable on/off. ATMF and ITU state diagram. dequeue. DR: Data Direction. 0 => ingress, 1 => egress. ST: Status. 0 => successful enqueue/dequeue operation. 1 => operation not successful. Packet Length: SDU length of enqueued data unit. The dequeue operation reports PDU length for AAL5 and NPAAL and CPS packet length for AAL2. See page 153 for a functional timing diagram. 116 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) 18.4.18.2 ESI Violation Code The status and violation code field in the ESI message is coded as shown in Table 26. Possible violation codes for ingress and egress are identical, distinguished by the DR field. Table 26. ESI Violation Codings SQ ST 0 0 0 1 Operation Enqueue Success Enqueue Failure Violation Code Reserved 000001 1 Description Operation Successful. Connection Queue Error. Intralevel 1 Queue Error. Level 1 Queue Error. Intralevel 2 Queue Error. Level 2 Queue Error. Enqueue Subpacket Error. Exception #11. See Table 34. Exception #12. See Table 34. Exception #13. See Table 34. Exception #14. See Table 34. Exception #15. See Table 34. Exception #16. See Table 34. Exception #17. See Table 34. Exception #18. See Table 34. Exception #24. See Section 18.4.18.3 and Table 34. Exception #25. See Table 34. Operation Successful. Dequeue Packet Abort 2. 0000101 0000111 000100 1 0001011 0001101 101011 1 1011001 1011011 101110 1 1011111 1100001 110001 1 1100101 1110001 111001 1 1 0 1 Dequeue Success Dequeue Failure 1 Reserved Reserved 1. Reserved for silicon revisions prior to TAAD08JU2 2K V2.0 (revision register 0000 0011). 2. SIF packet mode only. 18.4.18.3 ESI Packet Length The packet length reported in the ESI message is defined in Note 5 of Table 25. In this case, because the SAR could not allocate an L0Q descriptor, there is no ability to report length information to the ESI. For a frame-based service that fails to get an L0Q, multiple ESI messages are reported per frame. In all other cases, just one message is reported, and the packet length is the SDU length. 18.4.19 Service Types Sourced VCs are configured with an AAL type. Sourced flows are configured with a service type. Table 27 defines permissible service types for the AAL types. Service types are described in the following sections. Agere Systems Inc. Agere Systems - Proprietary 117 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 18 ATM Adaptation Layer (AAL) Block (continued) Table 27. AAL Type vs. Service Type Compatibility AAL Type Service Type CPS_SERVICE SEG_AAL2_SSSAR_SERVICE SEG_AAL2_SSTED_SERVICE SEG_AAL5_SERVICE TRANSPARENT_SERVICE REASS_AAL2_SSSAR_SERVICE REASS_AAL2_SSTED_SERVICE REASS_AAL5_SERVICE AAL0 Invalid Invalid Invalid Invalid Valid Invalid Invalid Invalid AAL2 Valid Invalid Invalid Invalid Invalid Valid Valid Invalid CPS-AAL0 Valid Invalid Invalid Invalid Invalid Valid Valid Invalid AAL5 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Valid NPAAL Invalid Valid Valid Valid Valid Invalid Invalid Invalid Figure 50 shows an example of how an HPF packet is read/written from the host interface. In this example, the packet has a length of 62 bytes. WRITES 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1ST 2ND 3RD D R VPI LEN VCI ICD (NOTE) DATA—byte 2 DATA—byte 3 PTI LP DATA—byte 1 DATA—byte 4 18TH DATA—byte 61 DATA—byte 62 UUI 1941 (F) Figure 50. Transferring an HPF Packet over the Host Interface Example Note: When reading an HPF packet from the host, this field will contain the ICID from the AAL engine. When writing an HPF packet to the host, this field is ignored. 18.4.20 CPS_SERVICE CPS_SERVICE offers a CPS layer segmentation and reassembly process. Management and reserved UUI codepoints are observed, but no attempt is made to perform any SEG-SSCS (segmentation service specific convergence sublayer) related functions. CPS_SERVICE may be selected for processing of received AAL2 cells destined for cell-based interfaces. CPS_SERVICE may also be selected for flows destined for the host. Data units requiring CPS_SERVICE are configured to use static L0Qs (see Section 18.5.4.5 ). 118 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) 18.4.21 SEG_AAL2_SSSAR_SERVICE SEG_AAL2_SSSAR_SERVICE represents the SSSAR segmentation process defined in ITU-T Recommendation I.366.1, Segmentation and Reassembly Service Specific Convergence Sublayer for the AAL Type 2. Data units requiring the SEG_AAL2_SSSAR_SERVICE may be sourced from a packet-based SIF, the host, or the adaptation loopback path. Connections using SEG_AAL2_SSSAR_SERVICE are configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). Connections using SEG_AAL2_SSSAR_SERVICE may be configured to operate in streaming mode with or without partial packet discard (PPD) behavior. Management or reserved data units received on message mode connections using SEG_AAL2_SSSAR_SERVICE, as defined in ITU-T Recommendation I.366.2, AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services, may be redirected to the processor. 18.4.22 SEG_AAL2_SSTED_SERVICE SEG_AAL2_SSTED_SERVICE represents the SSTED segmentation process defined in ITU-T Recommendation I.366.1, Segmentation and Reassembly Service Specific Convergence Sublayer for the AAL Type 2. The SEG_AAL2_SSTED_SERVICE incorporates the SSSAR SSCS. Data units requiring the SEG_AAL2_SSTED_SERVICE may be sourced from a packet-based SIF, the host, or the adaptation loopback path. Connections using SEG_AAL2_SSTED_SERVICE are configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). Connections using SEG_AAL2_SSTED_SERVICE may be configured to operate in streaming mode with or without PPD behavior. Management or reserved data units received on message mode connections using SEG_AAL2_SSTED_SERVICE, as defined in ITU-T Recommendation I.366.2, AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services, may be redirected to the processor. 18.4.23 SEG_AAL5_SERVICE SEG_AAL5_SERVICE represents the AAL5 segmentation process defined in ITU-T Recommendation I.363.5, BISDN ATM Adaptation Layer Specification: Type 5 AAL. Data units requiring the SEG_AAL5_SERVICE may be sourced from a packet-based SIF, the host, or the adaptation loopback path. Connections using SEG_AAL5_SERVICE are configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). Connections using SEG_AAL5_SERVICE may be configured to operate in streaming mode with or without PPD behavior. Agere Systems Inc. Agere Systems - Proprietary 119 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 18 ATM Adaptation Layer (AAL) Block (continued) 18.4.24 TRANSPARENT_SERVICE The transparent service provides no adaptation-layer processing. In-band indications received on connections (UUI, PTI) that use this service are propagated but otherwise ignored. No accumulation of multiple data units or segmentation of a data unit occurs. For appropriately sized data units, this service may be used to transfer cells transparently between the NIF and a cell based SIF. The host may inject datagrams destined for a packet-based SIF using this service. Data units requiring TRANSPARENT_SERVICE will typically be configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). 18.4.25 REASS_AAL2_SSSAR_SERVICE REASS_AAL2_SSSAR_SERVICE represents the SSSAR reassembly process defined in ITU-T Recommendation I.366.1, Segmentation and Reassembly Service Specific Convergence Sublayer for the AAL Type 2. Data units requiring the REASS_AAL2_SSSAR_SERVICE may be sourced from a cell-based SIF or the NIF. Connections using REASS_AAL2_SSSAR_SERVICE are configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). Connections using REASS_AAL2_SSSAR_SERVICE may be configured to operate in streaming mode with or without PPD behavior. Management or reserved data units received on message mode connections using REASS_AAL2_SSSAR_SERVICE, as defined in ITU-T Recommendation I.366.2, AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services, may be redirected to the processor. 18.4.26 REASS_AAL2_SSTED_SERVICE REASS_AAL2_SSTED_SERVICE represents the SSTED reassembly process defined in ITU-T Recommendation I.366.2, AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services. The REASS_AAL2_SSTED_SERVICE incorporates the SSSAR SSCS. Data units requiring the REASS_AAL2_SSTED_SERVICE may be sourced from a cell-based SIF or the NIF. Connections using REASS_AAL2_SSTED_SERVICE are configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). Connections using REASS_AAL2_SSTED_SERVICE may be configured to operate in streaming mode with or without PPD behavior. Management or reserved data units received on message mode connections using REASS_AAL2_SSTED_SERVICE, as defined in ITU-T Recommendation I.366.2, AAL Type 2 Service Specific Convergence Sublayer for Narrow-Band Services may be redirected to the processor. 18.4.27 REASS_AAL5_SERVICE REASS_AAL5_SERVICE represents the AAL5 reassembly process defined in ITU-T Recommendation I.363.5, BISDN ATM Adaptation Layer Specification: Type 5 AAL. Data units requiring the REASS_AAL5_SERVICE may be sourced from a cell-based SIF or the NIF. Connections using REASS_AAL5_SERVICE are configured to use dynamic L0Qs (Section 18.5.4.5 on page 129). Connections using REASS_AAL5_SERVICE may be configured to operate in streaming mode with or without PPD behavior. 120 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) Table 28. Transport of Congestion Indication and Loss Priority Source Service AAL0 AAL0 dst.LP = src.LP dst.PTI = src.PTI CPS — Destination Service SSSAR SSTED — — AAL5 — NPAAL CPS SSSAR SSTED AAL5 NPAAL dst.UUI = 0 dst.LP = src.LP dst.PTI = src.PTI — dst.UUI = src.UUI — — — dst.UUI = src.UUI dst.LP = 0 dst.PTI = 1 — — — — — dst.UUI = src.UUI1 dst.LP = 0 dst.PTI = 0/12 — — — — — dst.UUI = src.UUI3 dst.LP = src.LP4 dst.PTI = 0/1/2/35 — — — — — dst.UUI = src.UUI6 dst.LP = src.LP7 dst.PTI = 0/1/2/38 dst.LP = src.LP dst.UUI = dst.UUI = src.UUI dst.UUI = src.UUI dst.UUI = src.UUI dst.UUI = src.UUI dst.PTI = src.PTI src.UUI9 dst.LP = src.LP10 dst.LP = src.LP12 dst.LP = src.LP14 dst.CI = src.CI11 dst.PTI = 0,1,2,313 dst.PTI = 0/1/2/315 1. 2. 3. 4. 5. As derived from the final CPS packet comprising the SSSAR PDU (valid on the final IDU of an SSSAR-PDU only). According to streaming status, note that CI portion of the PTI is always clear. As derived from the SSTED trailer UUI field (valid on the final IDU of an NPAAL-PDU only). As derived from the SSTED trailer CPI LP field (valid on the final IDU of an NPAAL-PDU only). According to streaming status, note that CI portion of the PTI is derived from the SSTED trailer CPI CI field (CI is valid on the final IDU of an NPAAL-PDU only). 6. As derived from the CPCS trailer UUI field (valid on the final IDU of a NPAAL-PDU only). 7. As derived from a rolling OR of the current loss priority and the received loss priority of each cell comprising an AAL5 PDU. 8. According to streaming status, note that CI portion of the PTI is derived from the PTI of the cell immediately prior to a streaming/message mode packet operation. 9. The CPS packet UUI is a truncated version of the NPAAL UUI. 10. As derived from a rolling OR of the current loss priority and the received loss priority of each IDU comprising an NPAAL PDU. 11. As derived from the received congestion indication of the last IDU comprising an NPAAL PDU. 12. As derived from a rolling OR of the current loss priority and the received loss priority of each IDU comprising an NPAAL PDU. 13. According to streaming status, note that CI portion of the PTI is derived from the PTI of the final IDU prior to a streaming/message mode packet operation. 14. As derived from a rolling OR of the current loss priority and the received loss priority of each IDU comprising an NPAAL PDU. 15. According to streaming status, note that CI portion of the PTI is derived from the PTI of the final IDU prior to a streaming/message mode packet operation. Agere Systems Inc. Agere Systems - Proprietary 121 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 18 ATM Adaptation Layer (AAL) Block (continued) 18.5 Provisioning Resources within the SAR must be allocated before flows can be configured. This is termed provisioning. Provisioning is static: it is expected to be done once, before connections are set up. Provisioning is done from the source to the destination—the direction of the datapath. Source provisioning is performed first to allocate resources to reflect an expected mix of AAL types, VC ranges, etc., as they will appear at the source ports. Within the SAR, queueing and scheduling resources are then provisioned to provide desired levels of QoS. Finally, destination provisioning is performed to compose outgoing AAL types, and map flows to outgoing ports, VCs, and CIDs. This data sheet refers to a sourced AAL2 VC, for instance, to describe AAL2 adapted ATM cells at the source interface, as distinct from an AAL2 VC being composed for a destination interface. 18.5.1 Some Notes on Terminology and Command Referencing Provisioning is described in terms of the firmware commands issued to perform it. All commands begin with the NPT string. The firmware commands mentioned in Section 18.5.1 through Section 18.5.4.6 are implemented by the initialization of the AAL in the device manager and the setup file utility. Just as SAR datapaths for ingress and egress are very symmetric, there exist many command pairs: one for ingress, one for egress. Such pairs are occasionally identified with a composite term, e.g., NPT_AAL_NIF(SIF)_TRANSMIT(RECEIVE)_CONFIG instead of NPT_AAL_NIF_TRANSMIT_CONFIG/ NPT_AAL_SIF_RECEIVE_CONFIG. 18.5.2 System Interface The system interface block (SIF) will allow the SAR engine to communicate with the external systems in two different ways: ! ! UTOPIA cell mode (UT2) Enhanced UTOPIA packet mode (UT2+) Both interfaces support a maximum of 31 MPHYs. Upon configuration, all MPHYs work in one and only one selected mode. Packet and cell mode may be run as an 8-bit or 16-bit data bus interface (software selectable). Either of the data bus widths can be run at speeds between 25 MHz and 50 MHz. The SIF is a UTOPIA master. When operating in cell mode, the SIF does not support octet-level handshake. The SIF supports an octet-level flow control in packet mode. 122 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) In egress direction, the SIF throttles data from the SAR on different MPHYs using the DUAV(30:0) (data unit available) signal. In ingress direction, the SAR will use a single DUAV signal to backpressure data from the SIF. 18.5.3 Port Table A port table exists for both the ECA and ISIA. For either block, there is a table entry for each port, where a port is one of the following: a PHY from the interface (SIF or NIF), the management port (the host), or the loopback port (for adaptation loopback—ISIA only). Figure 51 illustrates the port table fields relevant to provisioning. PORT TABLE 0 1 2 PortIndex . . . M–1 [NOTE 1] VCIMinOffset VCIMaxOffset NumAal2VCs VPI Note: For ECA, M = 5. For ISIA, M = 33. 1648 (F) Figure 51. Port Table The port table is indexed by the PortIndex. The NPT_AAL_NIF_TRANSMIT_CONFIG(PortIndex) in each NPT_AAL_NIF_TRANSMIT_CONFIG command word is mapped to an ECA port. The NPT_AAL_SIF_RECEIVE_CONFIG(PortIndex) in each command word is mapped to an ISIA port, as shown in Table 29. Table 29. PortIndex to Enqueue Block Port Mapping PortIndex 0 1 2 3 4 5 6—30 31 32 ECA Port PHY[UtopiaStrtAdd] PHY[UtopiaStrtAdd+1] PHY[UtopiaStrtAdd+2] PHY[UtopiaStrtAdd+3] Management Port NA NA NA NA ISIA Port PHY[0] PHY[1] PHY[2] PHY[3] PHY[4] PHY[5] PHY[6-30] Management Port Loopback Port Note that NPT_AAL_SIF_RECEIVE_CONFIG(PortIndex) = [0—30] is hard-mapped to an ISIA PHY, whereas NPT_AAL_NIF_TRANSMIT_CONFIG(PortIndex) = [0—3] is hard-mapped to a normalized PHY, reflecting the fact that NIF Tx PHYs may begin at any multiple of 4 within [0, 4, 8, 12, 16, 20, 24, 28], as indicated by NPT_AAL_NIF_TRANSMIT_CONFIG(UtopiaStrtAdd). The VPI is set by programming VPI and PortIndex appropriately within each even word of NPT_AAL_NIF(SIF)_TRANSMIT(RECEIVE)_CONFIG. Note that the VPI is fixed per port. Data units sourced with a VPI other than NPT_AAL_NIF(SIF)_TRANSMIT(RECEIVE)_CONFIG(VPI) are discarded with an exception. Agere Systems Inc. Agere Systems - Proprietary 123 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 18 ATM Adaptation Layer (AAL) Block (continued) Since the VPI is fixed per port, flow identification at the source is referred to as {port, VCI, (CID)}. The total number of VCs sourced on the PortIndex is VCIMaxOffset-VCIMinOffset+1, and the VCIs begin at VCIMinOffset. NumAal2VCs is the number of AAL2 VCs on the PortIndex, where AAL2 VCs must begin at VCIMinOffset, and must fall within a contiguous range. This is discussed further in Section 18.5.4. 18.5.4 MEMI Shared Memory The SAR contains two large memories, each of which contains multiple resources (tables or state). These memories are the adaptation blocks shared memory (MEMI-SM) and the SQASE shared memory (SQASE-SM). The number of resources in each memory is fixed, but the memory allocation given to the resources is programmable. MEMI-SM is a 9K deep (0x2400 entries) memory. Each entry is 64 bits wide. MEMI-SM contains resources as listed in Table 30. Resources have different widths and are packed into MEMI-SM as efficiently as possible. This is illustrated by the width indicator in Table 30. The impact of packing on the user is explained on a case-by-case basis. Table 30. MEMI-SM Resources SAR Subblock ISIA ISIA ISIA ISIA ISIA ECA ECA ECA ECA ECA Resource Name VC Table AAL2 VC Table Connection Table Level 0 Queue Descriptor SSTED Trailer VC Table AAL2 VC Table Connection Table/Descriptor Level 0 Queue Descriptor SSTED Trailer Pipe2 Pipe2 Width Indicator1 2 2 1 0.5 1 2 2 1 0.5 1 2 Description Section 18.5.4.2 on page 125. Section 18.5.4.3 on page 126. Section 18.5.4.4 on page 127. Section 18.5.4.5 on page 129. State for sourced AAL2-SSTED VCs. Section 18.5.4.2 on page 125. Section 18.5.4.3 on page 126. Section 18.5.4.4 on page 127. Section 18.5.4.5 on page 129. State for sourced AAL2-SSTED VCs. Section 18.5.4.6 on page 129. Default #Entries3 Base 0x00 0x400 0x420 0xC20 0xD20 0x1560 0x1960 0x1980 0x2160 0x2260 0xD60 2048 64 2048 128 64 2048 64 2048 128 4164 4096 ICA & ESIA Dequeue Adaptation Table 1. Indicates for each resource the number of resource entries that fit into each MEMI-SM entry. 0.5 indicates that 2 MEMI-SM entries are required for each resource entry. 2. An SSTED trailer pipe entry is required for each allocated dynamic L0Q. 3. The number of entries is the number of resource indices available within the default allocated region, not the number of memory words. 4. MEMI-SM is 9K deep: 0x2400—0x2260 = 0x1a0 = (decimal) 416. Strictly, the SSTED trailer pipe needs to be no larger than the number of allocated dynamic L0Qs. The command NPT_AAL_ADAPBLK_MEM_ALLC is executed once to provision MEMI-SM. There are a number of constraints regarding MEMI-SM provisioning, as listed below. See Section 18.5.4.2 through Section 18.5.4.6 for explanations. 124 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) 18.5.4.1 MEMI-SM Provisioning Constraints ! ! ! ! NifVcCnt + SifVcCnt may not exceed the overall user flow limit of 4064. The AAL2 VCs within a port are constrained to occupy the lowermost VC table addresses. Neither NifAal2VcCnt nor SifAal2VcCnt may exceed the per-direction AAL2 VC limit of 64. NifVcPlusChanCnt + SifVcPlusChanCnt may not exceed the overall user flow limit of 4064. 18.5.4.2 VC Table The VC table contains parameters relating to sourced VCs. Both AAL2 and non-AAL2 sourced VCs require a VC table entry, where AAL2 VCs are constrained to occupy the lower VC table entries. This table is carved up across the ports as illustrated in Figure 52. VC TABLE PORT TABLE 0 1 2 PortIndex * * VCIMaxOffset0 – VCIMinOffset0 + 1 0 1 NumAal2VCs0 M–1 [NOTE 1][NOTE 2] NumAal2VCs2 VCIMaxOffset2 – VCIMinOffset2 + 1 N–1 [NOTE 1] 1649 (F) Figure 52. VC Table Notes: 1. For ECA, N = NPT_AAL_ADAPBLK_MEM_ALLC(NifVcCnt), which in turn, must be set to at least: Active Egress Ports Σ (NPT_AAL_NIF_TRANSMIT_CONFIG(VCIMaxOffset) – NPT_AAL_NIF_TRANSMIT_CONFIG(VCIMinOffset) + 1) 2. For ISIA, N = NPT_AAL_ADAPBLK_MEM_ALLC(SifVcCnt), which in turn, must be set to at least: Active Ingress Ports Σ (NPT_AAL_SIF_RECEIVE_CONFIG(VCIMaxOffset) – NPT_AAL_SIF_RECEIVE_CONFIG(VCIMinOffset) + 1) Agere Systems Inc. Agere Systems - Proprietary 125 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 18 ATM Adaptation Layer (AAL) Block (continued) MEMI-SM can fit two VC table entries per memory word. For example, in the default initialization of resource bases shown in Table 30, the ISIA VC table is given a range of 0x400 words, which provides an allocation of 2048 VCs sourced to ISIA. The provisioning constraints are as follows: ! NifVcCnt + SifVcCnt may not exceed the overall VC limit of 4064 (4096—32). There are 32 entries reserved for internal use. AAL2 VCs are constrained to occupy the lowermost addresses within the VC range. ! The VC table is discussed further below. 18.5.4.3 AAL2 VC Table The AAL2 VC table contains parameters and state relating to sourced AAL2 VCs. This table is carved up across the ports as illustrated in Figure 53. AAL2 VC TABLE PORT TABLE 0 1 2 PortIndex * * NumAal2VCs0 0 1 M–1 NumAal2VCs2 N–1 [NOTE 1] 1650 (F) Notes: 1. The AAL2 VC count is set to 64 and cannot be changed. 2. MEMI-SM can fit two VC table entries per memory word. For example, in the default initialization of resource bases shown in Table 30, the ISIA AAL2 VC table is given a range of 0x20 words, which provides an allocation of 64 AAL2 VCs sourced to ISIA. Figure 53. AAL2 VC Table 126 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) 18.5.4.4 Connection Table The Connection Table contains parameters and state relating to sourced flows. For sourced AAL2 VCs, a flow is identified as {Port, VCI, CID}. For sourced non-AAL2 VCs, a flow is identified as {Port, VCI}. The Connection Table is carved up across the port, VCs as illustrated in Figure 54. PortIndex VC TABLE CONNECTION TABLE VCTableBase2 + i 0 VCTableBase2 + j 0, j 0, i VCTableBase2 + p VCTableBase2 + q 2 VCTableBase2 + r 2, p 2, q 2, r NumCIDs(0, i) AAL2 VC Table Aal2VCTableBase0 + i 0 0, i NumCIDs(2, p) Aal2VCTableBase0 + p 2 Aal2VCTableBase0 + q 2, p 2, q NumCIDs(2, q) AAL2 SOURCE: NON-AAL2 SOURCE: N–1 [NOTE 1] 1651 (F) Figure 54. Connection Table Agere Systems Inc. Agere Systems - Proprietary 127 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Data Sheet August 18, 2003 18 ATM Adaptation Layer (AAL) Block (continued) Notes: 1. For ECA, N = NPT_AAL_ADAPBLK_MEM_ALLC(NifVcPlusChanCnt), which in turn, must be set to at least: Active Egress Ports Σ( NPT_ADAPTBLK_MEM_ALLC(NifVCCnt) – NPT_ADAPTBLK_MEM_ALLC(NifAal2VcCnt) ) + Expected Number of CIDs on VC . Active AAL2 Egress VCs Ports on Port Σ Σ( ) For ISIA, N = NPT_AAL_ADAPBLK_MEM_ALLC(SifVcPlusChanCnt), which in turn, must be set to at least: Active Ingress Ports Σ( NPT_ADAPTBLK_MEM_ALLC(SifVCCnt) – NPT_ADAPTBLK_MEM_ALLC(SifAal2VcCnt) ) + Expected Number of CIDs on VC . Active AAL2 Ingress VCs Ports on Port Σ Σ( ) The Connection Table must be sized for one entry per non-AAL2 VC, plus an entry for every used CID within each AAL2 VCs. NumCIDs indicates a contiguous range of used CIDs. NumCIDs is programmed during connection configuration, not provisioning (and thus is not a NPT_AAL_ADAPBLK_MEM_ALLC command field). However, the user must predict the total expected number of CIDs across all sourced AAL2 VCs before any connection configuration is done. Since AAL2 VCs may be sourced from both SIF and NIF, a prediction must be made for both ingress and egress. Note that the AAL2 allocation within the Connection Table is a contiguous range of entries: one per CID. MEMI-SM can fit one Connection Table per memory word. For example, in the default initialization of resource bases shown in Table 30, the ISIA Connection Table is given a range of 0x800 words, which provides an allocation of 2048 flows sourced to ISIA. Recall, the provisioning constraints are that NifVcPlusChanCnt + SifVcPlusChanCnt may not exceed the overall limit of 4064 (4096—32) flows. There are 32 entries reserved for internal use. The total number of entries in the connection table is divided evenly between channels and non-AAL2 VCs since every bidirectional AAL2 channel—CPSAAL0 flow will require a channel entry and connection entry in the connection table. So a Connection Table entry is needed for each channel and each non-AAL2 VC at a given interface. 128 Agere Systems - Proprietary Agere Systems Inc. Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 18 ATM Adaptation Layer (AAL) Block (continued) 18.5.4.5 Level 0 Queue Descriptor An overview of the SAR queueing structure is presented in Section 18.4.6 on page 109. Level 0 queueing is the first queueing step, whereby data is obtained from an interface (SIF, NIF, host, or loopback), and sent to the SQASE for buffering in the SQASE shared memory (SQASE-SM). An L0Q is active when the SAR is in the process of accumulating a data unit (for instance, accumulating an PATM packet for segmentation, reassembling a packet from a sequence of ATM-SDUs, etc.). A data unit is the lowest level packet of information associated with a flow/service (a 48-octet cell for AAL0; a CPS packet for AAL2; a PATM packet for PATM; etc.). An L0Q is active during accumulation of a data unit; once the data unit is queued into the SQASE-SM, the L0Q is freed up to be used to accumulate another data unit. L0Qs are a global resource but must also be divided between ingress and egress. The user must specify how many L0Qs are required for the SIF (ingress) and NIF (egress). The general rule that follows is that, for a given interface, the user needs to allocate an L0Q for each simultaneously accumulating service. CPS packets within a sourced AAL2 VC arrive one at a time, so an L0Q is required for each sourced AAL2 VC. The same rule applies for sourced AAL5 VCs. Sourced AAL0 and CPS-AAL0 packets are contained within an ATM cell, so just a single L0Q is required for all such services per direction. If the source user data type (UDT) is PATM or HPF, an L0Q is required for each MPHY. The TAAD08JU2 firmware allocates a static L0Q for each sourced AAL2 VC, and the balance of the L0Qs are dynamically allocated by the SAR to the remaining services. The default allocation of L0Qs is as follows: ! ! ! ! ! ! Total L0Qs = 164. Reserved L0Qs = 2. Egress static L0Qs = 32. Ingress static L0Qs = 32. Egress dynamic L0Qs = 49. Ingress dynamic L0Qs = 49. Dynamic L0Qing can be used to overallocate. The user may configure more non-AAL2 services at the source interface than there are dynamic L0Qs. If the SAR gets sourced data for which there is no L0Q, the data will be discarded. 18.5.4.6 ICID Table Once queued, each user data flow is identified within the SAR with an ICID. The ICID is used to look up destination parameters VPI, VCI, CID, PHY. The ICID table is shared across the destination interfaces (SIF, NIF, host, adaptation loopback). NPT_ADAPTBLK_MEM_ALLC(SifVcPlusChanCnt) + NPT_ADAPTBLK_MEM_ALLC(NifVcPlusChanCnt) must be