AIC1533

AIC1533 Triple-Output LCD Power Supply FEATURES One Low Dropout Linear Regulator Dropout Voltage 500mV at 0.3A Output Current Dual Adjustable Charge Pump Up to +30V Positive Output Down to -10V Negative Output Power Up Sequencing and Adjustable Delay time Power-Saving Shutdown Mode (0.1µA typical) Operating Supply Voltage: 12V 1MHz Operation Frequency Internal Current Limit and Thermal Protection built in LDO part Few External Components Required DESCRIPTION AIC1533, composed of dual charge pumps and a regulator, provide three independent regulated voltages designed for using in thin-film transistor (TFT) liquid crystal display (LCD). The main regulator has an adjustable output voltage and a low dropout voltage of 500mV at 300mA load current is performed. The dual charge pumps independently regulate a positive output and a negative output. AIC1533 has thermal shutdown capability and survives a continuous short circuit from output to ground. A unique control scheme minimizes output ripple as well as output capacitance for both charge pump. APPLICATIONS LCD Monitor Panel Module LCD TV Panel Module 1MHz-switching frequency of AIC1533 provides a low noise, low cost total solution. The device operates up to 15V supply voltage and is available in 14-lead SOP and 16-lead TSSOP package. Analog Integrations Corporation Si-Soft Research Center 3A1, No.1, Li-Hsin Rd. I, Science Park, Hsinchu 300, Taiwan, R.O.C. TEL: 886-3-5772500 FAX: 886-3-5772510 www.analog.com.tw DS-1533P-02 010405 1 AIC1533 TYPICAL APPLICATION CIRCUIT OUT3 10V/300mA 12VIN CIN 10µF + VCC SHDN Cp 1nF TP GND SUPP SW P OUT ADJ TN SW N FBN VREF Cn 4.7nF R3 910k + R4 130k Co3 10µF OUT2 -9V/30mA Co2 1µF CFLY3 0.1µF R5 240k C1 2.2µF BAT54S D1 CFLY1 0.1µF CFLY2 D3 BAT54S R6 33k C4 0.22µF FBP PGND AIC1533 C2 0.47uF OUT1 28V/30mA 0.1µF D2 BAT54S Co1 1µF R1 C3 470k 10pF R2 22k CIN, CO3: HER-MEI Electrolysis Capacitor, LER100M1CD11 or TAIYO YUDEN Ceramic Capacitor, EMK325BJ106MN-B (10µF/16V) CFLY1, CFLY2: TAIYO YUDEN Ceramic Capacitor, UMK212BJ104KG (0.1µF/50V) CFLY3: TAIYO YUDEN Ceramic Capacitor, EMK107BJ104KA (0.1µF/16V) CO1: TAIYO YUDEN Ceramic Capacitor, UMK212F105ZG (1µF/50V) CO2: TAIYO YUDEN Ceramic Capacitor, EMK212F105KG (1µF/16V) D1~D3: W TE Schottky Diode, BAT54S Fig.1 TFT-LCD Power Application 2 AIC1533 ORDERING INFORMATION A IC 153 3X X X X P A C K IN G T Y P E T B : T UB E T R : T APIN G & R E EL P A C K A G IN G T Y PE S : S O P- 1 4 L : T S SO P-16 C : C OM M E RCIA L P : L EAD FR EE C O M M E R C IAL P IN C O NF IG U R A T IO N S O P -14 T O P VIEW ADJ 1 1 4 G ND 1 3 VREF 12 FB N 11 T P 10 T N 9 8 SW N PGND OU T 2 FB P 3 S HDN 4 VCC 5 SUPP 6 7 E x am ple: A IC 1 533 C L T R in T S SO P -16 Pack age & T a ping & R eel P a c k in g T ype A IC 1 53 3P ST R in L ea d F r ee S O P- 1 4 P a c k age & T a ping & R e e l P a c k ing T ype SW P T S S O P -16 T O P VI EW ADJ OU T FB P SHDN VCC SUP P SW P GND 1 2 16 15 14 13 12 GND VREF FB N TP TN 3 4 5 6 1 1 SW N 10 9 P G ND G ND 7 8 3 AIC1533 ABSOLUTE MAXIMUM RATINGS VCC, SHDN to GND FBN, FBP, VREF, ADJ, TN, TP SWN, SWP PGND to GND Operating Temperature Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance Junction to Ambient SOP-14 (Assume no ambient airflow, no heatsink) TSSOP-16 -0.3V to 18V -0.3V to 8V -0.3V to (Vcc+0.3V) ±0.3V -40°C to 85°C 125°C -65°C to 150°C 260°C 100°C/W 120°C/W Absolute Maximum Ratings are those values beyond w hich the life of a device may be impaired. TEST CIRCUIT Refer to TYPICAL APPLICATION CIRCUIT. ELECTRICAL CHARACTERISTICS (VIN=12V, CO1=CO2=1µF, CO3=10µF, CFLY1=CFLY2=CFLY3=0.1µF, TA=25°C, unless otherw ise specified.) (Note 1) PARAMETER Input Voltage Range Quiescent Current Standby Current Thermal Shutdown Temperature TEST CONDITIONS MIN. 10 TYP. 12 1.2 MAX. 15 2.0 1 UNIT V mA µA °C V SHDN =2.4V, IOUT= 0mA V SHDN =0.6V,Output OFF 0.6 155 LOW DROPOUT LINEAR REGULATOR TERMINAL SPECIFICATION Adjustable Voltage Line Regulation Load Regulation Continuous Output Current Current Limit Dropout Voltage VIN =12~15V, VOUT3=10V, IOUT3=1mA VIN =12V, IOUT3=0.1~300mA VIN =12V VIN =12V, V OUT3=0V (Note2) IOUT3=300mA 350 300 700 500 1.225 1.25 1.275 1 1 V % % mA mA mV 4 AIC1533 ELECTRICAL CHARACTERISTICS PARAMETER FBP Threshold FBN Threshold VREF Voltage Continuous Output Current TP/TN Bias Current TP/TN Input Threshold Switching Frequency SUPP switch Internal Switch On-Resistance SWP switch SWN switch SHUTDOWN TERMINAL SPECIFICATIONS SHDN Pin Current SHDN Pin Voltage (Continued) MIN. TYP. MAX. UNIT TEST CONDITIONS CHARGE PUMP TERMINAL SPECIFICATION 1.225 -30 IREF=250µA VIN =12V 3 1.225 0.70 5 1.25 1 5 5 5 1.231 1.25 0 1.25 1.275 30 1.269 30 7 1.275 1.30 10 10 10 Ω V mV V mA µA V MHz V SHDN =2.4V Output ON Output OFF 2.4 0.1 1 µA V 0.6 Note 1: Specifications are production tested at TA=25°C. Specifications over the -40°C to 85°C operating temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). Note 2: Current limit is measured by pulse testing. 5 AIC1533 SHDN 0 Shutdown exit Delay time 90% LDO Negative Charge Pump 0 0 10% T1 90% T2 Positive Charge Pump 0 T1 set by CN T2 set by CP Fig. 2 Pow er Up Sequencing TYPICAL PERFORMANCE CHARACTERISTICS V =0~3V SHDN Vo1 Vo3 V O2=-10V, I O2=30mA VCC=12V VO1=30V, IO1=30mA Vo2 Fig. 3 Power- Up Sequence Fig 4. Ripple Voltage Waveforms 6 AIC1533 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 800 VCC=12V, VO3=10V, CO3=10µF, Io3=300mA 700 VCC=12V VO3 VCC-VOUT (mV) 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 400 450 IO3 IOUT (mA) Fig. 5 LDO Load Transient Response 800 700 800 Fig. 6 Dropout Voltage vs. LDO Load IOUT=300mA 600 500 400 300 200 -40 Current Limit (mA) -20 0 20 40 60 80 100 700 VCC-VOUT (mV) 600 500 400 120 300 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 7 LDO Dropout Voltage vs. Temperature Temperature (°C) Fig. 8 LDO Current Limit vs. Temperature 500 475 7.0 IOUT=300mA TN/TP Bias Current (µA) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 -40 VCC-VOUT (mV) 450 425 400 375 350 10 11 12 13 14 15 16 17 18 -20 0 20 40 60 80 100 120 VCC (V) Fig. 9 LDO Dropout Voltage vs. Input Voltage Temperature (°C) Fig. 10 TN/TP Bias Current vs. Temperature 7 AIC1533 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 1.260 1.255 1.250 -8.0 -8.4 -8.8 VNEG (V) VREF (V) -9.2 -9.6 VCC=11V 1.245 1.240 1.235 -10.0 -10.4 -10.8 VCC=12V VCC=13V 0 10 20 30 40 1.230 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Fig. 11 VREF vs. Temperature 32 31 INEG (mA) Fig. 12 Negative Charge-Pump vs. Load Current 100 VNEG=-10V VCC=13V 90 80 70 60 50 40 30 VCC=12V VCC=11V VCC=13V 30 29 VCC=12V 28 VCC=11V 27 26 25 0 10 20 30 40 Efficiency (%) VPOS (V) 0 10 20 30 40 IPOS (mA) Fig. 13 Positive Charge Pump vs. Load Current 100 90 80 70 60 50 40 30 INEG (mA) Fig. 14 Negative Charge-Pump vs. Load Current VPOS=30V VCC=11V VCC=12V Efficiency (%) VCC=13V 0 10 30 40 IPOS (mA) Fig. 15 Positive Charge-Pump Efficiency vs. Load Current 8 AIC1533 BLOCK DIAGRAM 14 ADJ 1 VCC + EA - Current Limit Thermal Shutdown GND 1.25V Reference Voltage 13 VREF OUT 2 ADJ - 90%VREF + 10%VREF 5µA + 12 5V 5µ A 11 FBN 5V FBP 3 COMP COMP TP SHDN 4 Shutdown OSC Q6 Q7 VCC 5 TP Q1 10 TN VCC SUPP 6 Q4 Q2 9 7 SW N SW P EA + Q3 - FBP FBN VREF + - EA Q5 8 PGND 9 AIC1533 PIN DESCRIPTIONS PIN 1: ADJ PIN 2: OUT PIN 3: FBP - Providing VADJ=1.25V (typ.) for adjustable VOUT. - Adjustable output. LDO regulator PIN 11: TP The capacitor on this pin sets negative charge pump to provide independent time control. Or TN connects to high level directly if it is not in use for programming delay time. - Programmable delay time pin. The capacitor on this pin sets positive charge pump to provide independent time control. Or TP connects to high level directly if it is not in use for programming delay time. - Negative charge pump feedback input. Regulates to 0V typical. - Positive charge pump feedback input. Regulates to 1.25V typical. - Active-Low logic level shutdown input. Connecting SHDN to VCC for typical operation. - Supply input. - Positive charge pump supply pin. It monitors negative charge pump. - Positive charge pump driver output. Output high level is VCC, and low level is GND. - Power ground. Connecting to GND. - Negative charge pump driver output. Output high level is VCC, and low level is GND. - Programmable delay time pin. PIN 4: SHDN PIN 5: VCC PIN 6: SUPP PIN 12: FBN PIN 7: SWP PIN 8: PGND PIN 9: SWN PIN 13: VREF - Internal reference bypass terminal. Connecting a 0.22µF capacitor to ground. Providing a positive voltage greater than negative feedback voltage to obtain a positive voltage for FBN. PIN 14: GND - Ground. Tie GND pin directly to local ground plane to obtain best performance. PIN 10: TN APPLICATION INFORMATION Introduction AIC1533 is composed of dual charge pumps and a regulator to provide three independent regulated voltages exclusively designed for thin-film transistor (TFT) liquid crystal display (LCD) applications. LDO regulator has an adjustable output voltage with a low dropout voltage of 500mV at 300mA load current. Two independent charge pumps regulate a positive output and a negative output by using a 1MHz switching frequency, and a pulse-width-modulation (PWM) architecture. AIC1533 provides a start-up sequence function with an adjustable start-up delay time. In shutdown mode, it only consumes 0.1µA supply current. AIC1533 also features an internal current limit and thermal shutdown protection. Operation As Fig. 16 shows, two internal MOSFETs - Q2, Q3, and external components comprise a positive charge pump, whose output is three times as much as input voltage. After delay time, which determined by CP, Q1 turns on. During on state, which indicates Q2 is at off stage and Q3 at on stage, CFLY1 connects VCC and PGND and is charged by VCC. 10 AIC1533 During off state, Q2 at on stage and Q3 off stage, voltage of C2 is the addition of VCC and VCFLY1. And then go back to on state with voltage of CFLY2 equal to VC2, which is twice as much voltage as VCC. Lastly, the system goes to off state, voltage of Co1 is the addition of VCC and CFLY2, that is, three times as much voltage as VCC. Fig.17 shows the structure of a negative charge pump. During on state, which represents Q4 at on stage and Q5 at off stage, voltage of CFLY3 is equal to VCC. During off state, indicating Q4 at off stage and Q5 on stage, SWN pin connects to PGND directly, and voltage of Co2 equals to -VCC. AIC1533 12VIN VCC AIC1533 VCC SW N Q4 CFLY3 3 2 D3 1 R5 C5 R6 VREF C4 Vn Co2 - Q5 FBN + PGND Fig. 17 Structure of Negative Charge Pump Q1 Power-Up Sequence And Adjustable Delay Time For thin-film transistor (TFT) liquid crystal display applications, power-up sequence of three output voltages is required. Fig. 3 indicates the power-up sequence of AIC1533. After shutdown exit delay time, output of LDO starts rising. When it reaches to 90% of normal voltage, which is determined by an external resistor divider, CN starts being charged from 5µA current source (referring to BLOCK DIAGRAM). The charging time of CN, defined as T1, can be calculated as 1 C1 2 D1 CFLY1 3 SUPP Q2 SW P FBP Q3 D2 C2 1 3 2 Vp + - PGND CFLY2 Co1 R1 R2 C3 T1 = Cn × VTH,n In (1) Fig.16 Structure of Positive Charge Pump where VTH,η = negative threshold voltage, 1.25V, In = negative bias current, 5µA Afterwards, while negative output voltage starts decreasing from 0V, VFBN decreases from 1.1V to 0V proportionally. As VFBN decreases to 10% of VREF, Q7 turns off and Cp starts being charged from 5µA current source (referring to BLOCK DIAGRAM). The charging time of CP, defined as T2, can be calculated as 11 AIC1533 T2 = Cp × VTH,P IP (2) Shutdown AIC1533 shuts off all devices and consumes only 0.1µA supple current when SHDN gets lower than 0.6V. This pin can be pulled high to 2.4V for normal operation. Due to high impedance of SHDN pin, it can’t be floating. where VTH,P = positive threshold voltage, 1.25V IP= positive bias current, 5µA Current Limit And Thermal Protection To protect devices from damage caused by short circuit, AIC1533 provides current limit and thermal protection. When short circuit occurs, output current is clamped at the current limit. Due to power dissipation of LDO is defined as PDISSIPATION = IOUT * (VIN-VOUT) (3) Components Selection 1. Determining The Number Of Charge Pump Stages The number of charge pump stages to regulate is determined by output voltage, supply voltage, switching frequency, load current, forward voltage of diodes, on-resistor of internal MOSFET, and value of ceramic capacitor. For positive charge pump, the number of required stages can be calculated as NPOS ≥ VPOS − Vcc + R TH × Iout Vcc − 2VD Under short circuit condition, the temperature rising, which is caused by power dissipation, gets to thermal shutdown temperature and shuts AIC1533 down. As the temperature gets lower than the thermal shutdown temperature, the device will resume. The pattern of temperature of the device recycles until the short circuit condition is removed. The waveform under short circuit condition is shown as Fig.18. IOUT (4) where VPOS = output of positive charge pump RTH = equivalent output impedance of charge pump Current Limit VD = forward voltage of diodes Vcc = input voltage Thermal Shutdown The following equation approximates RTH RTH = VOUT Fig.18 Current Limit Waveform of AIC1533 2(R DS,ON(P ) + R DS,ON(N) ) + ( 1 1 ) )+( CO × FSW CFLY × FSW (5) where RDS, ON(P) is on-resistor of internal P-channel MOSFET, RDS, ON(N) means on-resistor of internal N-channel MOSFET, and FSW is switching frequency of AIC1533 (referring to ELECTRIVAL CHARACTERISTICS). 12 AIC1533 For negative charge pump, the number of negative charge pump can be determined by NNEG ≥ R TH × Iout − VNEG Vcc − 2VD R3 ) R4 VLDO = VADJ × (1 + (10) (6) where VLDO = output voltage of LDO VADJ = adjustable voltage of LDO, the recommended R4 is 130kΩ. where VNEG = output of negative charge pump Example To obtain VPOS=28V/30mA, VNEG=-9V/30mA from VCC=12V, CFLY=0.1µF, the number of positive and negative charge pumps can be calculated as follows RTH = 2(R DS,ON(P ) + R DS,ON(N) ) + ( 1 1 )+( ) C FLY × FSW C O × FSW 6 2.2. Output Voltage Of Positive Charge Pump Output voltage of positive charge pump is determined by connecting a resistor divider to output terminal of positive charge pump, GND, and FBP (referred to TYPICAL APPLICATION CIRCUIT). The values of resistor divider can be calculated as equation (11). VPOS = VFBP × (1 + R1 ) R2 = 2(10 + 10) + ( 1 0.1× 10 −6 × 1× 10 )+( 1 1× 10 −6 × 1× 10 6 ) (11) =51 (7) where VPOS = output voltage of positive charge pump NPOS ≥ VPOS − Vcc + R TH × Iout 28 − 12 + (51 × 30 × 10 −3 ) = Vcc − 2VD 12 − 2 × 0.5 VFBP = feedback voltage of positive charge pump, 1.25V. The recommended R2 is 22kΩ = 1.59 2.3 Output voltage of negative charge pump Since comparator input of negative charge pump, FBN, is referenced to 0V, a positive reference voltage, which can be obtained by adding a 0.22µF bypass capacitor between VREF and GND, is needed (referred to TYPICAL APPLICATION CIRCUIT). The value of resistor dividers can be calculated as equation (12). VNEG = − VREF × R5 R6 (8) NNEG R × Iout − VNEG (51 × 30 × 10 −3 ) − ( −9) ≥ TH = Vcc − 2VD 12 − 2 × 0.5 = 0.96 (9) Thus, the number of positive charge pump is two, and the negative one requires one charge pump. 2. Output Voltage Selection 2.1 Output voltage of LDO A resistor divider, determining output voltage of LDO, connects to OUT, GND, and ADJ (referred to TYPICAL APPLICATION CIRCUIT). Values of resistors can be calculated by equation (10). (12) where VNEG represents output voltage of negative charge pump, and VREF means reference voltage, 1.25V. The recommended R6 is 33kΩ. 13 AIC1533 3. Flying Capacitor Selection A flying capacitor plays an important role in charge pump strength. Increase of flying capacitor value results in a rise of output capability with smaller ripple voltage. Normal voltage of flying capacitor must comply with the following conditions, as equation (13). VCFLY (POS) = VCFLY (NEG) >1.5 x [VCC x (N)] ..... (13) Where VCFLY(POS) is the normal voltage of positive charge pump flying capacitor, VCFLY(NEG) represents the normal voltage of negative charge pump flying capacitor, and N means the number of charge pump stages Besides, ceramic capacitors composed by different materials, such as X7R, X5R, Z5U and Y5V, have different tolerance in temperature, and result in different capacitance loss. A capacitor, which is made of X7R or X5R, is recommended for AIC1533 applications. maintain stability. The recommended values for both input and output capacitors are 10µF. Because of the material, X5R or X7R, ceramic capacitor has low ESR and excellent electrical characteristics in over temperature. That makes ceramic capacitor suitable for output and input capacitors of AIC1533. 4.2 Charge Pump A ceramic capacitor of a value, which is 10 times of flying capacitor, is suitable for the output capacitor of charge pump. In order to maintain a stable output voltage, make sure to place the capacitor as close to IC as possible. 5. Rectifier Diode Selection A Schottky diode with a current rating equal to or greater than two times of average charge pump input current, and a voltage rating at least 1.5 times of VCC, is recommended. Table 1 indicates the recommended components for AIC1533 applications. 4. Input-Output Capacitor Selection 4.1 LDO AIC1533 needs input and output capacitors to Table.1 Bill of Materials List Designator CIN CFLY1 CFLY2 CFLY3 CO1 CO2 CO3 D1~D3 U1 Part Type 10µF/16V 0.1µF/50V 0.1µF/50V 0.1µF/16V 1µF/50V 1µF/16V 10µF/16V BAT54SW AIC1533 Description Ceramic capacitor, EMK325BJ106MN-B Ceramic capacitor, UMK212BJ104KG Ceramic capacitor, UMK212BJ104KG Ceramic capacitor, EMK107BJ104KA Ceramic capacitor, UMK212F105ZG Ceramic capacitor, EMK212F105KG Ceramic capacitor, EMK325BJ106MN-B Surface mount Schottky barrier diode Triple Adjustable Output DC/DC Converter with a LDO Vender Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden WTE AIC Phone 02-27972155-314 02-27972155-314 02-27972155-314 02-27972155-314 02-27972155-314 02-27972155-314 02-27972155-314 07-8225408 03-5772500 14 AIC1533 Layout Consideration Due to the switching frequency of AIC1533, careful PCB layout is necessary. Place components as close to one another as possible and maintain each connection of minimum length and maximum width of trace for best performance. Make sure each device connect to its immediate ground plane. Fig 19, 20 and 21 represent recommended layouts. Fig. 19 Top Layer Fig. 20 Bottom Layer Fig. 21 Top-over Layer 15 AIC1533 PHYSICAL DIMENSIONS (unit: mm) SOP-14 D S Y M B O L SOP-14 MILLIMETERS MIN. 1.35 0.10 0.33 0.19 8.55 3.80 1.27 BSC 5.80 0.25 0.40 0° 6.20 0.50 1.27 8° MAX. 1.75 0.25 0.51 0.25 8.75 4.00 A H E A1 B C A A e D E h X 45° e H SEE VIEW B A A1 B WITH PLATING BASE METAL SECTION A-A h L 0.25 L VIEW B GAUGE PLANE SEATING PLANE TSSOP-16 D S Y M B O L θ C θ TSSOP-16 MILLIMETERS MIN. MAX. 1.20 0.05 0.80 0.19 0.09 4.90 6.40 BSC 4.30 0.65 BSC 0.45 0° 0.75 8° 4.50 0.15 1.05 0.30 0.20 5.10 A E1 E A1 A2 b c D e e/2 A A E SEE VIEW B E1 e A2 L A θ A1 b c BASE METAL SECTION A-A WITH PLATING 0.25 L VIEW B GAUGE PLANE SEATING PLANE θ 16 AIC1533 Note: Information provided by AIC is believed to be accurate and reliable. However, we cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AIC product; nor for any infringement of patents or other rights of third parties that may result from its use. We reserve the right to change the circuitry and specifications without notice. Life Support Policy: AIC does not authorize any AIC product for use in life support devices and/or systems. Life support devices or systems are devices or systems which, (I) are intended for surgical implant into the body or (ii) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 17