80C32E

Features • • • • • • • • • • • • • • • • • • • 8032 Pin and Instruction Compatible Four 8-bit I/O Ports Three 16-bit Timer/Counters 256 bytes RAM Full-duplex UART Asynchronous Port Reset 6 Sources, 2 Level Interrupt Structure 64 Kbytes Program Memory Space 64 Kbytes Data Memory Space Power Control Modes Idle Mode Power-down Mode On-chip Oscillator Operating Frequency: 30 MHz Power Supply: 4.5V to 5.5V Temperature Range: Military (-55oC to 125oC) Packages: Side Brazed 40-pin, MQFPJ 44-pin QML Q and V with SMD 5962-00518 SCC C an B with Specification SCC9521002 Rad. Tolerant 8-bit ROMless Microcontroller 80C32E Description The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit microcontroller. The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters. The fully static design of the 80C32E reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C32E has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. Rev. 4149M–AERO–06/03 1 Block Diagram RxD TxD P1 P2 T2 T2EX P0 P3 XTAL1 XTAL2 ALE PSEN CPU EA RD WR INT Ctrl Timer 0 Timer 1 Timer 2 UART RAM 256x8 Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3 C51 CORE IB-bus RST T0 INT0 Pin Configuration P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.1/A1 P0.2/A2 P0.3/A3 P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA/VPP ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 P0.2/AD2 P0.3/AD3 39 38 37 36 35 34 33 32 31 30 29 P0.0/AD0 P0.1/AD1 P0.0/A0 VCC NIC* P1.4 P1.3 P1.2 P1.1 P1.0 INT1 T1 6 5 4 3 2 1 44 43 42 41 40 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 SB40 MQFPJ44 18 19 20 21 22 23 24 25 26 27 28 P3.6/WR P2.2/A10 P2.3/A11 P2.4/A12 P3.7/RD NIC* P2.0/A8 P2.1/A9 XTAL2 XTAL1 VSS Note: NIC: No Internal Connection 2 80C32E 4149M–AERO–06/03 80C32E Pin Description Mnemonic VSS VCC Type I I Name and Function Ground: 0V reference Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. P0.0-P0.7 I/O P1.0-P1.7 I/O P2.0-P2.7 I/O I/O I O P3.0-P3.7 I I I I O O RST I 3 4149M–AERO–06/03 Mnemonic Type Name and Function Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier ALE O (I) PSEN O EA XTAL1 XTAL2 I I O 4 80C32E 4149M–AERO–06/03 80C32E Idle and Power-down Operation Idle mode allows the interrupt, serial port and timer blocks to continue to operate while the clock of the CPU is gated off. Power-down mode stops the oscillator. Table 1. PCON Register PCON – Power Control Register 7 SMOD Bit Number 7 6 5 4 6 Bit Mnemonic SMOD 5 4 3 GF1 2 GF0 1 PD 0 IDL Description Double Baud Rate bit Set to select double baud rate in mode 1, 2 or 3. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. General-purpose Flag Cleared by user for General-purpose usage. Set by user for General-purpose usage. General-purpose Flag Cleared by user for General-purpose usage. Set by user for General-purpose usage. Power-down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 000X 0000 Not bit addressable 5 4149M–AERO–06/03 Idle Mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. Power-down Mode To save maximum power, a power-down mode can be invoked by software. In power-down mode, the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from powerdown. To properly terminate power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 1. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and Power-down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put 80C32E into power-down mode. Figure 1. Power-down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. 6 80C32E 4149M–AERO–06/03 80C32E Exit from power-down by either reset or external interrupt does not affect the internal RAM content. Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table 2. State of Ports During Idle and Power-down Modes Mode Idle Powerdown Program Memory External External ALE 1 0 PSEN 1 0 PORT0 Floating Floating PORT1 Port Data Port Data PORT2 Address Port Data PORT3 Port Data Port Data 7 4149M–AERO–06/03 Hardware Description Electrical Characteristics Refer to the C51 8-bit Microcontroller Hardware description manual for details on 80C32E functionality. Absolute Maximum Ratings(2) Ambient Temperature Under Bias. M = Military-55°C to 125°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS ..........................................-0.5V to + 7V Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V Power Dissipation ........................................................... 1 W(2) Notes: 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 8 80C32E 4149M–AERO–06/03 80C32E DC Parameters Table 3. DC Parameters in Standard VoltageTA = -55°C to +125°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 30 MHz. Symbol VIL VIH VIH1 VOL VOL1 VOH Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3(5) Output Low Voltage, port 0, ALE, PSEN(5) Output High Voltage, ports 1, 2, 3 2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC 50 200 -75 ±10 -750 10 75 1.8 1 10 4 1.25F + 5 0.36F + 2.7 Min. -0.5 0.2 VCC + 1.4 0.7 VCC Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V V V V V kΩ µA µA µA pF µA mA mA mA mA mA mA Vin = 0.45V 0.45 V < Vin < VCC Vin = 2.0V Fc = 1 MHz TA = 25°C 2.0V < VCC < 5.5V VCC = 5.5V IOL = 1.6 mA(4) IOL = 3.2 mA(4) IOH = -60 µA IOH = -25 µA IOH = -10 µA IOH = -400 µA IOH = -150 µA IOH = -40 µA Test Conditions VOH1 RRST IIL ILI ITL CIO IPD Output High Voltage, port 0, ALE, PSEN RST Pull-down Resistor Logical 0 Input Current ports 1, 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 Capacitance of I/O Buffer Power-down Current (3) Power Supply Current Freq = 1 MHz Icc Op Freq = 1 MHz Icc Idle Freq = 6 MHz Icc Op Freq = 6 MHz Icc Idle Freq >12 MHz Icc Op Freq >12 MHz Icc Idle (1)(2)(6) ICC F in MHz Notes: 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 6), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator is used. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 4). 3. Power-down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 5). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. The use of a Schmitt Trigger is not necessary. 5. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA 9 4149M–AERO–06/03 If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 6. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. Figure 2. ICC Test Condition, Under Reset VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 3. Operating ICC Test Condition VCC ICC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC P0 EA VCC All other pins are disconnected. Figure 4. ICC Test Condition, Idle Mode VCC ICC Reset = Vss after a high pulse during at least 24 clock cycles VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS EA VCC All other pins are disconnected. 10 80C32E 4149M–AERO–06/03 80C32E Figure 5. ICC Test Condition, Power-down Mode VCC ICC VCC Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 6. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 11 4149M–AERO–06/03 AC Parameters Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example: TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -55°C to +125°C (Military temperature range); VSS = 0V; VCC = 5V ± 10%; Load capacitance for Port 0, ALE and PSEN = 100 pF; Load capacitance for all other outputs = 80 pF. Table 4. External Program Memory Characteristics (ns) 30 MHz Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ Parameter ALE Pulse Width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float 35 130 6 0 30 25 80 65 Min 60 15 35 100 Max Figure 7. External Program Memory Read Cycle 12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ 12 80C32E 4149M–AERO–06/03 80C32E Table 5. External Data Memory Characteristics (ns) 30 MHz Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Parameter RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high 20 90 115 20 215 20 0 40 0 70 235 260 115 min 180 180 135 max Figure 8. External Data Memory Write Cycle ALE TLLDV TWHLH PSEN TLLWL TRLDV TRLRH RD TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 TAVDV TRHDX DATA IN TRHDZ 13 4149M–AERO–06/03 Figure 9. External Data Memory Read Cycle ALE TWHLH PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX Table 6. Serial Port Timing – Shift Register Mode (ns) 30 MHz Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Min 400 300 50 0 300 Max Figure 10. Shift Register Timing Waveforms INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV VALID VALID 0 1 2 3 4 5 6 7 8 TXHQX 1 2 TXHDX VALID VALID 3 4 5 6 7 SET TI VALID VALID VALID VALID SET RI 14 80C32E 4149M–AERO–06/03 80C32E Table 7. External Clock Drive Characteristics (XTAL1) Symbol TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Period High Time Low Time Rise Time Fall Time Min 33.33 5 5 5 5 Max Unit ns ns ns ns ns Figure 11. External Clock Drive Waveforms VCC-0.5 V 0.45 V 0.7VCC 0.2VCC-0.1V TCHCL TCLCX TCLCL TCHCX TCLCH Figure 12. AC Testing Input/Output Waveforms VCC-0.5V INPUT/OUTPUT 0.45V 0.2VCC+0.9 0.2VCC-0.1 AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. Figure 13. Float Waveforms FLOAT VOH-0.1V VOL+0.1V VLOAD VLOAD+0.1V VLOAD-0.1V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20 mA. 15 4149M–AERO–06/03 Figure 14. Clock Waveforms INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION STATE4 P1P2 STATE5 P1P2 STATE6 P1P2 STATE1 P1P2 STATE2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2 P2 (EXT) READ CYCLE RD INDICATES ADDRESS TRANSITIONS PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT FLOAT P2 WRITE CYCLE WR P0 DPL OR Rt OUT DATA OUT P2 PORT OPERATION OLD DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, (INCLUDES INT0, INT1, TO, T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED NEW DATA P0 PINS SAMPLED INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) PCL OUT (EVEN IF MEMORY IS INTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION RXD SAMPLED RXD SAMPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 16 80C32E 4149M–AERO–06/03 80C32E Ordering Information Table 8. Possible Order Entries Part Number MC-80C32E-30-E MJ-80C32E-30-E MC-80C32E-30 MJ-80C32E-30 5962-0051801QQC 5962-0051801QXC 5962-0051801VQC 5962-0051801VXC SCC9521002-01B SCC9521002-02B MM0-80C32E-30-E(1) 5962-0051801Q9A (1) Speed (MHz) 30 30 30 30 30 30 30 30 30 30 30 30 30 Temperature Range 25°C 25°C Package Side Brazed 40-pin (.6) MQFPJ 44-pin Quality Flow Engineering samples Engineering samples Standard Mil. Standard Mil. QML-Q QML-Q QML-V QML-V SCC B SCC B Engineering samples QML-Q QML-V -55°C to +125°C Side Brazed 40 pin (.6) -55°C to +125°C MQFPJ 44-pin -55°C to +125°C Side Brazed 40 pin (.6) -55°C to +125°C MQFPJ 44-pin -55°C to +125°C Side Brazed 40 pin (.6) -55°C to +125°C MQFPJ 44-pin -55°C to +125°C Side Brazed 40 pin (.6) -55°C to +125°C MQFPJ 44-pin -55°C to +125°C Die -55°C to +125°C Die -55°C to +125°C Die 5962-0051801V9A(1) Note: 1. Please contact Atmel for availability. 17 4149M–AERO–06/03 Package Drawings 40-pin Side Braze (600 mils) 18 80C32E 4149M–AERO–06/03 80C32E 44-pin Multilayer Quad Flat Pack 19 4149M–AERO–06/03 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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