[AK09970N]
AK09970N
3D Magnetic Sensor with Programmable Switch
1.
Genaral Description
AK09970N is a 3D magnetic sensor IC with high sensitivity and wide measurement range utilizing our
latest Hall sensor technology.
Our ultra-small package of AK09970N incorporates magnetic sensors, chopper stabilized signal,
amplifier chain, and all necessary interface logic for detecting weak to strong magnetic fields in the X, Y
and Z planes independently. From its compact foot print, thin package, and extremely low power
consumption, it is suitable for a wide range of applications such as connected home, door & window
opening/close sensing, and magnetic tamper detection of IoT systems or smart meters just to name a
few.
2.
Features
Functions:
¾ 16 bit data out for each 3-axis magnetic component
¾ Programmable threshold 3-axis magnetometer
¾ Built-in A to D Converter for magnetometer data output
¾ Selectable sensor measurement range and sensitivity setting
High sensitivity setting
z Sensitivity: 1.1 μT/LSB (typ.)
z Measurement range: ± 36 mT
Wide range setting
z Sensitivity: 3.1 μT/LSB (typ.)
z Measurement range: X and Y-axis Æ ±34.9mT, Z-axis Æ ±101.5mT
¾ Serial interface
I2C bus interface
Standard and Fast mode compliant with Philips I2C specification Ver.2.1
4-wire SPI
¾ Operation mode
Power-down, Single measurement, Continuous measurement
¾ 3-axis programmable switch function
¾ Output pin for event notification
INT pin and OD-INT pin
¾ DRDY function for measurement data ready
¾ Magnetic sensor overflow monitor function
¾ Built-in oscillator for internal clock source
¾ Selectable sensor drive
Low power drive / Low noise drive
Operating temperatures:
¾
-4Û&WRÛ&
Operating supply voltage:
¾
+1.7V to +3.6V
Current consumption (VDD = +1.8V, +2Û&):
¾ Power-down:
2.0 nA (typ.)
¾ Measurement:
Average current consumption at 1 Hz/10Hz repetition rate
z Low power drive: 1.0 μA(typ.)@1HzODR, 3.5 μA(typ.)@10HzODR
z Low noise drive: 2.0 μA(typ.) @1HzODR, 12.0 μA(typ.)@10HzODR
Package
¾ AK09970N 16-pin QFN package: 3.0mm x 3.0mm x 0.75mm
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3.
Table of Contents
1.
2.
3.
4.
Genaral Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents................................................................................................................................ 2
Block Diagram and Functions ............................................................................................................. 4
4.1. Block Diagram.............................................................................................................................. 4
4.2. Functions ..................................................................................................................................... 4
5. Pin Configurations and Functions....................................................................................................... 5
6. Absolute Maximum Ratings ................................................................................................................ 6
7. Recommended Operating Conditions................................................................................................. 6
8. Electrical Characteristics..................................................................................................................... 7
8.1. DC Characteristics........................................................................................................................... 7
8.2. AC Characteristics of RSTN ............................................................................................................ 7
8.3. AC Characteristics of INT and OD-INT ........................................................................................... 8
8.4. Overall Characteristics .................................................................................................................... 9
8.5. 4-wire SPI ...................................................................................................................................... 10
8.6. I2C Bus Interface............................................................................................................................ 11
9. Status Description ............................................................................................................................. 12
9.1. State Transition Diagram............................................................................................................... 12
9.2. Power States ................................................................................................................................. 13
9.3. Register States .............................................................................................................................. 13
9.4. Pin States ...................................................................................................................................... 13
10.
Functional Descriptions ................................................................................................................. 14
10.1. Reset Functions........................................................................................................................... 14
10.2. Operation modes ......................................................................................................................... 14
10.2.1.
Description of Each Operation Mode.............................................................................. 14
10.3. Data Ready.................................................................................................................................. 16
10.3.1.
Normal Measurement Data Read Sequence ................................................................. 16
10.3.2.
Data Read Start during Measurement............................................................................ 17
10.3.3.
Data Skip......................................................................................................................... 17
10.3.4.
End Operation................................................................................................................. 18
10.4. Programmable Switch Function .................................................................................................. 18
10.5. Error Notification Function........................................................................................................... 19
10.5.1.
Magnetic Sensor Overflow.............................................................................................. 19
10.5.2.
ADC Overflow ................................................................................................................. 19
10.6. Interrupt Function ........................................................................................................................ 20
10.6.1.
Timing of Interrupt Function Operation........................................................................... 21
10.7. Sensor Drive Select..................................................................................................................... 22
10.8. Sensor Measurement Range and Sensitivity Select................................................................... 22
11.
Serial Interface .............................................................................................................................. 23
11.1. 4-wire SPI .................................................................................................................................... 23
11.1.1.
Writing Data .................................................................................................................... 23
11.1.2.
Reading Data .................................................................................................................. 24
11.2. I2C Bus Interface.......................................................................................................................... 24
11.2.1.
Data Transfer .................................................................................................................. 24
11.2.2.
WRITE Instruction........................................................................................................... 26
11.2.3.
READ Instruction ............................................................................................................ 27
12.
Registers ....................................................................................................................................... 29
12.1. Description of Registers .............................................................................................................. 29
12.2. Register Map ............................................................................................................................... 30
12.3. Detailed Description of Registers ................................................................................................ 32
12.3.1.
WIA[15:0]: Company ID and Device ID .......................................................................... 32
12.3.2.
RSV[15:0]: Reserved Register ....................................................................................... 32
12.3.3.
ST[15:0]: Status .............................................................................................................. 32
12.3.4.
HX[15:0]/HY[15:0]/HZ[15:0]: Measurement Data........................................................... 33
12.3.5.
CNTL1[15:0]: Interrupt Output Setting............................................................................ 35
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12.3.6.
CNTL2[7:0]: Operation Mode, Sensor Drive, Measurement Range and Sensitivity setting
36
12.3.7.
BOP1,2 and BRP1,2 registers: Operating Threshold and Returning Threshold Setting of
Programmable Switch Function........................................................................................................ 37
12.3.8.
SRST[7:0]: Soft Reset .................................................................................................... 38
12.3.9.
I2CDIS[7:0]: I2C Disable ................................................................................................. 38
12.3.10. TST1[15:0]/TST2[7:0]: Test register ............................................................................... 39
13.
Recommended External Circuits................................................................................................... 40
13.1. I2C Bus Interface.......................................................................................................................... 40
13.2. 4-wire SPI .................................................................................................................................... 41
14.
Package......................................................................................................................................... 42
14.1. Outline Dimensions ..................................................................................................................... 42
14.2. Pad Dimensions........................................................................................................................... 42
14.3. Marking ........................................................................................................................................ 43
14.4. Pin Assignment............................................................................................................................ 43
15.
Magnetic Orientation ..................................................................................................................... 44
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4.
Block Diagram and Functions
4.1. Block Diagram
3-axis
Hall
sensor
Chopper
SW
&
MUX
PreAMP
ADC
RSTN
SCL/SK
OSC1
OSC2
Analog
Regulator
Timing
Control
&
Signal
Processing
Interface,
Logic
&
Register
SDA/SI
CSB
SO
INT
VREF
OD-INT
VSS
VDD
CAD
4.2. Functions
Block
3-axis Hall sensor
Chopper SW MUX
Analog Regulator
PREAMP
ADC
OSC1
OSC2
VREF
Interface Logic
&
Register
Timing Control
&
Signal Processing
Function
Monolithic Hall elements.
Multiplexer for selecting Hall elements.
Internal power supply.
Differential amplifier used to amplify the magnetic sensor signal.
Convert analog output to digital output.
Generates an operating clock for sensor measurement.
Generates an operating periodic clock for sequencer.
Generates temperature independent reference voltage.
Exchanges data with an external CPU.
INT and OD-INT pin indicates State1 or/and State2 (selectable).
State1: Sensor measurement has ended and data is ready to be read.
State2: Measurement magnetic data exceeds setting switch threshold value.
I2C bus interface using two pins (SCL and SDA). Standard and Fast modes are
supported.
4-wire SPI is also supported by SK, SI, SO and CSB pins.
Generates a timing signal required for internal operation.
Magnetic sensitivity adjustment and switch calculation for switch function.
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5.
Pin Configurations and Functions
Pin
No.
1
Pin
name
INT
I/O
Type
Function
O
CMOS
2
CSB
I
CMOS
3
SCL
I
CMOS
N/C
SDA
I/O
CMOS
SI
I
6
SO
O
CMOS
7
8
9
10
11
N/C
N/C
N/C
N/C
OD-INT
O
12
CAD
I
Open
Drain
CMOS
13
14
15
16
VSS
N/C
VDD
RSTN
I
Power
Power
CMOS
Interrupt pin
“H” active. Refer to section 10.6.
Chip select pin for 4-wire SPI
“L” active. Connect to VDD when selecting I2C bus
interface.
When the I2C bus interface is selected (CSB pin is
connected to VDD).
SCL: Control clock input pin
Input: Schmitt trigger
When the 4-wire SPI is selected.
SK: Serial clock input pin
Non-connect. Keep this pin non-connected.
When the I2C bus interface is selected (CSB pin is
connected to VDD).
SDA: Control data input/output pin
Input: Schmitt trigger, Output: Open-drain
When the 4-wire SPI is selected.
SI: Serial data input pin
When the I2C bus interface is selected (CSB pin is
connected to VDD)
Hi-Z output. Keep this pin electrically non-connected.
When the 4-wire SPI is selected.
Serial data output pin
Non-connect. Keep this pin non-connected.
Non-connect. Keep this pin non-connected.
Non-connect. Keep this pin non-connected.
Non-connect. Keep this pin non-connected.
Open-drain interrupt pin
͆L” active. Refer to section 10.6.
When the I2C bus interface is selected (CSB pin is
connected to VDD).
CAD: Slave address input pin
Connect to VSS or VDD.
When the 4-wire serial interface is selected.
Connect to VSS.
Ground pin
Non-connect. Keep this pin non-connected.
Positive power supply pin
Reset pin
Resets registers by setting to “L”.
SK
4
5
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6.
Absolute Maximum Ratings
VSS=0V
Parameter
Power supply voltage
Input voltage
Input current
Storage temperature
Symbol
V+
VIN
IIN
Tstg
Min.
-0.3
-0.3
-10
-40
Max.
+4.3
(V+)+0.3
+10
+125
Unit
V
V
mA
Û&
Note:
If the device is used in conditions exceeding these values, the device may be destroyed. Normal
operations are not guaranteed in such exceeding conditions.
7.
Recommended Operating Conditions
VSS=0V
Parameter
Operating temperature
Power supply voltage
Remark
VDD pin voltage
Symbol
Ta
Vdd
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Min.
-40
1.7
Typ.
1.8
Max.
+85
3.6
Unit
Û&
V
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8.
Electrical Characteristics
The following conditions apply unless otherwise noted:
Vdd = 1.7V to 3.6V, Temperature range = -4Û&WRÛ&
Typical condition: Vdd = 1.8 V, Temperature = 25 Û&
8.1. DC Characteristics
Parameter
High level input voltage
Low level input voltage
Symbol
VIH
VIL
Input current
IIN
Hysteresis input voltage
*1
High level output voltage
*2
Current consumption
*4
VOH
*2
VOL1
*3
VOL2
Low level output voltage 1
Low level output voltage 2
VHS
IDD1
Pin
CSB
RSTN
SCL/SK
SDA/SI
CAD
CSB
RSTN
SCL/SK
SDA/SI
SO
INT
SO
INT
SDA/SI
OD-INT
VDD
IDD2
IDD3
Condition
-
Min.
70%Vdd
-
VIN
= Vss or Vdd
-10
9GG9
5%Vdd
Vdd 80%Vdd
5
-
-
μs
tSPRST
RSTN
-
-
-
1
μs
Figure 8.1 Reset condition
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8.3. AC Characteristics of INT and OD-INT
Parameter
Fall time of OD-INT
Symbol
TfOD
Pin
OD-INT
Fall time of INT
Rise time of INT
TfINT
TrINT
INT
INT
Condition
CL = 50 pF
RL N W\S
CL = 50 pF
CL = 50 pF
Min.
-
Typ.
-
Max.
250
Unit
ns
-
-
250
250
ns
ns
Figure 8.2 Output load circuit of OD-INT (recommended circuit)
[Rise time and fall time]
TfOD
OD-INT
90%Vdd
10%Vdd
TrINT
TfINT
90%Vdd
10%Vdd
INT
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8.4. Overall Characteristics
Table 8.1 High sensitivity setting
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Measurement data
output bit
Time for measurement
DBIT
-
-
16
-
Bit
TSM
SDR bit = “0”
(Low noise drive)
SDR bit = “1”
(Low power drive)
7D Û&,
SMR bit = “0”
7D Û&,
SMR bit = “0”
7D Û&,
X and Y-axis
7D Û&
Z-axis
SDR bit = “0”
(Low noise drive)
SDR bit = ”1”
(Low power drive)
-
0.792
0.872
ms
-
0.23
0.253
0.99
1.1
1.21
μT/LSB
s32.44
s36.04
s39.64
mT
-614
-
+614
LSB
-868
-
+868
-
5.0
-
-
15.0
-
Magnetic sensor
sensitivity
Magnetic sensor
measurement range
Magnetic sensor
*5
initial offset
*6
Noise
BSE
BRG
BOF
NIS
μTrms
Table 8.2 Wide range setting
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Measurement data
output bit
Time for measurement
DBIT
-
-
16
-
Bit
TSM
SDR bit = “0”
(Low noise drive)
-
0.792
0.872
ms
SDR bit = “1”
-
0.23
0.253
2.79
3.1
3.41
μT/LSB
s31.42
s34.91
s38.4
mT
s91.42
s101.57
s111.73
-218
-
+218
-308
-
+308
-
6.0
-
Magnetic sensor
sensitivity
Magnetic sensor
measurement range
Magnetic sensor
*5
initial offset
*6
Noise
BSE
BRG
BOF
NIS
(Low power drive)
7D Û&,
SMR bit = “1”
7D Û&,
X and Y-axis,
SMR bit = “1”
7D Û&,
Z-axis,
SMR bit = “1”
7D Û&,
X and Y-axis
7D Û&
Z-axis
SDR bit = “0”
(Low noise drive)
SDR bit = “1”
(Low power drive)
LSB
μTrms
18.0
Note:
* 5. Value of measurement data register on shipment test without applying magnetic field on purpose.
* 6. Reference value for design. Under steady magnetic field.
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8.5. 4-wire SPI
4-wire SPI is compliant with mode 3 (SPI-mode3)
Parameter
SK clock frequency
CSB setup time
Data setup time
Data hold time
SK high time
Symbol
Fspi
Tcs
Ts
Th
Twh
SK low time
Twl
SK setup time
*7
SK to SO delay time
*7
CSB to SO delay time
*8
SK rise time
*8
SK fall time
CSB high time
Tsd
Tdd
Condition
Vddt2.5V
2.5V>Vddt1.7V
Vddt2.5V
2.5V>Vddt1.7V
-
Min.
50
50
50
100
150
100
150
50
-
Typ.
-
Max.
4.0
50
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tcd
Tr
Tf
Tch
-
450
-
50
100
100
ns
ns
ns
ns
Notes:
* 7.SO load capacitance: 20pF
* 8.Reference value for design
Tch
Tcs
CSB
Tsd
Ts
Th
Tdd
Twh
Tcd
Twl
SK
SI
Hi-Z
Hi-Z
SO
Figure 8.3 4-wire SPI
Tr
Tf
0.9Vdd
0.1Vdd
SK
Figure 8.4 Rise time and fall time
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8.6. I2C Bus Interface
CSB pin = “H”
I2C bus interface is compliant with Standard mode and Fast mode. Standard/Fast is selected
automatically by fSCL.
Standard mode
I6&/N+]
Symbol
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Parameter
Min.
Typ.
Max.
Unit
SCL clock frequency
SCL clock “High” time
SCL clock “Low” time
SDA and SCL rise time
SDA and SCL fall time
Start Condition hold time
Start Condition setup time
SDA hold time
(vs. SCL falling edge)
SDA setup time
(vs. SCL rising edge)
Stop Condition setup time
Bus free time
4.0
4.7
4.0
4.7
0
-
100
1.0
0.3
-
kHz
μs
μs
μs
μs
μs
μs
μs
250
-
-
ns
4.0
4.7
-
-
μs
μs
Fast mode
100kHz BRPX1
(Switch function enable)
BOPX1 < HX
BRPX1 > HX
Other relations
1
0
Previous result
SWX1 bit = ”1”㻌
Hysteresis㻌
SWX1 bit = ”0”㻌
-BRG㻌
BRPX1㻌
BOPX1㻌
Measurement
data (HX)
BRG㻌
* 14
Figure 10.7 Relation between threshold values and SWX1 bit
Note:
* 14. SWX1 bit, SWY1 bit, SWZ1 bit, SWX2 bit, SWY2 bit and SWZ2 bit exhibits the same relationship
10.5. Error Notification Function
10.5.1. Magnetic Sensor Overflow
AK09970N has a limitation for measurement range, where the absolute value of X-axis and Y-axis
should be smaller than 36.04 mT (High sensitivity mode) or 34.91 mT (Wide range mode). When the
magnetic field exceeds this limitation, AK09970N outputs limitation value at the X-axis or/and Y-axis
(fixed value: 36.04 mT or 34.91 mT). This is called magnetic sensor overflow. When magnetic sensor
overflow occurs, ERRXY bit turns to “1”. When the magnetic field less than limitation value,
measurement data register (HX and HY) and ERRXY bit are updated.
10.5.2. ADC Overflow
AK09970N has a limitation for ADC range, when the magnetic field exceeded this limitation, data stored
at measurement data registers (HX, HY and HZ) are not correct. This is called ADC overflow. When
ADC overflow occurs, ERRADC bit turns to “1”.When measurement data registers are updated,
ERRADC bit is updated.
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10.6. Interrupt Function
AK09970N has two interrupt pins, INT pin (CMOS) and OD-INT pin (Open-drain). When CNTL1 register
is set and interrupt event (magnetic event) occurred, AK09970N outputs selected interrupt event at the
INT pin or/and OD-INT pin. AK09970N can output four type of interrupt event (Data ready, Magnetic
sensor overflow, ADC overflow and Switch event) to pins. INTEN bit and ODINTEN bit can select
interrupt function be enabled or disabled. When set INTEN bit/ODINTEN bit =”1” and magnetic event
occurs, INT pin turn to “H” and OD-INT pin turn to “L”.
Interrupt㻌
H㻌
Hysteresis㻌
Magnetic
flux density
L㻌
-BRG㻌
Returning
Operating
Threshold㻌
Threshold㻌
㻌
BRG㻌
Figure 10.8 Interrupt pin
Content of
interrupt event
Data ready
(Refer to 10.3)
Table 10.3 Interrupt event and interrupt function
INT
Conditions of event
INTEN
ODINTEN
pin output
bit
bit
DRDYEN bit = ”1”,
DRDY bit = ”1”
0
1
Magnetic sensor
Overflow
(Refer to 10.5.1)
ERRXYEN bit =”1”,
ERRXY bit = “1”
0
ADC overflow
(Refer to 10.5.2)
ERRADCEN bit =”1”,
ERRADC bit = “1”
1
0
1
Switch event
(Refer to 10.4)
-
* 15
0
SWEN bit =”1”,
* 16
SW bit :
”0”Æ”1” or “1”Æ”0”
1
Other than those above
condition
Don’t
care
OD-INT
pin
output
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Don’t
care
L
H
Note:
* 15. SWX1EN bit, SWY1EN bit, SWZ1EN bit, SWX2EN bit, SWY2EN bit and/or SWZ2EN bit
* 16. SWX1 bit, SWX2 bit, SWY1 bit, SWY2 bit, SWZ1 bit and/or SWZ2 bit
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10.6.1. Timing of Interrupt Function Operation
Timing of interrupt function operation is given below. Refer to Table 10.4, Figure 10.9 and Figure 10.10.
Table 10.4 Timing of interrupt function operation
Pin name
INT pin
OD-INT pin
Output transition
LÆH
Timing of transition
End of measurement
Remarks
-
HÆL
Read address 10h -1Fh
or
Write address 20h - 27h
End of measurement
During access to
address, INT pin is
always “L” state.
-
Read address 10h - 1Fh
or
Write address 20h - 27h
During access to
address, OD-INT
pin is always “H”
state.
HÆL
LÆH
(N-1)th
PS
Nth
Measurement
(N+1)th
Measurement
PS
ST register and
Measurement Data Register
(N-1)th
Nth [Event 1 occur]
PS
(N+1)th [Event 2 occur]
Interrupt for Event 1
Interrupt for Event 2
Interrupt for Event 1
Interrupt for Event 2
INT pin
OD-INT pin
Addr. ST,Data(N)
Data read
Addr. ST
Figure 10.9 Timing chart of interrupt function (Normal read sequence)
(N-1)th
PS
Nth
Measurement
(N+1)th
Measurement
PS
ST register and
Measurement Data Register
(N-1)th
Nth [Event 1 occur]
PS
(N+1)th [Event 2 occur]
Interrupt for Event 1
Interrupt for Event 2
Interrupt for Event 1
Interrupt for Event 2
INT pin
OD-INT pin
Data read
Addr. ST,Data(N)
Figure 10.10 Timing chart of interrupt function
(When Nth data is read start immediately before (N+1)th measurement end)
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10.7. Sensor Drive Select
Users can choose “Low power” or “Low noise” drive by the SDR bit.
“Low power” is used to save the current consumption and “Low noise” is used to reduce the noise of the
AK09970N. When Low noise (SDR bit = “0”) is set, output magnetic data noise is more reduced than
Low power (about 70% of Low power). When Low power (SDR bit = “1”) is set, average current
consumption at 10 Hz repetition rate is saved from 12.0 μA to 3.2 μA (VDD=1.8V, Û&). Default SDR
bit is Low noise enable (SDR bit = “0”).
10.8. Sensor Measurement Range and Sensitivity Select
Users can choose “High sensitivity (Normal measurement range and high sensitivity)” or “Wide range
(Wide measurement range and normal sensitivity)” setting.
“High sensitivity” is used to measure with high magnetic sensitivity and “Wide range” is used to measure
strong magnetic field (apply only to Z-axis). When High sensitivity (SMR bit = “0”) is set, magnetic sensor
sensitivity is about three times higher than Wide range (3.1 μT/LSB Æ 1.1μT/LSB). When Wide range
(SMR bit = “1”) is set, Z-axis measurement range is about three times wider than High sensitivity (Z-axis
measurement range:s36.04 mT Æ s101.57 mT). Default SMR bit is High sensitivity enable (SMR bit =
“0”).
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11. Serial Interface
AK09970N supports I2C bus interface and 4-wire SPI. A selection is made by CSB pin. When used as
3-wire SPI, set SI pin and SO pin wired-OR externally.
CSB pin = “L”:
4-wire SPI
CSB pin = “H”:
I2C bus interface
11.1. 4-wire SPI
The 4-wire SPI consists of four digital signal lines: SK, SI, SO, and CSB, and is provided in 16bit
protocol. Data consists of Read/Write control bit (R/W), register address (7-bit) and control data (8-bit).
To read out all axes measurement data (X, Y, Z), an option to read out more than one byte data using
automatic increment command is available. (Sequential read operation)
CSB pin is low active. Input data is taken in on the rising edge of SK pin, and output data is changed on
the falling edge of SK pin. (SPI-mode3)
Communication starts when CSB pin transits to “L” and stops when CSB pin transits to “H”. SK pin must
be “H” during CSB pin is in transition. Also, it is prohibited to change SI pin during CSB pin is “H” and SK
pin is “H”.
11.1.1. Writing Data
Input 16 bits data on SI pin in synchronous with the 16-bit serial clock input on SK pin. Out of 16 bits
input data, the first 8-bit specify the R/W control bit (R/W = “0” when writing) and register address (7-bit),
and the latter 8-bit are control data (8-bit). When any of addresses listed on Table 12.2 is input,
AK09970N recognizes that it is selected and takes in latter 8-bit as setting data.
If the number of clock pulses is less than 16, no data is written. It is compliant with serial write operation
for multiple addresses. AK09970N has one increment line; 20h to 27h. AK09970N increments as
follows: 20h Æ 21h Æ 22h Æ 23h ... Æ 27h Æ 20h Æ 21h … .
CSB
1㻌
2㻌
3㻌
4㻌
5㻌
6㻌
7㻌
8㻌
9㻌
A5㻌
A4㻌
A3㻌
A2㻌
A1㻌
A0㻌
D7㻌
10㻌
11㻌
12㻌
13㻌
14㻌
15㻌
16㻌
SK
SI
RW
A6
D6㻌
D5㻌
D4㻌
D3㻌
D2㻌
D1㻌
D0㻌
(INPUT)
SO
Hi-Z
(OUTPUT)
Figure 11.1 4-wire SPI writing data
Figure 11.2 4-wire SPI serial writing data
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[AK09970N]
11.1.2. Reading Data
Input the R/W control bit (R/W = “1”) and 7-bit register address on SI pin in synchronous with the first
8-bit of the 16 bits of a serial clock input on SK pin. Then AK09970N outputs the data held in the
specified register with MSB first from SO pin.
When clocks are input continuously after one byte of data is read, the address is incremented and data
in the next address is output. Accordingly, after the falling edge of the 15th clock and CSB pin is “L”, the
data in the next address is output on SO pin. When CSB pin is driven “L” to “H”, SO pin is placed in the
high-impedance state.
AK09970N has one increment line; 20h to 27h. AK09970N increments as follows: 20h Æ 21h Æ 22h Æ
23h ... Æ 27h Æ 20h Æ 21h … .
CSB
1㻌
2㻌
3㻌
4㻌
5㻌
6㻌
7㻌
8㻌
A5㻌
A4㻌
A3㻌
A2㻌
A1㻌
A0㻌
9㻌
10㻌
11㻌
12㻌
13㻌
14㻌
15㻌
16㻌
SK
SI
RW
A6
(INPUT)
SO
(OUTPUT)
Hi-Z
Hi-Z
D7㻌
D6㻌
D5㻌
D4㻌
D3㻌
D2㻌
D1㻌
D0㻌
Figure 11.3 4-wire SPI reading data
Figure 11.4 4-wire SPI serial reading data
11.2. I2C Bus Interface
The I2C bus interface of AK09970N supports the Standard mode (100 kHz max.) and the Fast mode
(400 kHz max.).
11.2.1. Data Transfer
To access AK09970N on the bus, generate a start condition first.
Next, transmit a one-byte slave address including a device address. At this time, AK09970N compares
the slave address with its own address. If these addresses match, AK09970N generates an
acknowledgement, and then executes READ or WRITE instruction. At the end of instruction execution,
generate a stop condition.
11.2.1.1. Change of Data
A change of data on the SDA line must be made during “Low” period of the clock on the SCL line. When
the clock signal on the SCL line is “High”, the state of the SDA line must be stable. (Data on the SDA line
can be changed only when the clock signal on the SCL line is “Low”.)
During the SCL line is “High”, the state of data on the SDA line is changed only when a start condition or
a stop condition is generated.
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[AK09970N]
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 11.5 Data Change
11.2.1.2. Start/Stop Condition
If the SDA line is driven to “Low” from “High” when the SCL line is “High”, a start condition is generated.
Every instruction starts with a start condition.
If the SDA line is driven to “High” from “Low” when the SCL line is “High”, a stop condition is generated.
Every instruction stops with a stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 11.6 Start and stop condition
11.2.1.3. Acknowledge
The IC that is transmitting data releases the SDA line (in the “High” state) after sending 1-byte data.
The IC that receives the data drives the SDA line to “Low” on the next clock pulse. This operation is
referred as an acknowledge. With this operation, whether data has been transferred successfully can be
checked. AK09970N generates an acknowledge after receipt of the start condition and slave address.
When a WRITE instruction is executed, AK09970N generates an acknowledge after every byte that is
received.
When a READ instruction is executed, AK09970N generates an acknowledge then transfers the data
stored at the specified address. Next, AK09970N releases the SDA line then monitors the SDA line. If a
master IC generates an acknowledge instead of a stop condition, AK09970N transmits the 8-bit data
stored at the next address. If no acknowledge is generated, AK09970N stops data transmission.
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[AK09970N]
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 11.7 Generation of acknowledge
11.2.1.4. Slave Address
The slave address of AK09970N can be selected from the following list by setting CAD0/1 pin. When
CAD pin is fixed to VSS, the corresponding slave address bit is “0“. When CAD pin is fixed to VDD, the
corresponding slave address bit is “1”.
Table 11.1 Slave address and CAD pin
CAD
Slave Address
0
0Ch
1
0Dh
MSB
0
LSB
0
0
1
1
0
CAD
R/W
Figure 11.8 Slave address
The first byte including a slave address is transmitted after a start condition, and an IC to be accessed is
selected from the ICs on the bus according to the slave address.
When a slave address is transferred, the IC whose device address matches the transferred slave
address generates an acknowledge then executes an instruction. The 8th bit (least significant bit) of the
first byte is a R/W bit.
When the R/W bit is set to “1“, READ instruction is executed. When the R/W bit is set to “0“, WRITE
instruction is executed.
11.2.2. WRITE Instruction
When the R/W bit is set to “0”, AK09970N performs write operation.
In write operation, AK09970N generates an acknowledge after receiving a start condition and the first
byte (slave address) then receives the second byte. The second byte is used to specify the address of
an internal control register and is based on the MSB-first configuration.
MSB
A7
LSB
A6
A5
A4
A3
A2
A1
A0
Figure 11.9 Register address
After receiving the second byte (register address), AK09970N generates an acknowledge then receives
the third byte.
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[AK09970N]
The third and the following bytes represent control data. Control data consists of 8-bit and is based on
the MSB-first configuration. AK09970N generates an acknowledge after every byte is received. Data
transfer always stops with a stop condition generated by the master.
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Figure 11.10 Control data
AK09970N can write multiple bytes of data at a time.
After reception of the third byte (control data), AK09970N generates an acknowledge then receives the
next data. If additional data is received instead of a stop condition after receiving one byte of data, the
address counter inside the LSI chip is automatically incremented and the data is written at the next
address.
The address is incremented from 20h to 27h. When the address is between 20h and 27h, the address is
incremented 20h Æ 21h Æ 22h Æ 23h ... Æ 27h, and the address goes back to 20h after 27h.
Actual data is written only to Read/Write registers (Table 12.2)
S
T
A
R
T
SDA
S
S
T
O
P
R/W="0"
Slave
Address
Register
Address(n)
A
C
K
Data(n+1)
Data(n)
A
C
K
Data(n+x)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 11.11 WRITE Instruction
11.2.3. READ Instruction
When the R/W bit is set to “1”, AK09970N performs read operation.
If a master IC generates an acknowledge instead of a stop condition after AK09970N transfers the data
at a specified address, the data at the next address can be read.
Address can be 20h to 27h. When the address is between 20h and 27h, the address is incremented 20h
Æ 21h Æ 22h Æ 23h ... Æ 27h, and the address goes back to 20h after 27h.
AK09970N supports one byte read and multiple byte read.
11.2.3.1. Current Address Read
AK09970N has an address counter inside the LSI chip. In current address read operation, the data at an
address specified by this counter is read.
The internal address counter holds the next address of the most recently accessed address.
For example, if the address most recently accessed (for READ instruction) is address “n”, and a current
address read operation is attempted, the data at address “n+1” is read.
In current address read operation, AK09970N generates an acknowledge after receiving a slave address
for the READ instruction (R/W bit = “1”). Next, AK09970N transfers the data specified by the internal
address counter starting with the next clock pulse, then increments the internal counter by one. If the
master IC generates a stop condition instead of an acknowledge after AK09970N transmits one byte of
data, the read operation stops.
S
T
A
R
T
SDA
S
S
T
O
P
R/W="1"
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
A
C
K
Data(n+x)
Data(n+2)
A
C
K
P
A
C
K
Figure 11.12 Current address read
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[AK09970N]
11.2.3.2. Random Address Read
By random address read operation, data at an arbitrary address can be read.
The random address read operation requires to execute WRITE instruction as dummy before a slave
address for the READ instruction (R/W bit = “1”) is transmitted. In random read operation, a start
condition is first generated then a slave address for the WRITE instruction (R/W bit = “0”) and a read
address are transmitted sequentially.
After AK09970N generates an acknowledge in response to this address transmission, a start condition
and a slave address for the READ instruction (R/W bit = “1”) are generated again. AK09970N generates
an acknowledge in response to this slave address transmission. Next, AK09970N transfers the data at
the specified address then increments the internal address counter by one. If the master IC generates a
stop condition instead of an acknowledge after data is transferred, the read operation stops.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W="0"
Slave
Address
Register
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W="1"
Slave
Address
Data(n+1)
Data(n)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
Figure 11.13 Random address read
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[AK09970N]
12. Registers
12.1. Description of Registers
AK09970N has registers of 29 addresses as indicated in Table 12.1. Every address consists of 1-byte to
8-byte data. Data is transferred to or received from the external CPU via the serial interface described
previously.
Table 12.1 Register Table
Description
Byte
width
Remarks
00H
Company ID, Device ID
4
Device Information
10H
Status
2
ST data
Address
READ/
WRITE
11H
4
ST + X-axis data
12H
4
ST + Y-axis data
6
ST + X and Y-axis data
Status
and
Measurement Magnetic Data
13H
14H
15H
16H
17H
READ
4
ST + Z-axis data
6
ST + X and Z-axis data
6
ST + Y and Z-axis data
8
ST + X,Y and Z-axis data
18H
2
ST data
19H
3
ST + X-axis data
1AH
Status
and
Measurement Magnetic Data
(upper 8 bits of measurement data
register)
1BH
1CH
1DH
3
ST + Y-axis data
4
ST + X and Y-axis data
3
ST + Z-axis data
4
ST + X and Z-axis data
1EH
4
ST + Y and Z-axis data
1FH
20H
Control 1
5
2
ST + X,Y and Z-axis data
Interrupt function settings
21H
Control 2
1
Operation Mode, Sensor
Drive, Measurement Range
and Sensitivity
4
4
X-axis threshold 1 settings
X-axis threshold 2 settings
4
Y-axis threshold 1 settings
4
Y-axis threshold 2 settings
4
Z-axis threshold 1 settings
4
Z-axis threshold 2 settings
Soft reset
22H
23H
24H
25H
26H
READ/
WRITE
Control 3
(Switch threshold value)
27H
30H
Reset
1
31H
I2C disable
1
40H
41H
Test
2
DO NOT ACCESS
1
DO NTO ACCESS
Addresses 20h to 27h are compliant with automatic increment function of serial interface respectively.
When the address is in 20h to 27h, the address is incremented 20h Æ 21h Æ 22h Æ 23h ... Æ 27h, and
the address goes back to 20h after 27h.
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12.2. Register Map
Addr.
Byte0
Byte1
00H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
WIA[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
ST[15:8]
WIA[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
ST[7:0]
Table 12.2 Register Map
Byte2
Byte3
Byte4
Read only register
RSV[15:8]
HX[15:8]
HY[15:8]
HY[15:8]
HZ[15:8]
HZ[15:8]
HZ[15:8]
HZ[15:8]
HX[15:8]
HY[15:8]
HY[15:8]
HZ[15:8]
HZ[15:8]
HZ[15:8]
HZ[15:8]
RSV[7:0]
HX[7:0]
HY[7:0]
HY[7:0]
HZ[7:0]
HZ[7:0]
HZ[7:0]
HZ[7:0]
HX[15:8]
HX[15:8]
HY[15:8]
HY[15:8]
HX[15:8]
HX[15:8]
HY[15:8]
HY[15:8]
HX[15:8]
Byte5
Byte6
Byte7
HX[7:0]
HX[7:0]
HY[7:0]
HY[7:0]
-
HX[15:8]
-
HX[7:0]
--
Read/Write register
20H
21H
22H
23H
24H
25H
26H
CNTL1[15:8] CNTL1[7:8]
CNTL2[7:0]
BOP1X[15:8] BOP1X[7:0] BRP1X[15:8] BRP1X[7:0]
-
-
-
-
BOP2X[15:8] BOP2X[7:0] BRP2X[15:8] BRP2X[7:0]
-
-
-
-
BOP1Y[15:8] BOP1Y[7:0] BRP1Y[15:8] BRP1Y[7:0]
-
-
-
-
BOP2Y[15:8] BOP2Y[7:0] BRP2Y[15:8] BRP2Y[7:0]
-
-
-
-
BOP1Z[15:8] BOP1Z[7:0] BRP1Z[15:8] BRP1Z[7:0]
-
-
-
-
27H
BOP2Z[15:8] BOP2Z[7:0] BRP2Z[15:8] BRP2Z[7:0]
-
-
-
-
30H
31H
40H
41H
SRST[7:0]
-
-
-
-
-
-
I2CDIS[7:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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[AK09970N]
Table 12.3 Further details about Register Map (D[7:0])
Register
name
WIA[7:0]
RSV[7:0]
ST[7:0]
HX[7:0]
HY[7:0]
HZ[7:0]
CNTL1[7:0]
CNTL2[7:0]
BOP1X[7:0]
BRP1X[7:0]
BOP2X[7:0]
BRP2X[7:0]
BOP1Y[7:0]
BRP1Y[7:0]
BOP2Y[7:0]
BRP2Y[7:0]
BOP1Z[7:0]
BRP1Z[7:0]
BOP2Z[7:0]
BRP2Z[7:0]
SRST[7:0]
I2CDIS[7:0]
TEST1[7:0]
TEST2[7:0]
7
1
RSV7
ERRXY
HX7
HY7
HZ7
ERRXYEN
0
BOP1X7
BRP1X7
BOP2X7
BRP2X7
BOP1Y7
BRP1Y7
BOP2Y7
BRP2Y7
BOP1Z7
BRP1Z7
BOP2Z7
BRP2Z7
0
I2CDIS7
-
6
1
RSV6
SWZ2
HX6
HY6
HZ6
SWZ2EN
0
BOP1X6
BRP1X6
BOP2X6
BRP2X6
BOP1Y6
BRP1Y6
BOP2Y6
BRP2Y6
BOP1Z6
BRP1Z6
BOP2Z6
BRP2Z6
0
I2CDIS6
-
5
0
RSV5
SWZ1
HX5
HY5
HZ5
SWZ1EN
SMR
BOP1X5
BRP1X5
BOP2X5
BRP2X5
BOP1Y5
BRP1Y5
BOP2Y5
BRP2Y5
BOP1Z5
BRP1Z5
BOP2Z5
BRP2Z5
0
I2CDIS5
-
Bit number (D[7:0])
4
3
0
0
RSV4
RSV3
SWY2
SWY1
HX4
HX3
HY4
HY3
HZ4
HZ3
SWY2EN
SWY1EN
SDR
MODE3
BOP1X4
BOP1X3
BRP1X4
BRP1X3
BOP2X4
BOP2X3
BRP2X4
BRP2X3
BOP1Y4
BOP1Y3
BRP1Y4
BRP1Y3
BOP2Y4
BOP2Y3
BRP2Y4
BRP2Y3
BOP1Z4
BOP1Z3
BRP1Z4
BRP1Z3
BOP2Z4
BOP2Z3
BRP2Z4
BRP2Z3
0
0
I2CDIS4
I2CDIS3
-
2
0
RSV2
SWX2
HX2
HY2
HZ2
SWX2EN
MODE2
BOP1X2
BRP1X2
BOP2X2
BRP2X2
BOP1Y2
BRP1Y2
BOP2Y2
BRP2Y2
BOP1Z2
BRP1Z2
BOP2Z2
BRP2Z2
0
I2CDIS2
-
1
0
RSV1
SWX1
HX1
HY1
HZ1
SWX1EN
MODE1
BOP1X1
BRP1X1
BOP2X1
BRP2X1
BOP1Y1
BRP1Y1
BOP2Y1
BRP2Y1
BOP1Z1
BRP1Z1
BOP2Z1
BRP2Z1
0
I2CDIS1
-
0
0
RSV0
DRDY
HX0
HY0
HZ0
DRDYEN
MODE0
BOP1X0
BRP1X0
BOP2X0
BRP2X0
BOP1Y0
BRP1Y0
BOP2Y0
BRP2Y0
BOP1Z0
BRP1Z0
BOP2Z0
BRP2Z0
SRST
I2CDIS0
-
9
0
RSV9
DOR
HX9
HY9
HZ9
INTEN
BOP1X9
BRP1X9
BOP2X9
BRP2X9
BOP1Y9
BRP1Y9
BOP2Y9
BRP2Y9
BOP1Z9
BRP1Z9
BOP2Z9
BRP2Z9
I2CDIS9
-
8
0
RSV8
ERRADC
HX8
HY8
HZ8
ERRADCEN
BOP1X8
BRP1X8
BOP2X8
BRP2X8
BOP1Y8
BRP1Y8
BOP2Y8
BRP2Y8
BOP1Z8
BRP1Z8
BOP2Z8
BRP2Z8
I2CDIS8
-
Table 12.4 Further details about Register Map (D[15:8])
Register
name
WIA[15:8]
RSV[15:8]
ST[15:8]
HX[15:8]
HY[15:8]
HZ[15:8]
CNTL1[15:8]
CNTL2[15:8]
BOP1X[15:8]
BRP1X[15:8]
BOP2X[15:8]
BRP2X[15:8]
BOP1Y[15:8]
BRP1Y[15:8]
BOP2Y[15:8]
BRP2Y[15:8]
BOP1Z[15:8]
BRP1Z[15:8]
BOP2Z[15:8]
BRP2Z[15:8]
SRST[15:8]
I2CDIS[15:8]
TEST1[15:8]
TEST2[15:8]
15
0
RSV15
1
HX15
HY15
HZ15
0
BOP1X15
BRP1X15
BOP2X15
BRP2X15
BOP1Y15
BRP1Y15
BOP2Y15
BRP2Y15
BOP1Z15
BRP1Z15
BOP2Z15
BRP2Z15
I2CDIS15
-
14
1
RSV14
1
HX14
HY14
HZ14
0
BOP1X14
BRP1X14
BOP2X14
BRP2X14
BOP1Y14
BRP1Y14
BOP2Y14
BRP2Y14
BOP1Z14
BRP1Z14
BOP2Z14
BRP2Z14
I2CDIS14
-
13
0
RSV13
1
HX13
HY13
HZ13
0
BOP1X13
BRP1X13
BOP2X13
BRP2X13
BOP1Y13
BRP1Y13
BOP2Y13
BRP2Y13
BOP1Z13
BRP1Z13
BOP2Z13
BRP2Z13
I2CDIS13
-
Bit number (D[15:8])
12
11
0
1
RSV12
RSV11
1
1
HX12
HX11
HY12
HY11
HZ12
HZ11
0
0
BOP1X12
BOP1X11
BRP1X12
BRP1X11
BOP2X12
BOP2X11
BRP2X12
BRP2X11
BOP1Y12
BOP1Y11
BRP1Y12
BRP1Y11
BOP2Y12
BOP2Y11
BRP2Y12
BRP2Y11
BOP1Z12
BOP1Z11
BRP1Z12
BRP1Z11
BOP2Z12
BOP2Z11
BRP2Z12
BRP2Z11
I2CDIS12
I2CDIS11
-
10
0
RSV10
1
HX10
HY10
HZ10
ODINTEN
BOP1X10
BRP1X10
BOP2X10
BRP2X10
BOP1Y10
BRP1Y10
BOP2Y10
BRP2Y10
BOP1Z10
BRP1Z10
BOP2Z10
BRP2Z10
I2CDIS10
-
When RSTN pin is applied VDD, all registers of AK09970N are initialized.
TEST1 and TEST2 is test register for shipment test. Do not access this register.
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[AK09970N]
12.3. Detailed Description of Registers
12.3.1. WIA[15:0]: Company ID and Device ID
Addr.
00h
Addr.
00h
Register
name
WIA[7:0]
Register
name
WIA[15:8]
D7
D6
1
1
D15
D14
0
D5
D4
Read-only register
0
0
D13
D12
Read-only register
1
0
0
D3
D2
D1
D0
0
0
0
0
D11
D10
D9
D8
1
0
0
0
WIA[7:0] bits: Device ID of AKM. It is described in one byte and fixed value.
C0h: fixed
WIA[15:8] bits: Company ID of AK09970N. It is described in one byte and fixed value.
48h: fixed
12.3.2. RSV[15:0]: Reserved Register
Addr.
00h
Addr.
00h
Register
name
RSV[7:0]
Register
name
RSV[15:8]
D7
RSV7
D15
RSV15
D6
D5
D4
Read-only register
RSV6
RSV5
RSV4
D14
D13
D12
Read-only register
RSV14 RSV13 RSV12
D3
D2
D1
D0
RSV3
RSV2
RSV1
RSV0
D11
D10
D9
D8
RSV11
RSV10
RSV9
RSV8
D3
D2
D1
D0
SWY1
0
SWX2
0
SWX1
0
DRDY
0
D11
D10
D9
D8
1
1
1
1
DOR
0
ERRADC
RSV[7:0] bits/ RSV[15:8] bits: Reserved register for AKM.
12.3.3. ST[15:0]: Status
Addr.
10h-1fh
Addr.
10h-1fh
Register
name
ST[7:0]
Reset
Register
name
ST[15:8]
Reset
D7
ERRXY
0
D15
1
1
D6
D5
D4
Read-only register
SWZ2 SWZ1 SWY2
0
0
0
D14
D13
D12
Read-only register
1
1
1
1
1
1
0
DRDY bit: Data Ready
“0”: Normal
“1”: Data is ready
DRDY bit turns to “1” when data is ready in Single measurement mode and Continuous measurement
mode 1, 2, 3, 4, 5, 6, and 7. It returns to “0” when any one of measurement data register (HX,HY or/and
HZ register) is read all the way through or access to Setting Registers (address 20h to 27h).
DOR bit: Data Overrun
“0”: Normal
“1”: Data overrun
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DOR bit turns to “1” when data has been skipped in Continuous measurement mode 1, 2, 3, 4, 5, 6 or 7.
DOR bit turns to “0” at the after the next measurement ended.
SWX1 bit, SWY1 bit, SWZ1 bit: Measurement data of X, Y and Z-axis exceed switch threshold 1
“0”: Measurement data of X, Y and Z-axis exceed returning threshold 1
“1”: Measurement data of X, Y and Z-axis exceed operating threshold 1
SWX2 bit, SWY2 bit, SWZ2 bit: Measurement data of X, Y and Z-axis exceed switch threshold 2
“0”: Measurement data of X, Y and Z-axis exceed returning threshold 2
“1”: Measurement data of X, Y and Z-axis exceed operating threshold 2
Refer to 10.4 for detailed information.
ERRXY bit: Magnetic sensor overflow
“0”: Normal
“1”: Magnetic sensor overflow occurred (X and/or Y-axis)
Refer to 10.5.1 for detailed information.
ERRADC bit: ADC overflow
“0”: Normal
“1”: ADC overflow occurred and measurement data is not correct
Refer to 10.5.2 for detailed information.
12.3.4. HX[15:0]/HY[15:0]/HZ[15:0]: Measurement Data
Addr.
10h
|
1fh
Addr.
10h
|
1fh
Register
name
HX[7:0]
HY[7:0]
HZ[7:0]
Reset
Register
name
HX[15:8]
HY[15:8]
HZ[15:8]
Reset
D7
D6
HX7
HY7
HZ7
0
HX6
HY6
HZ6
0
D15
D14
HX15
HY15
HZ15
0
D5
D4
Read-only register
HX5
HX4
HY5
HY4
HZ5
HZ4
0
0
D13
D12
Read-only register
HX14
HX13
HX12
HY14
HY13
HY12
HZ14
HZ13
HZ12
0
0
0
D3
D2
D1
D0
HX3
HY3
HZ3
0
HX2
HY2
HZ2
0
HX1
HY1
HZ1
0
HX0
HY0
HZ0
0
D11
D10
D9
D8
HX11
HY11
HZ11
0
HX10
HY10
HZ10
0
HX9
HY9
HZ9
0
HX8
HY8
HZ8
0
Measurement data of magnetic sensor X-axis/Y-axis/Z-axis
HX[7:0] bits: X-axis measurement data lower 8-bit
HX[15:8] bits: X-axis measurement data higher 8-bit
HY[7:0] bits: Y-axis measurement data lower 8-bit
HY[15:8] bits: Y-axis measurement data higher 8-bit
HZ[7:0] bits: Z-axis measurement data lower 8-bit
HZ[15:8] bits: Z-axis measurement data higher 8-bit
Measurement data is stored in two’s complement. Measurement range of each axis is -32768 to 32767
in 16-bit output (High sensitivity setting). Measurement range of X and Y-axis are -11264 to 11264 in
16-bit output, Z-axis is -32768 to 32767 in 16-bit output (Wide range setting).
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Table 12.5 Measurement magnetic data format (High sensitivity setting)
Measurement data (each axis) [15:0] bits
Magnetic flux
ERRXY bit
density [mT]
Two’s complement
Hex
Decimal
0111 1111 1111 1111
7FFF
32767
>36.0437
1
0111 1111 1111 1111
7FFF
32767
36.0437
0
|
|
|
|
|
0000 0000 0000 0001
0001
1
0.0011
0
0000 0000 0000 0000
0000
0
0
0
1111 1111 1111 1111
FFFF
-1
-0.0011
0
|
|
|
|
|
1000 0000 0000 0000
8000
-32768
-36.0448
0
1000 0000 0000 0000
8000
-32768
34.9184
1
0010 1100 0000 0000
2C00
11264
34.9184
0
|
|
|
|
|
0000 0000 0000 0001
0001
1
0.0031
0
0000 0000 0000 0000
0000
0
0
0
1111 1111 1111 1111
FFFF
-1
-0.0031
0
|
|
|
|
|
1101 0100 0000 0000
D400
-11264
-34.9184
0
1101 0100 0000 0000
D400
-11264
101.5777
0111 1111 1111 1110
7FFE
32766
101.5746
|
|
|
|
0000 0000 0000 0001
0001
1
0.0031
0000 0000 0000 0000
0000
0
0
1111 1111 1111 1111
FFFF
-1
-0.0031
|
|
|
|
1000 0000 0000 0001
8001
-32767
-101.5777
1000 0000 0000 0000
8000
-32768
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