AK2307LV

ASAHI KASEI [AK2307/LV] AK2307/LV SPEECH CODEC for Digital Key telephone (5.0V/3.3V) FEATURES GENERAL DISCREPTION - AK2307/LV is an integrated LSI with PCM CODEC, Voice path control, MIC amplifier and Handset driver suitable for PBX/KTS digital key telephone, VoIP Telephone. - PCM CODEC is compliant to ITU specification, very low noise, and low power dissipation CODEC. A-law and u-law selectable through Serial I/F register. PCM I/F provides Long/Short frame format and GCI. The output is 8bit compressed data along with 16bit linear format. - 2 MIC AMP for the handset and microphone are integrated. A 150 ohm handset driver and an extra 150 ohm driver for a headset receiver are provided. Path control and volume control via serial CPU I/F programmable tone generator 5.0V+/-5%, 3.3V+/-0.3V single power supply Low noise, low power consumption Package 28pin VSOP package Voice path block consists of Tone generator, Volume for both TX and RX, Analog inputs, outputs for Handset speaker and the speaker for hands-free conversation, and the path control switch. Side tone can be added internally and its volume is controlled through serial I/F. - Package size; 9.8*7.6mm(pin to pin) - Pin pitch; 0.65mm MS0199-E-04 2005/12 1 ASAHI KASEI [AK2307/LV] BLOCK DIAGRAM Handset Mic I/F HANDT4 upto +25dB HANDT2 HANDT3 TX Digital Attenuator VOL1 HANDT1 +14dB SW1 +14dB SW2 SW3 Amp1 Amp3 16 steps by 1dB +7 to -8dB AGC A/D 8 steps by 3dB 0 to -21dB (Back ground Noise ATT) Linear A/u +0dB External Mic I/F MIC3 MIC1 MIC2 PCM Interface 16 Steps Side Tone by 3dB Digital ATT -12 to -57dB Amp2 PCM CODEC D/A RAIN VOL2 24 steps by 1dB 0 to -23dB Handset Receiver output 0dB/+3dB VOL3 24 steps by 1dB 0 to -23dB + PAD 0/-9dB 8 steps by 3dB +6 to -21dB DX DR FS RX Digital Volume DAOUT 16bit Linear or A/u-law BCLK Linear A/u SW4 SW5 HANDR -1 150ohm Driver Tone Gen H (DTMF-H) VOL4 Headset Receiver output 0dB/+3dB SW6 SW7 Amp5 16 steps by 3dB 0 to -45dB HEADO SW10 150ohm Driver 0dB/+3dB Speaker output Amp10 PLLCAP + L_ATT -2.5dB -1 PLL Clock generator Tone Gen L (DMTF-L) CPU Interface VOL5 16 steps by 2dB 0 to -30dB CSN SCLK DATA VREF SW8 Voltage Reference SW9 SPO TAGND RAGND 10K ohm Driver AVDD AVSS DVDD DVSS EXRIN MS0199-E-04 2005/12 2 ASAHI KASEI [AK2307/LV] PIN ASSIGNMENT HANDR HEADO VSS VDD FS DX BCLK DR DATA SCLK CSN AVDD MIC2 MIC1 1 2 TOP VIEW 3 4 5 6 7 8 9 10 11 12 13 14 MS0199-E-04 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PLLCAP SPO EXRIN RAIN DAOUT RAGND VREF AVSS TAGND HANDT3 HANDT2 HANDT1 HANDT4 MIC3 2005/12 3 ASAHI KASEI [AK2307/LV] PIN CONDITIONS Pin types; NIN: Normal Input NOUT: Normal Output TOUT: Tri-state output AOUT: Analog output PWR: Power supply AIN: Analog Input Table 1 Name HANDT2 HANDT3 HANDT1 HANDT4 HANDR MIC3 MIC2 MIC1 DAOUT RAIN HEADO SPO EXRIN DATA SCLK CSN DR DX BCLK FS DVSS DVDD AVSS AVDD PLLCAP TAGND RAGND VREF Type Max MIn Cap load Res load Pin function comment AIN AIN AOUT AIN AOUT AIN AIN AOUT AOUT AIN AOUT AOUT AIN I/O Analog input for Handset microphone Analog input for Handset microphone OPamp output for Handset microphone Analog input for A/D converter Analog output for Handset receiver 1000pF 150ohm nd 2 Analog input for A/D converter Analog input for External microphone Output of External microphone amplifier Analog output of D/A converter Analog input to RX voice path RX output for Headset receiver 1000pF 150ohm RX output for External Speaker Driver 20pF 10kohm External input for Speaker pre-driver Data input for internal register access 50pF Serial data clock for internal register NIN access NIN Chip select input NIN RX PCM data serial input TOUT TX PCM data serial output. Tri-state output 50pF NIN Bit clock input for DR, DX NIN 8KHz frame sync signal input for PCM I/F PWR Power supply for digital block:0V PWR Power supply for digital block: 3.3V PWR Power supply for Analog block:0V PWR Power supply for Analog block: 3.3V Output to connect the PLL loop filter 1.0uF external AOUT Capacitance capacitance 1.0uF external AOUT TX side Analog ground output. capacitance 1.0uF external AOUT RX side Analog ground output capacitance 1.0uF external AOUT Voltage reference output capacitance MS0199-E-04 2005/12 4 ASAHI KASEI [AK2307/LV] ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Power Supply Voltages Analog/Digital Power Supply VDD -0.3 6.5 VSS Voltage VSS -0.1 0.1 Digital Input Voltage VTD -0.3 VDD+0.3 Analog Input Voltage VTA -0.3 VDD+0.3 Input current (except power supply pins) IIN -10 10 Storage Temperature Tstg -55 125 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes. Units V V V V mA o C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supplies Analog/Digital power supply( AK2307LV) VDD Analog/Digital power supply( AK2307) VDD Ambient Operating Temperature Ta Frame Sync Frequency FS Note) All voltages reference to ground : VSS=0V MS0199-E-04 Min Typ Max Units 3.0 4.75 -10 - 3.3 5.0 3.6 5.25 85 - V V o C kHz 8 2005/12 5 ASAHI KASEI [AK2307/LV] FUNCTIONAL DISCRIPTIONS 1. SERIAL INTERFACE The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN pin. 1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write. The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers. Table1-A CPU I/F ADDRESS/DATA STRUCTURE B15 B14 B13 B12 B11 B10 B9 B8 I2 I1 I0 A3 Instruction code (3 bit ) A2 A1 A0 Address (4bit) * B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 * Data for internal registers (8bit) *)Dummy bit for adjusting the I/O timing when reading register. Table1-B INSTRUCTION CODE I2 I1 I0 1 1 0 1 1 1 Read/Write Read Write No action Others 1-2 Timing of the Serial Interface SCLK and DATA timing in WRITE/READ operation (1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CSN. (3) When CSN is “L” and more than 16 SCLK pulses: th [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16 pulse. th [READ] DATA pin becomes an input pin at the falling edge of the SCLK 16 pulse. CSN timing and WRITE/READ CANCELLATION th (1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse. th (2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse. SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE) (1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and st data after 1 write or read operation. st nd (2) It is not necessary to make CSN high between 1 operation and 2 operation. MS0199-E-04 2005/12 6 ASAHI KASEI [AK2307/LV] WRITE Continuous SCLK Goes up anytime after SCLK 16th pulse and before 32nd pulse CSN SCLK 1 Z DATA 2 1 3 1 4 1 5 0 6 0 Instruction Code 7 0 8 0 9 16 D7 * Z D0 Write data to address”000” Address “0000” 1 2 1 WRITE at the rising edge of SCLK 16th pulse 1 3 4 8 1 9 D7 15 D1 16 D0 Z Write data Instruction Code Burst SCLK SCLK can be stoped at “H” level or “L” level at anytime during the write cycle. After resuming the SCLK, write cycle is retrieved normally. Goes up anytime after SCLK 16th pulse and 32nd pulse CSN SCLK 1 Z DATA 2 1 3 1 4 1 5 0 6 0 Instruction Code 7 0 8 0 9 16 D7 * D0 Write data to address “000” Address ”0000” Z WRITE at the rising edge of SCLK 16th pulse CANCELLATION CSN goes “H” before the rising edge of 16th SCLK pulse CSN SCLK DATA 1 Z 1 2 1 3 1 Instruction Code 4 0 5 0 6 0 Address ”0000” 7 0 8 * 9 D7 16 Z D0 Write data to address”000” Write is not Excuted MS0199-E-04 Z DATA pin: Input mode (Hi-Z) 2005/12 7 ASAHI KASEI [AK2307/LV] SERIAL ACCESS Serial access can be done by CSN staying “L” during the serise of write cycle. CSN SCLK DATA 1 Z 1 2 1 3 1 4 0 5 0 6 0 7 0 8 D7 * Address ”0000” Instruction Code 9 16 1 Z D0 1 Write data to Address”000” 2 3 1 1 8 4 1 9 15 16 Z D1 D0 D7 Write data Instruction Code EXCUTE! EXCUTED! READ Continuous SCLK Can be going up at anytime after SCLK 16th pulse and before 32nd pulse CSN SCLK DATA 1 Z 1 2 1 3 0 4 5 A3 A2 Read Instruction 6 7 A1 A0 8 Z 9 D7 16 1 Z D0 1 Read Data Address 2 1 3 1 4 0 Read Instruction 8 9 D7 15 16 D1 D0 Z Read Data Read period until the earlier edge of either CSN rising or SCLK 16th pulse falling Data output starts at the falling edge of SCLK 8th pulse Burst SCLK Can be going up at anytime after SCLK 16th pulse and before 32nd pulse CSN SCLK DATA 1 Z 1 2 1 3 0 Read Instruction 4 5 A3 A2 6 7 A1 A0 Address 8 Z 9 16 D0 D7 Z Read Data Read output starts at the falling edge of SCLK 8th pulse MS0199-E-04 2005/12 8 ASAHI KASEI [AK2307/LV] SERIAL ACCESS Serial access can be done by CSN staying “L” during the serise of read cycle CSN SCLK DATA 1 Z 1 2 1 3 0 4 5 0 0 6 7 0 0 Z 9 D7 16 1 Z D0 2 1 Read data Address ”0000” Read Instruction 8 1 3 1 4 8 9 15 16 Z 0 Read Instruction READ EXCUTED! READ EXCUTED! DISCORD OF INSTRUCTION CODE CSN SCLK DATA Z 1 2 3 4 5 I2 I1 I0 IA3 A2 IInstructions except specified 0bb 10b (b=0 or 1) 6 7 8 9 16 Z A1 A0 Address WRITE/READ NOT EXCUTED! Z DATA pin: Input mode (Hi-Z) Register Map Register Type : Read/ Write Register Name (Functions) SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 Path Control 1 RX_ RX Pad Side PCM_1 PCM_0 u/A-law SW10 SW9 Path Control 2 & A_gain -9dB Tone PCM Control 2 0 TX Attenuator VOL1 TX Digital Volume Control 3 RX Volume Side Tone Attenuator RX Digital Volume Control 4 0 0 0 0 VOL4 Tone Volume Control 5 0 0 Tone Freq. Select Tone Generator 1 6 0 L-ATT Tone Freq. Select Tone Generator 2 7 0 0 0 VOL2 RX Handset Volume Control 8 0 0 0 VOL3 RX Headset Volume Control 9 VOL5 RX Speaker Volume Control A AGC_ON Falling time Rising time Threshold level AGC Control B–F Reserved for test use Address “1” ; PCM_1/2 ---- Selection of the PCM interface Mode(Long/Short frame, AK130-1,AK130-2, 16bit linear) Address ”6” ; L-ATT ---- -6dB attenuation for Tone generator-L output in case of DTMF tone generation. Add (Hex) 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Bits in which “0” is filled are for test mode activation. Please fill the data “0” for the normal operation. Bits in which “-“ is filled are for test use and can not write the data from CPU interface. In case the read operation, data “0” are read from CPU interface. MS0199-E-04 2005/12 9 ASAHI KASEI 2. PCM Data Interface [AK2307/LV] AK2307/LV supports 4 PCM data interface modes. - A/u-Law PCM data mode( Long or Short frame) This mode is for interface of 64kbps PCM data which are compressed /extended by A -law or u-law. Both Long frame and short frame format data are acceptable. The PCM data occupies the first time slot of the PCM data bus which is specified by the frame sync signal. Please refer to the format diagram. - 16 bit Linear data Mode This mode interfaces the 16 bit linear PCM data. PCM CODEC of AK2307/LV operates at 14 bit accuracy. The 2 bits of the LSB are fixed in the 16 bit data stream. - AK130 B1 Mode This mode provides the PCM data Interface to AK130, the TCM transceiver for PBX/KTS system. PCM da ta format is 64kbps A-law or u-law data. The timing between data and FS is different from the A/u -Law PCM data mode written above. In this mode the PCM data are transmitted/received via B1 channel , one of the PCM data channel of the AK130. - AK130 B2 Mode This mode provides the PCM data interface to AK130 B2 channel in as same manner as AK130 B1 Mode. In every modes, the digital voice data are in and out from DR and DX pin and the bit clock and the 8KHz frame sync signal will be fed via BCLK and FS, respectively. The order of PCM and linear data is MSB first . Table 2-A Summary of PCM interface modes Mode PCM data format BCLK rate frame signal Time slot A/u-Law PCM data mode 16bit Linear data mode AK130 B1 mode AK130 B2 mode A/u-Law A/u-Law 2.048MHz LF/SF auto select SF only AK130 FS signal AK130 FS signal 1 Time slot 16bit Linear A/u-Law 64K x N (N: 1 to 32) 128K x N (N: 1 to 16) 2.048MHz st first 16 bit after FS signal xxth time slot of 2.048MHz(B1 channel) xxth time slot of 2.048MHz(B2 channel) 2-1. Selection of the interface mode These four interface modes are selectable through the CPU register which specified below. A/u-Law selection is also selectable from the same CPU register and it is effective in the u/ A-law interface mode and AK130 B1/B2 modes. Register Name; Path Control 2 ADD D7 D6 RX 1 Default 0 Register Type : Read Write D5 D4 D3 D2 D1 D0 PCM_1 PCM_0 u/A law SW10 SW9 Pad Side Tone 0 0 0 0 0 0 0 PCM_1、0 ； PCM interface mode select PCM_1 PCM_0 Mode 0 0 A/u-Law PCM data mode 0 1 16bit Linear interface mode 1 0 AK130 B1 mode 1 1 AK130 B2 mode u/A-law ; PCM compress/Extend format select A/u-law Compress/Extend 0 u-law 1 A-law MS0199-E-04 2005/12 10 ASAHI KASEI [AK2307/LV] 2-2 Timing and format of the PCM interface 2-2-1 u/A-Law PCM data Mode 8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2307/LV occupies first time slot as is indicated in figures below. 2-2-1-a Signals - Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock of the LSI is generated based on this FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 64kHz to 2.048MHz by 64kHz step. - PCM data output (DX) DX is an output signal of 64Kbps PCM u/A -law data. The data is synchronized to the BCLK which determines th e data rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. In the long frame mode, th the LSB bit turns to Hi-impedance at the faster edge of ether FS falling edge or 9 rising edge of BCLK. - PCM data input (DR) DR is an input signal of 64Kbps PCM u/A -law data. The data is clocked by BCLK at the falling edge and fed into the D/A block. 2-2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection AK2307/LV monitors the duration of the “H” level of FS and automatically selects LF or SF interface format. period of FS=”H” Interface format more than 2 clocks of BCK LF 1 clock of BCK SF 2-2-1-c Frame format of the interface Long Frame format 1 2 5 u s (8 K H z ) FS BCLK DX DR 7 D o n ’t c a re 7 6 6 5 5 4 4 3 3 2 2 1 1 0 D o n ’t c a r e 0 Short Frame format 1 2 5 u s (8 K H z ) FS BCLK DX DR 7 D o n ’t c a re 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 MS0199-E-04 D o n ’t c a re 2005/12 11 ASAHI KASEI [AK2307/LV] 2-2-2 16 bit Linear PCM data mode In this mode the 16 bit linear PCM data are interfaced to the outside. This mode is useful to compress/extend the PCM data by much higher compress rate algorithm than u/A -law algorithm by the external DSP. The AK2307/LV CODEC operates at 14bit accuracy, thus the least 2 bits are output as fixed value. 2-2-2-a Signals - Frame Sync signal (FS) 8kHz reference signal which is same as in u/A -law PCM data mode. How the FS pulse H level width should be 1 clo ck period which is like the short frame FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 2.048MHz by 128kHz step which is different from in the u/A-law PCM data mode. - PCM data output (DX) DX is an output signal of 128Kbps linear PCM data. The data is synchronized to the BCLK which determines the data rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. - PCM data input (DR) DR is an input signal of 128Kbps linear PCM data. The data is clocked by BCLK at the falling edge and fed into the D/A block. 16bti Linear Frame format 125us (8KHz) FS BCLK DX DR Hi-Z MSB First 1 2 3 12 13 14 * MSB First 1 2 3 12 13 14 Hi-Z * * * Hi-Z * 1 2 2-2-3 AK130 B1/B2 Mode These modes are for connecting the PCM interface to AK130, AKM ’s TCM( ping-pong ) transceiver for PBX/KTS system. The PCM data format is A-law or u-law which can be selected by the register. The AK130 B1 mode interfaces the data to B1 channel which is one of two B channels which AK130 provides, and the AK130 B2 mode interfaces to B2 chann el. 2-2-3-a Signals - Frame Sync signal (FS) ___ Please feed the FS signal which is generated by AK130.( F0o , pin#3 ) - Bit Clock (BCLK) BCLK defines the PCM data rate. Please use 2.048MHz clock which is generated by AK130 .( E2o,pin#5 ) - PCM data output (DX) DX is an output signal of 128Kbps linear PCM data. Please connect to the PCM data input pin of AK130.( DSTi,pin#11 ) - PCM data input (DR) DR is an input signal of 128Kbps linear PCM data. The data is clocked by BCLK at the falling edge and fed into the D/A block. Please connect to the PCM data output pin of AK130.( DSTo,pin#6 ) MS0199-E-04 2005/12 12 ASAHI KASEI [AK2307/LV] AK130 B1 Mode 244ns 125us(8kHz) FS BCLK 16CLK 8CLK MSB First Hi-Z DX DR * * * 7 * * * 7 6 2 MSB First 6 1 Hi-Z 0 1 0 * * * * Note)*：Don't care AK130 B2 Mode 244ns 125us(8kHz) FS BCLK 24CLK 8CLK MSB First Hi-Z DX DR * * * 7 * * * 7 6 MSB First 6 2 1 1 Hi-Z 0 0 * * * * Note)*：Don't care MS0199-E-04 2005/12 13 ASAHI KASEI 3. Path and Gain Controls [AK2307/LV] Voice path, gain control of both RX and TX side, and the tone control are controlled from the CPU registers. 3-1. Path control switches; AK2307/LV has 10 analog switches to control the RX and TX analog path. These switches are controlled from following 2 registers, Path control 1/2. Path Control 1 Register Type : Read Write[Address:0000 D7-D0:(SW8-SW1)] ADD D7 D6 D5 D4 D3 D2 0 SW8 SW7 SW6 SW5 SW4 SW3 Default 0 0 0 0 0 0 D1 SW2 0 D0 SW1 0 Path Control 2 Register Type : Read Write[Address:0001 D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)] ADD D7 D6 D5 D4 D3 D2 D1 D0 1 RX RX Side PCM_1 PCM_0 u-law SW10 SW9 _Apad _Pad Tone A-law Default 0 1 0 0 0 0 0 0 Table3-a Switch function SW Name SW10 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 Function External voice input enable for Speaker RX Tone output enable for Speaker RX Voice path enable for Speaker RX Tone output enable for Headset RX Voice path enable for Headset RX Tone output enable for Handset RX Voice path enable for Handset TX Tone output enable TX MIC path enable TX Handset path enable MS0199-E-04 Polarity 1: External input path 0: Internal Voice path 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Tone output ON 0: Tone output OFF 1: MIC input ON 0: MIC input OFF 1: Handset path ON 0: Handset path OFF 2005/12 14 ASAHI KASEI [AK2307/LV] 3-2 Voice path gain Controls AK2307/LV provides the RX and TX voice gain control functions both in analog domain and in digital domain. These gain can be controlled from following five registers. 3-2-1. RX voice path gain controls RX side voice path has three gain control blocks and two gain Pads. These gain stages are controlled through following four registers, Path Control 2, RX digital Volume control, RX handset control, RX Headset control and RX speaker control. Path Control 2 Register Type : Read Write[Address:0001 D6-D5,D1-D0:(RX_Pad, Side_Tone,SW10-SW9)] ADD D7 D6 D5 D4 D3 D2 D1 D0 1 RX RX Side PCM_1 PCM_0 u-law SW10 SW9 _Apad _Pad Tone A-law Default 0 1 0 0 0 0 0 0 RX_Apad ; Analog +3dB gain pad at three RX voice output amps. This gain for to get the extra gain in the RX level diagram. This means, for example, the analog output will be equivalent to one correspond to –7dBm0 digital code when this gain is enabled. However, please notice the maximum analog output can not exceed the one which is defined in analog characteristics specification. The three gain stages at each output can not be changed individually. Name Porarity Comment RX_Apad 0 0dB 1 +3dB default RX_Pad; A digital –9dB gain pad at D/A digital domain. This gain pad is for a gain adjustment between the in-system call and the external call. Name Porarity Comment RX_Pad 0 0dB 1 -9dB default MS0199-E-04 2005/12 15 ASAHI KASEI [AK2307/LV] RX Digital Volume Control Register Type : Read Write[Address:0011 D7-D0(VTX3-VTX0, VSD_3-VSD_0)] ADD D7 D6 D5 D4 D3 D2 D1 D0 3 VRX3 VRX2 VRX1 VRX0 VSD_3 VSD_2 VSD_1 VSD_0 Default 0 1 1 1 1 1 1 1 VRX[3-0]; RX side digital volume from +6dB to –21dB by 3dB step. when VRX3=1 Gain[dB]＝ 3 x VRX[2-0] (VRX[2-0]=1 or 2) VRX3=0 Gain[dB]＝ - 3×VRX[2-0] VRX3 VRX2 VRX1 VRX0 RX digital Attenuator Comment 0 0 0 0 0dB Ref level=0dBm0 0 0 0 1 -3dB 0 0 1 0 -6dB 0 0 1 1 -9dB 0 1 0 0 -12dB 0 1 0 1 -15dB 0 1 1 0 -18dB 0 1 1 1 -21dB 1 0 0 0 NA 1 0 0 1 +3dB 1 0 1 0 +6dB 1 0 1 1 NA 1 1 0 0 NA 1 1 0 1 NA 1 1 1 0 NA 1 1 1 1 NA default NA ; Not applicable MS0199-E-04 2005/12 16 ASAHI KASEI [AK2307/LV] RX Handset Volume Control ( Vol 2 ) Register Type : Read Write [Address:0111 D4-D0(V2_4-V2_0)] ADD D7 D6 D5 D4 D3 D2 7 V2_4 V2_3 V2_2 default 0 0 0 1 1 1 D1 V2_1 1 D0 V2_0 1 V2_[4-0]; Analog volume for the RX side Handset output. The gain is variable from 0dB to –23dB by 1 dB step. Gain[ dB ] = -V2[dB] (when 0