AK4114VQ

ASAHI KASEI [AK4114] AK4114 High Feature 192kHz 24bit Digital Audio Interface Transceiver GENERAL DESCRIPTION The AK4114 is a digital audio transceiver supporting 192kHz, 24bits. The channel status decoder supports both consumer and professional modes. The AK4114 can automatically detect a Non-PCM bit stream. When combined with the multi channel codec (AK4527B or AK4529), the two chips provide a system solution for AC-3 applications. The dedicated pins or a serial µP I/F can control the mode setting. The small package, 48pin LQFP saves the system space. *AC-3 is a trademark of Dolby Laboratories. FEATURES † AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible † Low jitter Analog PLL † PLL Lock Range : 32kHz to 192kHz † Clock Source: PLL or X'tal † 8-channel Receiver input † 2-channel Transmission output (Through output or DIT) † Auxiliary digital input † De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz † Detection Functions • Non-PCM Bit Stream Detection • DTS-CD Bit Stream Detection • Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) • Unlock & Parity Error Detection • Validity Flag Detection † Up to 24bit Audio Data Format † Audio I/F: Master or Slave Mode † 40-bit Channel Status Buffer † Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream † Q-subcode Buffer for CD bit stream † Serial µP I/F † Two Master Clock Outputs: 64fs/128fs/256fs/512fs † Operating Voltage: 2.7 to 3.6V with 5V tolerance † Small Package: 48pin LQFP † Ta: -10 to 70°C MS0098-E-04 2004/03 -1- ASAHI KASEI [AK4114] AVSS AVDD R XTI XTO RX0 X'tal Clock Recovery RX1 RX2 8 to 3 RX3 RX4 Input RX5 Oscillator Clock MCKO1 Generator MCKO2 Selector DEM RX6 RX7 DAIF Audio Decoder I/F LRCK BICK SDTO TX0 DAUX TX1 PDN DIT CSN DVDD AC-3/MPEG DVSS TVDD Detect VIN B,C,U,VOUT Error & Q-subcode STATUS Detect buffer CDTO CDTI P/S=”L” IIC INT1 INT0 µP I/F CCLK Serial Control Mode AVSS AVDD RX0 RX1 RX2 R XTI XTO X'tal 4 to 2 Clock Recovery Input Selector Oscillator RX3 IPS0 Clock MCKO1 Generator MCKO2 DEM DIF0 DIF1 DAIF DIF2 Decoder Audio I/F LRCK BICK SDTO TX0 DAUX TX1 DIT PDN OCKS0 DVDD AC-3/MPEG OCKS1 DVSS TVDD Error & STATUS Detect Detect CM1 VIN B,C,U,VOUT INT0 INT1 CM0 P/S=”H” IPS1 Parallel Control Mode MS0098-E-04 2004/03 -2- ASAHI KASEI [AK4114] „ Ordering Guide -10 ~ +70 °C AK4114VQ 48pin LQFP (0.5mm pitch) TEST1 RX1 AVSS RX0 AVSS VCOM R AVDD INT1 43 42 41 40 39 38 37 RX2 46 44 AVSS 47 45 RX3 48 „ Pin Layout IPS0/RX4 1 36 INT0 AVSS 2 35 OCKS0/CSN/CAD0 DIF0/RX5 3 34 OCKS1/CCLK/SCL TEST2 4 33 CM1/CDTI/SDA AK4114VQ DIF1/RX6 5 32 CM0/CDTO/CAD1 AVSS 6 31 PDN 7 30 XTI DIF2/RX7 Top View IPS1/IIC 8 29 XTO P/SN 9 28 DAUX 24 LRCK 21 DVDD 22 20 VOUT 23 19 UOUT DVSS 18 COUT MS0098-E-04 MCKO1 17 TX1 SDTO BOUT 25 16 12 15 VIN TX0 BICK 14 MCKO2 26 13 27 NC 10 11 TVDD XTL0 XTL1 2004/03 -3- ASAHI KASEI [AK4114] PIN/FUNCTION No. Pin Name IPS0 RX4 I/O I I 2 NC(AVSS) I 3 DIF0 RX5 I I 4 TEST2 I 5 DIF1 RX6 I I 6 NC(AVSS) I DIF2 RX7 IPS1 I I I IIC I 9 P/SN I 10 11 12 13 XTL0 XTL1 VIN TVDD I I I I 14 NC I 15 TX0 O 16 TX1 O 17 BOUT O 18 19 20 21 22 23 24 25 26 27 28 29 30 COUT UOUT VOUT DVDD DVSS MCKO1 LRCK SDTO BICK MCKO2 DAUX XTO XTI 1 7 8 O O O I I O I/O O I/O O I O I Function Input Channel Select 0 Pin in Parallel Mode Receiver Channel 4 Pin in Serial Mode (Internal biased pin) No Connect No internal bonding. This pin should be connected to AVSS. Audio Data Interface Format 0 Pin in Parallel Mode Receiver Channel 5 Pin in Serial Mode (Internal biased pin) TEST 2 pin This pin should be connect to AVSS. Audio Data Interface Format 1 Pin in Parallel Mode Receiver Channel 6 Pin in Serial Mode (Internal biased pin) No Connect No internal bonding. This pin should be connected to AVSS. Audio Data Interface Format 2 Pin in Parallel Mode Receiver Channel 7 Pin in Serial Mode (Internal biased pin) Input Channel Select 1 Pin in Parallel Mode IIC Select Pin in Serial Mode. “L”: 4-wire Serial, “H”: IIC Parallel/Serial Select Pin “L”: Serial Mode, “H”: Parallel Mode X’tal Frequency Select 0 Pin X’tal Frequency Select 1 Pin V-bit Input Pin for Transmitter Output Input Buffer Power Supply Pin, 3.3V or 5V No Connect No internal bonding. This pin should be open or connected to DVSS. Transmit Channel (Through Data) Output 0 Pin When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin. When TX bit = “1”, Transmit Channel (DAUX Data) Output Pin (Default). Block-Start Output Pin for Receiver Input “H” during first 40 flames. C-bit Output Pin for Receiver Input U-bit Output Pin for Receiver Input V-bit Output Pin for Receiver Input Digital Power Supply Pin, 3.3V Digital Ground Pin Master Clock Output 1 Pin Channel Clock Pin Audio Serial Data Output Pin Audio Serial Data Clock Pin Master Clock Output 2 Pin Auxiliary Audio Data Input Pin X'tal Output Pin X'tal Input Pin MS0098-E-04 2004/03 -4- ASAHI KASEI [AK4114] PIN/FUNCTION (Continued) No. Pin Name I/O Function Power-Down Mode Pin 31 PDN I When “L”, the AK4114 is powered-down and reset. CM0 I Master Clock Operation Mode 0 Pin in Parallel Mode 32 CDTO O Control Data Output Pin in Serial Mode, IIC= “L”. CAD1 I Chip Address 1 Pin in Serial Mode, IIC= “H”. CM1 I Master Clock Operation Mode 1 Pin in Parallel Mode 33 CDTI I Control Data Input Pin in Serial Mode, IIC= “L”. SDA I/O Control Data Pin in Serial Mode, IIC= “H”. OCKS1 I Output Clock Select 1 Pin in Parallel Mode 34 CCLK I Control Data Clock Pin in Serial Mode, IIC= “L” SCL I Control Data Clock Pin in Serial Mode, IIC= “H” OCKS0 I Output Clock Select 0 Pin in Parallel Mode 35 CSN I Chip Select Pin in Serial Mode, IIC=”L”. CAD0 I Chip Address 0 Pin in Serial Mode, IIC= “H”. 36 INT0 O Interrupt 0 Pin 37 INT1 O Interrupt 1 Pin 38 AVDD I Analog Power Supply Pin, 3.3V External Resistor Pin 39 R 18kΩ +/-1% resistor should be connected to AVSS externally. Common Voltage Output Pin 40 VCOM 0.47µF capacitor should be connected to AVSS externally. 41 AVSS I Analog Ground Pin Receiver Channel 0 Pin (Internal biased pin) 42 RX0 I This channel is default in serial mode. No Connect 43 NC(AVSS) I No internal bonding. This pin should be connected to AVSS. 44 RX1 I Receiver Channel 1 Pin (Internal biased pin) TEST 1 pin. 45 TEST1 I This pin should be connected to AVSS. 46 RX2 I Receiver Channel 2 Pin (Internal biased pin) No Connect 47 NC(AVSS) I No internal bonding. This pin should be connected to AVSS. 48 RX3 I Receiver Channel 3 Pin (Internal biased pin) Note 1. All input pins except internal biased pins should not be left floating. MS0098-E-04 2004/03 -5- ASAHI KASEI [AK4114] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 2) Parameter Symbol min max Power Supplies: Analog AVDD -0.3 4.6 Digital DVDD -0.3 4.6 Input Buffer TVDD -0.3 6.0 |AVSS-DVSS| (Note 3) 0.3 ∆GND Input Current (Any pins except supplies) IIN ±10 Input Voltage (Except XTI pin) VIN -0.3 TVDD+0.3 Input Voltage (XTI pin) VINX -0.3 DVDD+0.3 Ambient Temperature (Power applied) Ta -10 70 Storage Temperature Tstg -65 150 Note 2. All voltages with respect to ground. Note 3. AVSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 2) Parameter Symbol min typ Power Supplies: Analog AVDD 2.7 3.3 Digital DVDD 2.7 3.3 Input Buffer TVDD DVDD 3.3 Note 2. All voltages with respect to ground. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol min typ Input Resistance Zin 10 Input Voltage VTH 200 Input Hysteresis VHY 50 Input Sample Frequency fs 32 - Units V V V V mA V V °C °C max 3.6 AVDD 5.5 Units V V V max Units kΩ mVpp mV kHz 192 DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation: PDN = “H” (Note 4) 28 56 mA Power down: PDN = “L” (Note 5) 10 100 µA High-Level Input Voltage VIH 70%DVDD TVDD V Low-Level Input Voltage VIL DVSS-0.3 30%DVDD V VOH DVDD-0.4 V High-Level Output Voltage (Iout=-400µA) Low-Level Output Voltage VOL 0.4 V (Except SDA pin: Iout=400µA) VOL 0.4 V ( SDA pin: Iout= 3mA) Input Leakage Current Iin ± 10 µA Note 4. AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=192kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1=1, OCKS0=1. AVDD=11mA (typ), DVDD=17mA (typ), TVDD=10µA (typ). DVDD=28mA (typ) when the circuit of Figure 22 is attached to both TX0 and TX1 pins. Note 5. RX inputs are open and all digital input pins are held DVDD or DVSS. MS0098-E-04 2004/03 -6- ASAHI KASEI [AK4114] SWITCHING CHARACTERISTICS (Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 External Clock Frequency fECLK 11.2896 Duty dECLK 40 MCKO1 Output Frequency fMCK1 4.096 Duty dMCK1 40 MCKO2 Output Frequency fMCK2 2.048 Duty dMCK2 40 PLL Clock Recover Frequency (RX0-7) fpll 32 LRCK Frequency fs 32 Duty Cycle dLCK 45 Audio Interface Timing Slave Mode BICK Period tBCK 80 BICK Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 20 tLRB LRCK Edge to BICK “↑” (Note 6) tBLR 20 BICK “↑” to LRCK Edge (Note 6) tLRM LRCK to SDTO (MSB) tBSD BICK “↓” to SDTO 20 tDXH DAUX Hold Time tDXS 20 DAUX Setup Time Master Mode BICK Frequency fBCK BICK Duty dBCK tMBLR -20 BICK “↓” to LRCK tBSD BICK “↓” to SDTO tDXH 20 DAUX Hold Time tDXS 20 DAUX Setup Time Control Interface Timing (4-wire serial mode) 200 tCCK CCLK Period tCCKL 80 CCLK Pulse Width Low 80 tCCKH Pulse Width High 50 tCDS CDTI Setup Time 50 tCDH CDTI Hold Time tCSW 150 CSN “H” Time 50 tCSS CSN “↓” to CCLK “↑” tCSH 50 CCLK “↑” to CSN “↑” tDCD CDTO Delay tCCZ CSN “↑” to CDTO Hi-Z typ 50 50 50 - max Units 24.576 24.576 60 24.576 60 24.576 60 192 192 55 MHz MHz % MHz % MHz % kHz kHz % 30 30 64fs 50 20 10 45 70 ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 6. BICK rising edge must not occur at the same time as LRCK edge. MS0098-E-04 2004/03 -7- ASAHI KASEI [AK4114] SWITCHING CHARACTERISTICS (Continued) (Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ Control Interface Timing (I2C Bus mode): fSCL SCL Clock Frequency 4.7 tBUF Bus Free Time Between Transmissions 4.0 tHD:STA Start Condition Hold Time (prior to first clock pulse) 4.7 tLOW Clock Low Time 4.0 tHIGH Clock High Time 4.7 tSU:STA Setup Time for Repeated Start Condition 0 tHD:DAT SDA Hold Time from SCL Falling (Note 7) 250 tSU:DAT SDA Setup Time from SCL Rising tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines 4.0 tSU:STO Setup Time for Stop Condition Cb Capacitive load on bus Reset Timing PDN Pulse Width tPW 150 Note 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 8. I2C is a registered trademark of Philips Semiconductors. max Units 100 - kHz µs µs 1000 300 400 µs µs µs µs ns ns ns µs pF ns Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips. MS0098-E-04 2004/03 -8- ASAHI KASEI [AK4114] „ Timing Diagram 1/fECLK VIH XTI VIL tECLKH tECLKL dECLK = tECLKH x fECLK x 100 = tECLKL x fECLK x 100 1/fMCK1 MCKO1 50%DVDD tMCKH1 tMCKL1 dMCK1 = tMCKH1 x fMCK1 x 100 = tMCKL1 x fMCK1 x 100 1/fMCK2 MCKO2 50%DVDD tMCKH2 tMCKL2 dMCK2 = tMCKH2 x fMCK2 x 100 = tMCKL2 x fMCK2 x 100 1/fs VIH LRCK VIL tLRH tLRL dLCK = tLRH x fs x 100 = tLRL x fs x 100 Figure 1. Clock Timing VIH LRCK VIL tBCK tBLR tLRB tBCKL tBCKH VIH BICK VIL tLRM tBSD 50%DVDD SDTO tDXS tDXH VIH DAUX VIL Figure 2. Serial Interface Timing (Slave Mode) MS0098-E-04 2004/03 -9- ASAHI KASEI [AK4114] LRCK 50%DVDD tMBLR 50%DVDD BICK tBSD 50%DVDD SDTO tDXS tDXH VIH DAUX VIL Figure 3. Serial Interface Timing (Master Mode) VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS CDTI CDTO C1 C0 R/W A4 VIH VIL Hi-Z Figure 4. WRITE/READ Command Input Timing in 4-wire serial mode MS0098-E-04 2004/03 - 10 - ASAHI KASEI [AK4114] tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO Figure 5. WRITE Data Input Timing in 4-wire serial mode VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD Hi-Z CDTO D7 D6 D5 50%DVDD Figure 6. READ Data Output Timing 1 in 4-wire serial mode tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 D0 50%DVDD Figure 7. READ Data Input Timing 2 in 4-wire serial mode MS0098-E-04 2004/03 - 11 - ASAHI KASEI [AK4114] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Figure 8. I2C Bus mode Timing tPW PDN VIL Figure 9. Power Down & Reset Timing MS0098-E-04 2004/03 - 12 - ASAHI KASEI [AK4114] OPERATION OVERVIEW „ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection The AK4114 has a Non-PCM steam auto-detection function. When the 32bit mode Non-PCM preamble based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the AUTO bit goes “1”. The 96bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “1”. Once the AUTO is set “1”, it will remain “1” until 4096 frames pass through the chip without additional sync pattern being detected. When those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers. The AK4114 also has the DTS-CD bitstream auto-detection function. When AK4114 detects DTS-CD bitstreams, DTSCD bit goes to “1”. When the next sync code does not come within 4096 flames, DTSCD bit goes to “0” until when AK4114 detects the stream again. „ 192kHz Clock Recovery On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4114 has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel status, AK4114 detects the sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz). The PLL loses lock when the received sync interval is incorrect. „ Master Clock The AK4114 has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and OCKS1 as shown in Table 1. The 512fs clock will not output when 96kHz and 192kHz. The 256fs clock will not output when 192kHz. No. 0 1 2 3 OCKS1 0 0 1 1 OCKS0 0 1 0 1 MCKO1 256fs 256fs 512fs 128fs MCKO2 256fs 128fs 256fs 64fs X’tal 256fs 256fs 512fs 128fs fs (max) 96 kHz 96 kHz 48 kHz 192 kHz Default Table 1. Master Clock Frequency Select (Stereo mode) „ Clock Operation Mode The CM0/CM1 pins (or bits) select the clock source and the data source of SDTO. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored. For Mode2 and 3, it is recommended that the frequency of X’tal is different from the recovered frequency from PLL. Mode 0 1 CM1 0 0 CM0 0 1 UNLOCK PLL X'tal Clock source SDTO ON ON(Note) PLL RX Default OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off. Table 2. Clock Operation Mode select MS0098-E-04 2004/03 - 13 - ASAHI KASEI [AK4114] „ Clock Source The following circuits are available to feed the clock to XTI pin of AK4114. 1) X’tal XTI AK4114 XTO Figure 10. X’tal mode Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock XTI External Clock AK4114 XTO Figure 11. External clock mode Note: Input clock must not exceed DVDD. 3) Fixed to the Clock Operation Mode 0 XTI AK4114 XTO Figure 12. off mode MS0098-E-04 2004/03 - 14 - ASAHI KASEI [AK4114] „ Sampling Frequency and Pre-emphasis Detection The AK4114 has two methods for detecting the sampling frequency as follows. 1. Clock comparison between recovered clock and X’tal oscillator 2. Sampling frequency information on channel status Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits. XTL1 0 0 1 1 XTL0 0 1 0 1 X’tal Frequency 11.2896MHz 12.288MHz 24.576MHz (Use channel status) Default Table 3. Reference X’tal frequency Except XTL1,0= “1,1” XTL1,0= “1,1” Consumer Register output fs mode Professional mode Clock comparison (Note 2) (Note 1) Byte3 Byte0 Byte4 FS3 FS2 FS1 FS0 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 0 0 0 0 44.1kHz 44.1kHz 0000 01 0000 0 0 0 1 Reserved Reserved 0001 (Others) 0 0 1 0 48kHz 48kHz 0010 10 0000 0 0 1 1 32kHz 32kHz 0011 11 0000 1 0 0 0 88.2kHz 88.2kHz (1000) 00 1010 1 0 1 0 96kHz 96kHz (1010) 00 0010 1 1 0 0 176.4kHz 176.4kHz (1100) 00 1011 1 1 1 0 192kHz 192kHz (1110) 00 0011 Note1: At least ±3% range is identified as the value in the Table 4. In case of intermediate frequency of those two, FS3-0 bits indicate nearer value. When the frequency is much bigger than 192kHz or much smaller than 32kHz, FS3-0 bits may indicate “0001”. Note2: When consumer mode, Byte3 Bit3-0 are copied to FS3-0. Table 4. fs Information The pre-emphasis information is detected and reported on PEM bit. These information are extracted from channel 1 at default. It can be switched to channel 2 by CS12 bit in control register. PEM Pre-emphasis 0 1 OFF ON Byte 0 Bits 3-5 ≠ 0X100 0X100 Table 5. PEM in Consumer Mode PEM Pre-emphasis 0 1 OFF ON Byte 0 Bits 2-4 ≠110 110 Table 6. PEM in Professional Mode MS0098-E-04 2004/03 - 15 - ASAHI KASEI [AK4114] „ De-emphasis Filter Control The AK4114 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to four sampling frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. The AK4114 goes this mode at default. Therefore, in Parallel Mode, the AK4114 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU is “0”. The internal de-emphasis filter is bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is OFF. PEM 1 1 1 1 1 0 FS3 0 0 0 1 FS2 0 0 0 0 x x FS1 0 1 1 1 FS0 0 0 1 0 x x (Others) Mode 44.1kHz 48kHz 32kHz 96kHz OFF OFF Table 7. De-emphasis Auto Control at DEAU = “1” (Default) PEM 1 1 1 1 1 1 1 1 0 DFS 0 0 0 0 1 1 1 1 x DEM1 0 0 1 1 0 0 1 1 x DEM0 0 1 0 1 0 1 0 1 x Mode 44.1kHz OFF 48kHz 32kHz OFF OFF 96kHz OFF OFF Default Table 8. De-emphasis Manual Control at DEAU = “0” „ System Reset and Power-Down The AK4114 has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4114 should be reset once by bringing PDN pin = “L” upon power-up. PDN Pin: All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= “L”. All the registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled. RSTN Bit (Address 00H; D0): All the registers except PWN and RSTN are initialized by bringing RSTN bit = “0”. The internal timings are also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is disabled. PWN Bit (Address 00H; D1): The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks are stopped. The registers are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled. MS0098-E-04 2004/03 - 16 - ASAHI KASEI [AK4114] „ Biphase Input and Through Output Eight receiver inputs (RX0-7) are available in Serial Control Mode. Each input includes amplifier corresponding to unbalance mode and can accept the signal of 200mV or more. IPS2-0 selects the receiver channel. When BCU bit = “1”, the Block start signal, C bit and U bit can output from each pins. IPS2 0 0 0 0 1 1 1 1 IPS1 0 0 1 1 0 0 1 1 IPS0 0 1 0 1 0 1 0 1 INPUT Data RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 Default Table 9. Recovery Data Select B 1/4fs COUT (or U,V) C(R191) C(L0) C(R0) C(L1) C(L31) C(R31) C(L32) (Normal mode) SDTO R190 L191 R191 L0 R190 L191 R191 L0 L30 R30 L31 LRCK (except I2 S) LRCK (I2 S) L30 R30 L31 (Mono mode) SDTO (except I2S) LRCK (except I2 S) LRCK (I2 S) Figure 13. B, C, U, V output/input timings MS0098-E-04 2004/03 - 17 - ASAHI KASEI [AK4114] „ Biphase Output The AK4114 can output either the through output(from DIR) or transmitter output(DIT; the data from DAUX is transformed to IEC60958 format.) from TX1/0 pins. Those could be selected by DIT bit. The source of the through output from TX0 could be selected among RX0-8 by OPS00,01 and 02 bits, for TX1, by OPS10,11 and 12 bits respectively. When output DAUX data, V bit could be controlled by VIN pin and first 5 bytes of C bit could be controlled by CT39-CT0 bits in control registers. When bit0= “0”(consumer mode), bit20-23(Audio channel) could not be controlled directly but be controlled by CT20 bit. When the CT20 bit is “1”, AK4114 outputs “1000” as C20-23 for left channel and output “0100” at C20-23 for right channel automatically. When CT20 bit is “0”, AK4114 outputs “0000” set as “1000” for sub frame 1, and “0100” for sub frame 2. U bits are fixed to “0”.as C20-23 for both channel. U bit could be controlled by UDIT bit as follows; When UDIT bit is “0”, U bit is always “L”. When UDIT bit is “1”, the recovered U bits are used for DIT( DIR-DIT loop mode of U bit). This mode is only available when PLL is locked and the master mode. OPS02 0 0 0 0 1 1 1 1 OPS01 0 0 1 1 0 0 1 1 OPS00 0 1 0 1 0 1 0 1 Output Data RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 Default Table 10. Output Data Select for TX0 DIT 0 0 0 0 0 0 0 0 1 OPS12 0 0 0 0 1 1 1 1 x OPS11 0 0 1 1 0 0 1 1 x OPS10 0 1 0 1 0 1 0 1 x Output Data RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 DAUX Default Table 11. Output Data Select for TX1 (Normal mode) (Mono mode) LRCK (except I2 S) LRCK (I2S) DAUX L0 R0 L1 R1 VIN R191 L0 R0 L1 L0 R0 L191/R191 L1 R1 L0/R0 L1/R1 Figure 14. DAUX and VIN input timings MS0098-E-04 2004/03 - 18 - ASAHI KASEI [AK4114] „ Double sampling frequency mode When MONO bit = “1”, the AK4114 outputs data with double speed according to “Single channel double sampling frequency mode” of AES3. For example, when 192kHz mono data is transmitted or received, L/R channels of 96kHz biphase data are used. In this case, 1 frame is 96kHz and LRCK frequency is 192kHz. 1) RX When MONO bit = “1”, AK4114 outputs mono data from SDTO as follows. 1 frame Biphase (Image) MONO = 1 A0 RX A1 LRCK (except IIS) LRCK (IIS) A0 SDTO A0 A1 A1 1 LRCK Figure 15. MONO mode (RX) Lch RX AK4114 SDTO (Master) MCKO MCLK BICK LRCK DAC (AK4394/5) SW Rch RX SDTI AK4114 SDTO (Slave) Figure 16. MONO mode Connection Example (RX) MS0098-E-04 2004/03 - 19 - ASAHI KASEI [AK4114] 2) TX When MONO bit = “1” and TLR bit = “0”, the AK4114 outputs Lch data through TX1 as biphase signal. When MONO bit = “1” and TLR bit = “1”, then Rch data. 1 LRCK LRCK (except IIS) LRCK (IIS) Serial Data A0 DAUX B0 A1 B1 MONO = 1, TLR=0 Biphase (Image) TX A0 A1 TX B0 B1 MONO = 1, TLR=1 Biphase (Image) 1 frame Figure 17. MONO mode (TX) XTI Lch XTO AK4114 DAUX (Master) TX MCKO MCLK BICK LRCK ADC (AK5394) XTI Rch TX SDATA AK4114 DAUX (Slave) Figure 18. MONO mode Connection Example (TX) Note: When the connection example (Figure 18) or multiple AK4114s are used, LRCK and BICK should be input after reset so that the phase of TX outputs is aligned. The AK4114s should be set by following sequence (Figure 19). MS0098-E-04 2004/03 - 20 - ASAHI KASEI [AK4114] Upon power on PDN pin Mode Stereo mode Mono mode Stereo mode Mono mode LRCK, BICK During operation RSTN bit Mode LRCK, BICK (1) Reset all the AK4114s by PDN pin = “L” → “H” or RSTN bit = “0” → “1”. (2) Set all the AK4114s to MONO mode while they are still in slave mode. (3) Set one of the AK4114s to master mode so that LRCK is input to all other AK4114s at the same time, or LRCK should be input to all the AK4114s at the same time. Figure 19. MONO mode setup sequence (TX) MS0098-E-04 2004/03 - 21 - ASAHI KASEI [AK4114] „ Biphase signal input/output circuit 0.1uF RX 75Ω Coax 75Ω AK4114 Figure 20. Consumer Input Circuit (Coaxial Input) Note: In case of coaxial input, if a coupling level to this input from the next RX input line pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is possible to lower the coupling level by adding this decoupling capacitor. Optical Receiver Optical Fiber 470 RX O/E AK4114 Figure 21. Consumer Input Circuit (Optical Input) In case of coaxial input, as the input level of RX line is small, in Serial Mode, be careful not to crosstalk among RX input lines. For example, by inserting the shield pattern among them. In Parallel Mode, four channel inputs (RX0,1,2,3) are available and RX4-7 change to other pins for audio format control. Those pins must be fixed to “H” or “L”. The AK4114 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure 22 is a transformer of 1:1. R1 TX 75Ω cable R2 DVSS Vdd R1 3.3V 240Ω 3.0V 220Ω T1 R2 150Ω 150Ω Figure 22. TX External Resistor Network Note: When the AK4114 is in the power-down mode (PDN= “L”), power supply current can be suppressed by using AC couple capacitor as following figure since TX1 pin output becomes uncertain at power-down mode. 0.1uF R1 TX1 75Ω cable R2 DVSS T1 MS0098-E-04 Vdd 3.3V 3.0V R1 240Ω 220Ω R2 150Ω 150Ω 2004/03 - 22 - ASAHI KASEI [AK4114] „ Q-subcode buffers The AK4114 has Q-subcode buffer for CD application. The AK4114 takes Q-subcode into registers by following conditions. 1. The sync word (S0,S1) is constructed at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit. 4. The distance between two start bits are 8-16 bits. The QINT bit in the control register goes “1” when the new Q-subcode differs from old one, and goes “0” when QINT bit is read. S0 S1 S2 S3 : S97 S0 S1 S2 S3 : 1 0 0 1 1 : 1 0 0 1 1 : 2 3 4 5 6 7 8 * 0 0 0 0 0 0 0 0… 0 0 0 0 0 0 0 0… Q2 R2 S2 T2 U2 V2 W2 0… Q3 R3 S3 T3 U3 V3 W3 0… : : : : : : : : Q97 R97 S97 T97 U97 V97 W97 0… 0 0 0 0 0 0 0 0… 0 0 0 0 0 0 0 0… Q2 R2 S2 T2 U2 V2 W2 0… Q3 R3 S3 T3 U3 V3 W3 0… : : : : : : : : ↑ Q Q2 Q3 Q4 CTRL Q5 Q6 Q7 Q8 ADRS (*) number of "0" : min=0; max=8. Figure 23. Configuration of U-bit(CD) Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 TRACK NUMBER INDEX Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 MINUTE SECOND FRAME Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73 ZERO ABSOLUTE MINUTE ABSOLUTE SECOND Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97 ABSOLUTE FRAME CRC G(x)=x^16+x^12+x^5+1 Figure 24. Q-subcode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 Q-subcode Address / Control Q9 Q8 ··· ··· ··· ··· Q3 Q2 Q-subcode Track Q-subcode Index Q17 ··· Q16 ··· ··· ··· ··· ··· ··· ··· ··· ··· Q11 ··· Q10 ··· Q-subcode Minute ··· ··· ··· ··· ··· ··· ··· ··· Q-subcode Second ··· ··· ··· ··· ··· ··· ··· ··· Q-subcode Frame ··· ··· ··· ··· ··· ··· ··· ··· Q-subcode Zero ··· ··· ··· ··· ··· ··· ··· ··· Q-subcode ABS Minute ··· ··· ··· ··· ··· ··· ··· ··· Q-subcode ABS Second ··· ··· ··· ··· ··· ··· ··· ··· Q-subcode ABS Frame Q81 Q80 ··· ··· ··· ··· Q75 Q74 Figure 25. Q-subcode register MS0098-E-04 2004/03 - 23 - ASAHI KASEI [AK4114] „ Error Handling There are the following eight events who make INT0/1 pin “H”. INT0/1 pin shows the status of following conditions. 1. UNLOCK : “1” when the PLL loses lock. AK4114 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. PAR : “1” when parity error or biphase coding error is detected, and keeps “1” until this register is read. Updated every sub-frame cycle. Reading this register resets itself. 3. AUTO : “1” when Non-PCM bitstream is detected. Updated every 4096 frames cycle. 4. DTSCD : “1” when DTS-CD bitstream is detected. Updated every DTS-CD sync cycle. 5. AUDION : “1” when the “AUDIO” bit in recovered channel status indicates “1”. Updated every block cycle. 6. PEM : “1” when “PEM” in recovered channel status indicates “1”. Updated every block cycle. 7. QINT : “1” when Q-subcode differ from old one, and keeps “1” until this register is read. Updated every sync code cycle for Q-subcode. Reading this register resets itself. 8. CINT : “1” when received C bits differ from old one, and keeps “1” until this register is read. Updated every block cycle. Reading this register resets itself. Both INT0/1 are fixed to “L” when the PLL is off (CM1,0= “01”). Once the INT0 pin goes to “H”, this pin holds “H” for 1024/fs cycles(this value can be changed by EFH0/1 bits) after those events are removed. INT1 goes to “L” at the same time when those events are removed. Each INT0/1 pins can mask those eight events individually. Once PAR, QINT and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4114 loses lock, registers regarding C-bit or U-bits are not initialized and keep previous value. 1. Parallel mode In Parallel Mode, INT0 pin outputs the ORed signal between UNLOCK and PAR, INT1 pin outputs the ORed signal among AUTO, DTSCD and AUDION. Once INT0 pin goes ”H”, it maintains “H” for 1024/fs cycles after the all error events are removed. Table 12 shows the state of each output pins when the INT0/1 pin is “H”. UNLOCK 1 0 0 x x x x Event (State of Internal Register) PAR AUTO DTSCD AUDION INT0 x x x x “H” 1 x x x 0 x x x “L” x 1 x x x x 1 x x x x 1 x 0 0 0 Table 12. Error Handling (Parallel Mode) MS0098-E-04 INT1 - Pin SDTO “L” Previous Data Output V “L” Output Output TX Output “H” - - “L” x: Don’t care 2004/03 - 24 - ASAHI KASEI [AK4114] 2. Serial mode In Serial Mode, INT0/1 pin output the ORed signal among those eight events. However, each events can be masked by each mask bits. When each bit masks those events, the event does not affect INT0/1 pin operation (those mask do not affect those resisters (UNLOCK, PAR, etc.) themselves. Once INT0 pin goes “H”, it maintains “H” for 1024/fs cycles (this value can be changed by EFH0-1 bits) after the all events are removed. Once those PAR, QINT or CINT bit goes “1”, it holds “1” until reading those registers. While the AK4114 loses lock, the channel status an Q-subcode bits are not updated and holds the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR, INT1 outputs the ORed signal among AUTO, DTSCD and AUDION. UNLOCK 1 0 0 0 0 0 0 0 PAR x 1 0 0 0 0 0 0 AUTO x x 1 x x x x x Register DTSCD AUDION PEM QINT CINT x x x x x x x x x x x x x x x 1 x x x x x 1 x x x x x 1 x x x x x 1 x x x x x 1 Table 13. Error Handling (Serial Mode) MS0098-E-04 Pin SDTO “L” Previous Data Output Output Output Output Output Output V “L” Output Output Output Output Output Output Output TX Output Output Output Output Output Output Output Output 2004/03 - 25 - ASAHI KASEI Error (UNLOCK, PAR,..) [AK4114] (Error) INT0 pin Hold Time (max: 4096/fs) INT1 pin Hold Time = 0 Register (PAR,CINT,QINT) Hold ”1” Reset Register (others) Command MCKO,BICK,LRCK (UNLOCK) READ 06H Free Run (fs: around 20kHz) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) Previous Data SDTO (others) Vpin (UNLOCK) Vpin (except UNLOCK) Normal Operation Figure 26. INT0/1 pin timing MS0098-E-04 2004/03 - 26 - ASAHI KASEI [AK4114] PD pin ="L" to "H" Initialize Read 06H INT0/1 pin ="H" No Yes Release Muting Mute DAC output Read 06H (Each Error Handling) Read 06H (Resets registers) No INT0/1 pin ="H" Yes Figure 27. Error Handling Sequence Example 1 MS0098-E-04 2004/03 - 27 - ASAHI KASEI [AK4114] PD pin ="L" to "H" Initialize Read 06H No INT1 pin ="H" Yes Read 06H and Detect QSUB= “1” (Read Q-buffer) QCRC = “0” No New data is invalid Yes INT1 pin ="L" No Yes New data is valid Figure 28. Error Handling Sequence Example (for Q/CINT) MS0098-E-04 2004/03 - 28 - ASAHI KASEI [AK4114] „ Audio Serial Interface Format The DIF0, DIF1 and DIF2 pins can select eight serial data formats as shown in Table 14. In all formats the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to 128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the last 4LSBs are auxiliary data (see Figure 29). When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4114 continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4114 output “0” from SDTO. In case of using DAUX pin, the data is transformed and output from SDTO. DAUX pin is used in Clock Operation Mode 1, 3 and unlock state of Mode 2. The input data format to DAUX should be left justified except in Mode5 and 7(Table 14). In Mode5 or 7, both the input data format of DAUX and output data format of SDTO are I2S. Mode6 and 7 are Slave Mode that is corresponding to the Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2. sub-frame of IEC958 0 3 4 preamble 7 8 11 12 27 28 29 30 31 Aux. V U C P LSB MSB MSB LSB 23 0 AK4112 Audio Data (MSB First) Figure 29. Bit configuration Mode DIF2 DIF1 DIF0 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I/O O O O O O O I I Default Table 14. Audio data format MS0098-E-04 2004/03 - 29 - ASAHI KASEI [AK4114] LRCK(0) 0 1 2 15 16 17 31 0 1 2 15 16 17 31 0 1 0 1 0 1 BICK (0:64fs) 15 14 1 0 15 14 1 0 SDTO(0) 15:MSB, 0:LSB Lch Data Rch Data Figure 30. Mode 0 Timing LRCK(0) 0 1 2 9 10 12 11 31 0 1 2 9 10 11 12 31 BICK (0:64fs) 23 22 21 20 1 0 23 22 21 20 1 0 SDTO(0) 23:MSB, 0:LSB Lch Data Rch Data Figure 31. Mode 3 Timing LRCK 0 1 2 21 22 24 23 31 0 1 2 21 22 23 24 31 BICK (64fs) 23 SDTO(0) 22 21 2 1 0 23 22 3 2 1 0 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 32. Mode 4, 6 Timing Mode4 : LRCK, BICK : Output Mode6 : LRCK, BICK : Input LRCK 0 1 2 22 24 23 25 31 0 1 2 21 22 23 24 25 31 0 1 BICK (64fs) SDTO(0) 23 22 21 2 1 23 22 0 3 2 1 0 23 23:MSB, 0:LSB Lch Data Rch Data Figure 33. Mode 5, 7 Timing MS0098-E-04 Mode5 : LRCK, BICK : Output Mode7 : LRCK, BICK : Input 2004/03 - 30 - ASAHI KASEI [AK4114] „ Serial Control Interface (1). 4-wire serial control mode (IIC= “L”) The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4114 should be reset by PDN= “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI WRITE CDTO CDTI READ CDTO C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z C1-C0: Chip Address (Fixed to “00”) R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data Figure 34. 4-wire Serial Control I/F Timing MS0098-E-04 2004/03 - 31 - ASAHI KASEI [AK4114] (2). I2C bus control mode (IIC= “H”) AK4114 supports the standard-mode I2C-bus (max : 100kHz). Then AK4114 can not be incorporated in a fast-mode I2C-bus system (max : 400kHz). (2)-1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4114 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master device. (2)-1-1. Data validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition. SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 35. Data transfer (2)-1-2. START and STOP condition A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the STOP condition. SCL SDA START CONDITION STOP CONDITION Figure 36. START and STOP conditions MS0098-E-04 2004/03 - 32 - ASAHI KASEI [AK4114] (2)-1-3. ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4114 will generates an acknowledge after each byte has been received. In the read mode, the slave, AK4114 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition. Clock pulse for acknowledge SCL FROM MASTER 1 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge Figure 37. Acknowledge on the I2C-bus (2)-1-4. FIRST BYTE The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the SDA line. The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 pin and CAD0 pin) set them. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read condition is requested by the master. A “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. 0 0 1 0 0 CAD1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins.) Figure 38. The First Byte MS0098-E-04 2004/03 - 33 - ASAHI KASEI [AK4114] (2)-2. WRITE Operations Set R/W bit = “0” for the WRITE operation of AK4114. After receipt the start condition and the first byte, the AK4114 generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4114. The format is MSB first, and those most significant 3-bits are “Don’t care”. * * * A4 A3 A2 A1 A0 (*: Don’t care) Figure 39. The Second Byte After receipt the second byte, the AK4114 generates an acknowledge, and awaits the third byte. Those data after the second byte contain control data. The format is MSB first, 8bits. D7 D6 D5 D4 D3 D2 D1 D0 Figure 40. Byte structure after the second byte The AK4114 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4114 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. S T A R T SDA Register Address(n) Slave Address Data(n) S T Data(n+x) O P Data(n+1) P S A C K A C K A C K A C K Figure 41. WRITE Operation MS0098-E-04 2004/03 - 34 - ASAHI KASEI [AK4114] (2)-3. READ Operations Set R/W bit = “1” for the READ operation of AK4114. After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4114 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. (2)-3-1. CURRENT ADDRESS READ The AK4114 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4114 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4114 discontinues transmission S T A R T SDA Slave Address Data(n) Data(n+1) S Data(n+x) T O P Data(n+2) S P A C K A C K A C K A C K Figure 42. CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4114 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4114 discontinues transmission. S T A R T SDA Slave Address S T A R T Word Address(n) S Slave Address Data(n) S Data(n+x) T O P Data(n+1) P S A C K A C K A C K A C K A C K Figure 43. RANDOM READ MS0098-E-04 2004/03 - 35 - ASAHI KASEI [AK4114] „ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H CLK & Power Down Control 01H Format & De-em Control 02H Input/ Output Control 0 03H Input/ Output Control 1 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MDTS0 MPE0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MDTS1 MPE1 MAUD1 MPAR1 UNLCK DTSCD CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN MONO DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 EFH1 EFH0 TLR DIT IPS1 IPS0 UDIT IPS2 06H Receiver status 0 QINT AUTO CINT PEM AUDION PAR 07H Receiver status 1 FS3 FS2 FS1 FS0 0 V QCRC CCRC 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0DH TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8 0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16 10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24 11H TX Channel Status Byte 4 CT39 CT39 CT39 CT39 CT39 CT39 CT39 CT32 12H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 13H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 14H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 15H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 16H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 17H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 18H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 19H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 1AH Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 1BH Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 1CH Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1DH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1EH Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1FH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”. Q74 Q-subcode ABS Second MS0098-E-04 2004/03 - 36 - ASAHI KASEI [AK4114] „ Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control R/W Default D7 CS12 R/W 0 D6 BCU R/W 1 D5 CM1 R/W 0 D4 CM0 R/W 0 D3 D2 OCKS1 OCKS0 R/W R/W 0 0 D1 PWN R/W 1 D0 RSTN R/W 1 RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down 0: Power Down 1: Normal Operation OCKS1-0: Master Clock Frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start & C/U Output Mode When BCU=1, the three Output Pins(BOUT, COUT, UOUT) become to be enabled. The block signal goes high at the start of frame 0 and remains high until the end of frame 31. CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, Pc and Pd. The de-emphasis filter is controlled by channel 1 in the Parallel Mode. Format & De-emphasis Control Addr Register Name 01H Format & De-em Control R/W Default D7 MONO R/W 0 D6 DIF2 R/W 1 D5 DIF1 R/W 1 D4 DIF0 R/W 0 D3 DEAU R/W 1 D2 DEM1 R/W 0 D1 DEM0 R/W 1 D0 DFS R/W 0 DFS: 96kHz De-emphasis Control DEM1-0: 32, 44.1, 48kHz De-emphasis Control (see Table 8.) DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable DIF2-0: Audio Data Format Control (see Table 14.) MONO: Double sampling frequency mode enable 0: Stereo mode 1: Mono mode MS0098-E-04 2004/03 - 37 - ASAHI KASEI [AK4114] Input/Output Control Addr Register Name 02H Input/ Output Control 0 R/W Default D7 TX1E R/W 1 D6 D5 D4 OPS12 OPS11 OPS10 R/W R/W R/W 0 0 0 D3 TX0E R/W 1 D2 D1 D0 OPS02 OPS01 OPS00 R/W R/W R/W 0 0 0 OPS02-00: Output Through Data Select for TX0 pin OPS12-10: Output Through Data Select for TX1 pin TX0E: TX0 Output Enable 0: Disable. TX0 outputs “L”. 1: Enable TX1E: TX1 Output Enable 0: Disable. TX1 outputs “L”. 1: Enable Addr Register Name 03H Input/ Output Control 1 R/W Default D7 EFH1 R/W 0 D6 EFH0 R/W 1 D5 UDIT R/W 0 D4 TLR R/W 0 D3 DIT R/W 1 D2 IPS2 R/W 0 D1 IPS1 R/W 0 D0 IPS0 R/W 0 IPS2-0: Input Recovery Data Select DIT: Through data/Transmit data select for TX1 pin 0: Through data (RX data). 1: Transmit data (DAUX data). TLR: Double sampling frequency mode channel select for DIT(stereo) 0: L channel 1: R channel UDIT: U bit control for DIT 0: U bit is fixed to “0” 1: Recovered U bit is used for DIT (loop mode for U bit) EFH1-0: Interrupt 0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK 10: 2048 LRCK 11: 4096 LRCK MS0098-E-04 2004/03 - 38 - ASAHI KASEI [AK4114] Mask Control for INT0 Addr Register Name 04H INT0 MASK R/W Default D7 MQI0 R/W 1 D6 MAT0 R/W 1 D5 MCI0 R/W 1 D4 MUL0 R/W 0 D3 MDTS0 R/W 1 D2 MPE0 R/W 1 D1 MAN0 R/W 1 D0 MPR0 R/W 0 D5 MCI1 R/W 1 D4 MUL1 R/W 1 D3 MDTS1 R/W 0 D2 MPE1 R/W 1 D1 MAN1 R/W 0 D0 MPR1 R/W 1 MPR0: Mask Enable for PAR bit MAN0: Mask Enable for AUDN bit MPE0: Mask Enable for PEM bit MDTS0: Mask Enable for DTSCD bit MUL0: Mask Enable for UNLOCK bit MCI0: Mask Enable for CINT bit MAT0: Mask Enable for AUTO bit MQI0: Mask Enable for QINT bit 0: Mask disable 1: Mask enable Mask Control for INT1 Addr Register Name 05H INT1 MASK R/W Default D7 MQI1 R/W 1 D6 MAT1 R/W 0 MPR1: Mask Enable for PAR bit MAN1: Mask Enable for AUDN bit MPE1: Mask Enable for PEM bit MDTS1: Mask Enable for DTSCD bit MUL1: Mask Enable for UNLOCK0 bit MCI1: Mask Enable for CINT bit MAT1: Mask Enable for AUTO bit MQI1: Mask Enable for QINT bit 0: Mask disable 1: Mask enable MS0098-E-04 2004/03 - 39 - ASAHI KASEI [AK4114] Receiver Status 0 Addr Register Name 06H Receiver status 0 R/W Default D7 QINT RD 0 D6 AUTO RD 0 D5 CINT RD 0 D4 D3 UNLCK DTSCD RD RD 0 0 D2 PEM RD 0 D1 AUDION RD 0 D0 PAR RD 0 D2 V RD 0 D1 QCRC RD 0 D0 CCRC RD 0 PAR: Parity Error or Biphase Error Status 0:No Error 1:Error It is “1” if Parity Error or Biphase Error is detected in the sub-frame. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. PEM: Pre-emphasis Detect. 0: OFF 1: ON This bit is made by encoding channel status bits. DTSCD: DTS-CD Auto Detect 0: No detect 1: Detect UNLCK: PLL Lock Status 0: Locked 1: Out of Lock CINT: Channel Status Buffer Interrupt 0: No change 1: Changed AUTO: Non-PCM Auto Detect 0: No detect 1: Detect QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed QINT, CINT and PAR bits are initialized when 06H is read. Receiver Status 1 Addr Register Name 07H Receiver status 1 R/W Default D7 FS3 RD 0 D6 FS2 RD 0 D5 FS1 RD 0 D4 FS0 RD 1 D3 0 RD 0 CCRC: Cyclic Redundancy Check for Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check for Q-subcode 0:No Error 1:Error V: Validity of channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (see Table 4.) MS0098-E-04 2004/03 - 40 - ASAHI KASEI [AK4114] Receiver Channel Status Addr 08H 09H 0AH 0BH 0CH Register Name RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 R/W Default D7 CR7 CR15 CR23 CR31 CR39 D6 CR6 CR14 CR22 CR30 CR38 D5 CR5 CR13 CR21 CR29 CR37 D4 CR4 CR12 CR20 CR28 CR36 D3 CR3 CR11 CR19 CR27 CR35 D2 CR2 CR10 CR18 CR26 CR34 D1 CR1 CR9 CR17 CR25 CR33 D0 CR0 CR8 CR16 CR24 CR32 D2 CT2 CT10 CT18 CT26 CT34 D1 CT1 CT9 CT17 CT25 CT335 D0 CT0 CT8 CT16 CT24 CT32 D2 PC2 PC10 PD2 PD10 D1 PC1 PC9 PD1 PD9 D0 PC0 PC8 PD0 PD8 RD Not initialized CR39-0: Receiver Channel Status Byte 4-0 Transmitter Channel Status Addr 0DH 0EH 0FH 10H 11H Register Name TX Channel Status Byte 0 TX Channel Status Byte 1 TX Channel Status Byte 2 TX Channel Status Byte 3 TX Channel Status Byte 3 R/W Default D7 CT7 CT15 CT23 CT31 CT39 D6 CT6 CT14 CT22 CT30 CT38 D5 CT5 CT13 CT21 CT29 CT37 D4 D3 CT4 CT3 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 R/W 0 CT39-0: Transmitter Channel Status Byte 4-0 Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr 12H 13H 14H 15H Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default D7 PC7 PC15 PD7 PD15 D6 PC6 PC14 PD6 PD14 D5 PC5 PC13 PD5 PD13 D4 PC4 PC12 PD4 PD12 D3 PC3 PC11 PD3 PD11 RD Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 MS0098-E-04 2004/03 - 41 - ASAHI KASEI [AK4114] Q-subcode Buffer Addr 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame R/W Default D7 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 Q81 D6 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 D5 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 D4 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 D3 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 D2 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 D1 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 D0 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74 RD Not initialized MS0098-E-04 2004/03 - 42 - ASAHI KASEI [AK4114] „ Burst Preambles in non-PCM Bitstreams sub-frame of IEC958 0 3 4 preamble 7 8 Aux. 11 12 27 28 29 30 31 LSB MSB V U C P 16 bits of bitstream 0 Pa Pb Pc Pd 15 Burst_payload stuffing repetition time of the burst Figure 44. Data structure in IEC60958 Preamble word Pa Pb Pc Pd Length of field Contents 16 bits sync word 1 16 bits sync word 2 16 bits Burst info 16 bits Length code Table 15. Burst preamble words MS0098-E-04 Value 0xF872 0x4E1F See Table 16 Numbers of bits 2004/03 - 43 - ASAHI KASEI Bits of Pc Value 0-4 5, 6 7 8-12 13-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 0 0 1 0 [AK4114] Contents Repetition time of burst in IEC60958 frames data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to “0” ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 Table 16. Fields of burst info Pc MS0098-E-04 2004/03 - 44 - ASAHI KASEI [AK4114] „ Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames, PDN pin Bit stream Pa Pb Pc1 Pd1 Pa Pb Pc2 Pd2 Repetition time Pa Pb Pc3 Pd3 >4096 frames AUTO bit Pc Register “0” Pd Register “0” Pc1 Pc2 Pd1 Pc3 Pd2 Pd3 Figure 45. Timing example 1 2) When Non-PCM bitstream stops (when MULK0=0), INT0 hold time INT0 pin